JPH0869389A - Semiconductor testing device - Google Patents

Abstract

PURPOSE: To improve working efficiency and to perform a test with high efficiency by indirectly finding a stored test condition based on the test condition indirect designation data of a set instruction with respect to stored test sequence and executing a test program. CONSTITUTION: This device is provided with a data storage unit 12 to store the set data (test condition) of a semiconductor device to be tested, and a sequence storage unit 13 to store the execution sequence of the test item of the semiconductor device to be tested that is the test program. The test program can be constituted of the set data and the set instruction with respect to the test sequence stored in those units 12, 13. The test of the semiconductor device to be tested is performed by indirectly designated set data based on the test condition indirect designation data of the set instruction with respect to the test sequence. Therefore, it is not required to generate a similar test program repeatedly and the test program can easily be generated only by changing the set data in the storage unit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test device for inspecting a semiconductor device.

[0002]

2. Description of the Related Art FIG. 14 shows a conventional semiconductor test apparatus 10.
It is a whole block diagram which shows 0. In the figure, 1 is a control unit for controlling the operation of the semiconductor test apparatus 100, 2 is an input / output unit for giving instructions to the semiconductor test apparatus 100 and displaying test results, and 3 is a test condition and a judgment condition for each test item. A storage unit for storing a test program, a power supply unit 4 for supplying a voltage for operating a semiconductor device under test 5, a relay control unit 5 for controlling a relay existing on a peripheral circuit of the semiconductor device under test 11, 6a to 6h is a signal generation / measurement unit for generating a signal to be given to the semiconductor device under test 11 and measuring a signal output from the semiconductor device under test 11, and 7 is a terminal of the semiconductor device under test and an input / output terminal of the semiconductor test device 100. The peripheral circuit portions, 8a to 8j, for connecting to and are input to the semiconductor device 11 to be inspected, or the semiconductor device 11 to be inspected. Input / output terminals of the semiconductor test device for taking in signals output from the semiconductor test device, and 9a to 9g are signal lines connecting the terminals of the semiconductor device under test 11 and the input / output terminals 8a to 8j of the semiconductor test device 100. Reference numeral 10 denotes a relay which is present on the peripheral circuit of the semiconductor device under test 11 and is connected between the semiconductor device under test 11 and the input / output terminal 8i of the semiconductor test device 100.

FIG. 16 is a flow chart showing the inspection procedure of the semiconductor device 11 to be inspected by the semiconductor test device 100. Next, the operation when inspecting the semiconductor device 11 to be inspected will be described with reference to this flowchart. First, a test condition for a predetermined test item of the semiconductor device under test 11 (this test item is determined at the design stage of the semiconductor device under test 11) is created by a test program of the semiconductor test device. This test program is created by inputting from the input / output device of the input / output unit 2 (step ST1) and stored in the storage unit 3 (step ST2).

FIG. 15 is an explanatory diagram showing a test program in which test conditions and judgment conditions for each test item are described. The description of the test program will be described here. For the description of the test program, a dedicated language for a semiconductor test device or a general-purpose high-level language is usually used. In this case, C language is used. The setting of the test conditions for the power supply unit 4, the relay control unit 5, and the signal generation / measurement units 6a to 6h of the semiconductor test device is performed by using a function prepared beforehand (stored as a system program in the semiconductor test device). To use.

As an example of setting to each unit, for example, in the power supply unit 4, as shown in FIG. 15, vps (1,5.
0v), the output voltage is 5v in the first power supply unit.
Set.

Further, in the relay control unit 5, eight relays are turned on by the description of dataout (0xff00), for example. That is, this semiconductor test device is supposed to be able to control up to 16 relays existing on the peripheral circuit of the semiconductor device to be inspected, and if the hexadecimal number "ff00" is converted into binary number bits and converted to 16b.
It becomes the data of it, and each bit controls one relay corresponding to each bit. When one bit is set to "1", one relay is turned on, so that eight relays are turned on in the hexadecimal data "ff00".

The signal generation / measurement units 6a to 6h are also included.
Then, for example, by describing asgnset (pin), which signal generation / measurement unit to use is set by the argument data. In this case, a variable called pin is used. This variable can be set for 32 pins (units), and each bit is data for 1 pin.

Returning to FIG. 16, when the test program thus created is stored in the storage unit 3, it is judged whether or not the test program creation is completed (step ST3). When there are a plurality of test items, the operations from step ST1 to step ST3 are repeated so that all the test items can be tested, and the creation of the test program capable of testing all the test items is completed. When the creation of the test program is completed, the control unit 1 reads the test program for one test item stored in the storage unit 3, and according to the description content, the power supply unit 4, the relay control unit 5, the signal generation / measurement unit 6
Data is sent to a to 6h to set test conditions (step ST4). Next, the control unit 1 includes the power supply unit 4,
Relay control unit 5, signal generation / measurement unit 6a-
An instruction to start the test is output to 6h (step ST5).

The control unit 1 includes a power supply unit 4, a relay control unit 5, signal generation / measurement units 6a to 6h.
When the test is completed, the test completion signal is sent from each unit, so it is determined whether the test in each unit is completed (step ST6), and the test data obtained as a result of the test is regarded as the expected value. It is determined whether or not the result is obtained, and the determination result is obtained (step ST7). Then, the judgment result and the test result are displayed and output on the input / output unit 2 (step ST8). Then, it is further determined whether or not there is the next test item (step ST9),
The operations from step ST4 to step ST9 are repeated until all the test items are completed.

[0010]

Since the conventional semiconductor test apparatus is configured as described above, the structure of the test program has a setting order for each unit when the test conditions of the semiconductor test apparatus are created ( Relay settings → Power settings → Which signal generation / measurement unit to use ...
・ Order and etc.) and setting data for those units (specific values indicating test conditions such as which relay is turned on and what voltage the output voltage of the power supply is set to) are integrally described. There is a problem that the test programs cannot be separated and the test program cannot be created unless the setting order and the setting data are determined.

In the case of testing a semiconductor device, even if the type of the semiconductor device to be inspected changes, the test items and test order are almost the same, and only the setting data is changed according to the semiconductor device to be inspected. In spite of many cases, there was a problem that almost the same test program with only different setting data had to be created again.

Furthermore, in semiconductor devices such as ICs,
In many cases, the pin arrangement and external shape are different even if the ICs of the same type are used. When testing such ICs of the same type, the same test program is used for the purpose of shortening the test program creation time. The peripheral circuit section 7 is separately prepared and tested to change the connection of the signal lines of the peripheral circuits of the IC to deal with the problem. In this case, the input / output terminals 8a to 8j of the semiconductor test apparatus 100 are handled. Since the position of does not change, the length of the signal line connecting between the input / output terminals 8a to 8j and the terminal of the IC to be tested may change, and accordingly, the semiconductor test device tries to test. As a result of the delay of the signal supplied to the IC, the signal timing is delayed, and it is necessary to determine the signal timing setting value in consideration of the delay amount according to the length of the signal line. The results can not be obtained.

To reduce the accuracy of the test result, it is advisable to connect the IC pin terminal and the input / output terminal located at the shortest distance with the signal line so that the signal line does not become long. Well, if you do this, you will have to modify the test program. If the test program is modified, there will be multiple test programs corresponding to different terminal arrangements and external shapes for the same type of IC, and it will take time to maintain the test program due to changes in test items. There is a problem that the error due to the error occurs in the test program and the quality of the test program deteriorates.

The invention of claim 1 has been made to solve the above-mentioned problems, and a semiconductor test apparatus capable of improving the work efficiency when creating a similar test program and performing an efficient test. Aim to get.

According to the second aspect of the invention, it is possible to flexibly deal with the change of the signal line for connecting with the semiconductor device to be inspected, and to improve the work efficiency in creating the test program for the semiconductor device to be inspected having different terminal arrangements. It is an object of the present invention to obtain a semiconductor test device capable of improving and efficiently performing a test and performing a highly reliable test.

According to a third aspect of the present invention, the semiconductor device to be inspected can flexibly deal with the change of the signal line for connection with the semiconductor device to be inspected, and has a work efficiency in creating a similar test program and a different terminal arrangement. An object of the present invention is to obtain a semiconductor test device capable of improving the work efficiency in creating a test program for the device and performing the test efficiently and performing the test with high reliability.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor test device which stores a sequence storage unit in which a setting command relating to a test order of a semiconductor device under test is stored and a test condition of the semiconductor device under test. And a control for indirectly determining the test condition stored in the data storage unit based on the test condition indirect designation data of the setting instruction related to the test order stored in the sequence storage unit. And means.

According to a second aspect of the present invention, there is provided a semiconductor test device in which a pin assignment table storing terminal connection information indicating a correspondence relationship between a terminal of a semiconductor device to be inspected and a terminal of an inspection unit side, and the pin. A control unit for setting the test condition directly described in the test program stored in the storage unit to the inspection unit corresponding to the terminal of the semiconductor device under test based on the terminal connection information of the assignment table Is.

According to a third aspect of the present invention, there is provided a semiconductor test device in which a sequence storage unit in which a setting command regarding a test order of a semiconductor device under test is stored and a data storage unit in which data regarding a test condition of the semiconductor device under test is stored. And a pin assignment table storing the terminal connection information indicating the correspondence between the terminals of the semiconductor device under test and the terminals on the inspection unit side, and based on the terminal connection information of the pin assignment table. A test obtained from the data storage unit, which is indirectly designated by the test condition indirect designation data of the setting instruction regarding the test order stored in the sequence storage unit, to the inspection unit corresponding to the terminal of the semiconductor device under test. And a control means for setting conditions.

[0020]

The control means of the semiconductor test apparatus according to the invention of claim 1 does not interpret the test program as a set instruction relating to the test sequence and the data relating to the test conditions as a unit, but rather the test sequence stored in the sequence storage unit. Related to the test condition indirectly specified data of the setting command, the test condition stored in the data storage unit is indirectly obtained and the test program is executed. Therefore, the data related to the test condition can be independently created. Therefore, the content of the test program is changed only by changing the test conditions, the work efficiency in creating a similar test program is improved, and the test can be efficiently performed.

According to a second aspect of the present invention, the control means of the semiconductor test device sets the test condition directly described in the test program to the inspection unit corresponding to the terminal of the semiconductor device under test according to the terminal connection information of the pin assignment table. Therefore, the change of the contents of the test program is replaced with the change of the terminal connection information of the pin assignment table, the change of the contents of the test program is facilitated, and the change of the signal line for connecting with the semiconductor device under test is changed. (EN) It is possible to flexibly deal with the semiconductor device to be inspected having different terminal arrangements, improve the work efficiency in creating a test program, perform an efficient test, and realize a highly reliable test.

According to a third aspect of the present invention, the control means of the semiconductor test device is based on the terminal connection information indicating the correspondence between the terminals of the semiconductor device to be inspected and the terminals on the inspection unit side, based on the terminal connection information. Data relating to the test conditions obtained from the data storage unit indirectly designated by the test condition indirect designation data of the setting instruction relating to the test order stored in the sequence storage unit is used as the inspection unit corresponding to the terminal of the semiconductor device under test. To facilitate changes in the contents of the test program and to flexibly respond to changes in the signal lines that connect to the semiconductor device under test, and to improve work efficiency and different terminal layout when creating similar test programs. Improves work efficiency when creating a test program for the semiconductor device to be inspected, resulting in high efficiency and high reliability To realize the experience.

[0023]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing a semiconductor test apparatus 200 of this embodiment. In FIG. 1, parts that are the same as or correspond to those in FIG. 14 are given the same reference numerals and description thereof is omitted. In the figure, 12 is a data storage unit for storing setting data (test conditions) of the semiconductor device to be inspected, and 13 is a sequence storage unit for storing the execution order of test items of the semiconductor device to be inspected, which is a test program.

The control unit 1 corresponds to the control means, the input / output unit 2 corresponds to the input means, and the signal generation /
The measurement units 6a to 6h correspond to the inspection unit.

FIG. 2 shows a semiconductor test apparatus 20 of this embodiment.
10 is a flowchart showing the operation of No. 0, and the operation will be described below based on this flowchart. First, a test program for determining a test method according to predetermined test items of the semiconductor device 11 to be inspected is created (step ST11). FIG. 3 is an explanatory diagram showing a description example of a test program according to the determined test method. FIG.
Compared to the conventional test program description example shown in FIG. 15, the description example shown in FIG. 15 does not have concrete data description in the argument part of each setting instruction, and the reference destination is the test condition indirect designation data 1
4b. A setting command for this test program is input from the input / output unit 2 and stored in the sequence storage unit 13 (step ST12).

When the test program based on the setting command thus created is stored in the sequence storage unit 13, it is judged whether or not the test program creation is completed (step ST13). If there are multiple test items, step S so that all test items can be tested.
The operation from T11 to step ST13 is repeated to complete the creation of the test program in which all the test items can be tested.

In this case, it is not necessary to input duplicate test methods for the test items that can be tested by the same test method and only the setting data is changed. Further, even in the case where the test method is the same as the test method stored in the sequence storage unit 13 based on the test order setting command, it is not necessary to input the test method. Even if the type of the semiconductor device to be inspected changes, the type of test item (the item to be tested or the type of test method) is often the same, and in most cases, it relates to the test order already stored in the sequence storage unit 13. The test program can be diverted by the setting command.

When the creation of the test program is completed, the setting data for each test item is then input from the input / output unit 2 (step ST14). The input setting data is stored in the data storage unit 12 (step ST15). FIG. 3 shows a description example of a test program relating to the test data stored in the sequence storage unit 13 and the setting data stored in the data storage unit 12.

Next, the control unit 1 reads out a test program for one test item from the data storage unit 12 and the sequence storage unit 13, and according to the description contents, the power supply unit 4, the relay control unit 5, the signal generation / measurement. Data is sent to the units 6a to 6h to set test conditions (step ST16). One test item at this time includes data indicating which test method is used to execute the test. This is a part of the test method: function shown in 14a of FIG. Which test method of the test program in the sequence storage unit 13 to use is determined.

Next, the control unit 1 includes the power supply unit 4,
Relay control unit 5, signal generation / measurement unit 6a-
An instruction to start the test is output to 6h (step ST1).
7).

The control unit 1 includes a power supply unit 4, a relay control unit 5, signal generation / measurement units 6a to 6h.
When the test is completed, a signal of test completion is sent from each unit. Therefore, it is determined whether the test in each unit is completed (step ST18), and whether each test data is the expected value or not is determined. Judgment is made and the judgment result is obtained (step ST19). And the judgment result,
The test result is displayed and output on the input / output unit 2 (step ST20). Further, it is determined whether or not there is the next test item (step ST21), and the processes from step ST16 to step ST21 are repeated until all the test items are completed.

As described above, according to the present embodiment, the test program is composed of the setting data stored in the data storage unit 12 and the setting command relating to the test order stored in the sequence storage unit 13, and the test order is set. Semiconductor device 1 to be inspected according to the setting data indirectly specified based on the test condition indirect specifying data of the setting instruction regarding
Since the test No. 1 is performed, it is not necessary to repeatedly create a similar test program for each semiconductor device to be inspected, and a similar test program can be easily and simply changed by changing the setting data stored in the data storage unit 12. Can be created in time.

Example 2. FIG. 4 is an overall configuration diagram showing the semiconductor test apparatus 300 of this embodiment. In FIG. 4, parts that are the same as or equivalent to those in FIG. 14 are given the same reference numerals and description thereof is omitted. In the figure, reference numeral 15 denotes terminals on the signal generation / measurement units 6a to 6h side of the semiconductor test device 300 (terminals on the inspection unit side) and the semiconductor device 11 under test.
3 is a pin assignment table that stores terminal connection information indicating a connection relationship of terminals A to D on the semiconductor device side to be inspected.

FIG. 7 shows terminals A to A of the semiconductor device 11 to be inspected.
D and terminals on the signal generation / measurement units 6a to 6h side
4 shows a pin assignment table that stores terminal connection information when the and are connected as shown in FIG. 4, and FIG.
Pins storing terminal connection information when the semiconductor device 17 to be inspected, in which D is arranged in a pattern shown in FIG. 6, is connected to terminals on the signal generation / measurement units 6a to 6h side as shown in FIG. The assignment table is shown.

FIG. 10 shows a semiconductor test apparatus 3 of this embodiment.
00 is a flowchart showing the operation of No. 00, and the operation will be described below based on this flowchart. In the flowchart shown in FIG. 10, the same processing steps as those in the flowchart of FIG. In this embodiment, the test program created in step ST20 is stored in the storage unit 3, and in step ST21, the terminals of the signal generation / measurement units 6a to 6h of the semiconductor test apparatus 300 and the terminals of the semiconductor device to be inspected A to. A pin assignment table that stores terminal connection information indicating the connection relationship with D is created.

When the semiconductor device under test is the semiconductor device under test 11 having a terminal arrangement as shown in FIG. 4, the pin assignment table is created by using terminals A and terminals, terminals B and terminals, terminals C and terminals. By connecting the terminal D and the terminal with a signal line, the length of the signal line can be minimized, and the pin assignment table created at this time is as shown in FIG. When the semiconductor device to be inspected is the semiconductor device 17 to be inspected having the terminal arrangement as shown in FIG. 6, the terminal A and the terminal, the terminal B and the terminal, the terminal C and the terminal, and the terminal D and the terminal are signal lines. The length of the signal line can be minimized by connecting with, and the pin assignment table created at this time is as shown in FIG.

Therefore, when the semiconductor device to be inspected is the semiconductor device to be inspected 17 shown in FIG. 5 or 6 having a terminal arrangement different from that of the semiconductor device to be inspected 11 as shown in FIG. And the terminal C, the terminal C and the terminal, and the terminal D and the terminal are connected by a signal line, the length of the signal line becomes long as shown in FIG. 5, and the connection by such a signal line increases the delay amount in the signal line. Since the test results are adversely affected, the pin assignment table has a terminal connection indicating the connection relationship between the terminals on the signal generation / measurement units 6a to 6h side and the terminals A to D on the semiconductor device side as shown in FIG. Set the information.

Returning now to FIG. 10, in step ST22, the control unit 1 stores 1 stored in the storage unit 3.
The test programs for the test items are read out, data is sent to the power supply unit 4, the relay control unit 5, the signal generation / measurement units 6a to 6h according to the description contents of the test program, and the test conditions are set. In this case, the data (variable pin) indicating the terminals of the semiconductor device to be inspected in the test program are described by the terminal names A to D on the side of the semiconductor device to be inspected. FIG. 9 is an explanatory diagram showing a description example of this test program. In the pin assignment table, the terminal connection information shown in FIG. 7 or FIG. 8 is set according to the terminal arrangement of the semiconductor device under test, so that the control unit 1 generates the signal generated / connected to any of the terminals. What kind of test condition should be set in the measuring unit is determined based on the pin assignment table.

As described above, according to this embodiment, by changing the pin assignment table, the connection relationship between the terminals on the semiconductor device to be inspected side and the terminals on the signal generating / measuring units 6a to 6h side is changed. The test program can be easily changed with respect to the change of the terminal arrangement on the semiconductor device side to be inspected, and the work efficiency at the time of creating a test program for the semiconductor device to be inspected having a different terminal arrangement can be improved and improved efficiently. It is possible to perform a test with high reliability.

Example 3. FIG. 11 is an overall configuration diagram showing the semiconductor test apparatus 400 of this embodiment. 11, parts that are the same as or correspond to those in FIGS. 1 and 4 are given the same reference numerals and description thereof is omitted. FIG. 12 is an explanatory diagram showing a description example of the test program used in this embodiment. FIG. 13 is a flowchart showing the operation of the semiconductor test apparatus 400 of this embodiment, and the operation will be described below based on this flowchart. In the flowchart shown in FIG. 13, the same processing steps as those in the flowcharts of FIGS. 2 and 10 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the control unit 1 stores the test programs for one test item in the data storage unit 1.
2 and the sequence storage unit 13 are read out, data is sent to the power supply unit 4, the relay control unit 5, and the signal generation / measurement units 6a to 6h in accordance with the description contents, and the test conditions are set. The data for each terminal of the semiconductor device under test 17 in the test program in this case is described by the terminal names A to D on the side of the semiconductor device under test. An example of this description is shown in the assignment data part 19 in the setting data description of the test program in FIG. Therefore, the control unit 1 refers to the pin assignment table 15 to determine what kind of test conditions should be set for the signal generation / measurement units connected to the terminals (step ST).
31). As the pin assignment table in this case, the one in which the terminal connection information shown in FIG. 8 is stored is used.

As described above, according to this embodiment, a similar test program can be easily created in a short time only by changing the setting data and the pin assignment table stored in the data storage unit 12, and the semiconductor under test can be inspected. The device is a semiconductor device to be inspected 17 to a semiconductor device to be inspected 11 shown in FIG.
If the pin assignment table 15 is changed to the one shown in FIG. 7, the semiconductor device 11 to be inspected can be tested.

[0043]

As described above, according to the first aspect of the present invention, the test condition stored in the data storage unit is set based on the test condition indirect designation data of the setting instruction related to the test order stored in the sequence storage unit. Since the control means for indirectly setting the required inspection unit is provided,
There is an effect that it is possible to easily change the contents of the test program, improve the work efficiency at the time of creating a similar test program, and obtain a semiconductor test device that can perform a test efficiently.

According to the second aspect of the present invention, the test program stored in the storage means is directly written in the inspection unit corresponding to the terminal of the semiconductor device to be inspected, based on the terminal connection information of the pin assignment table. Since it is configured to have a control means for setting the test conditions, it is possible to easily change the contents of the test program and flexibly respond to the connection change of the signal line connecting between the semiconductor device under test and the terminal on the inspection unit side. A semiconductor test device capable of improving work efficiency when creating a test program for a semiconductor device to be inspected having different terminal arrangements, capable of performing an efficient test and a highly reliable test can be obtained. There is an effect that can be done.

According to the third aspect of the present invention, based on the terminal connection information of the pin assignment table, the test unit corresponding to the terminal of the semiconductor device under test is tested for the setting command related to the test order stored in the sequence storage unit. Since the control means for indirectly setting the data related to the test condition, which is indirectly specified by the condition indirectly specifying data and obtained by referring to the data storage unit, is provided, the contents of the test program can be easily changed, and It can flexibly respond to changes in the signal line that connects to the test semiconductor device, efficiently test semiconductor devices under test that have different terminal arrangements, and realize highly reliable tests. There is an effect that it is possible to obtain a semiconductor test device with improved work efficiency in creating a program.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing a semiconductor test device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the semiconductor test device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a description example of a test program by setting data stored in a data storage unit of a semiconductor test device according to an embodiment of the present invention and a setting command regarding a test order stored in a sequence storage unit. .

FIG. 4 is an overall configuration diagram showing a semiconductor test device according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a connection state between a semiconductor device to be inspected having a different terminal arrangement and terminals on the inspection unit side in the semiconductor test device according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a connection state between a semiconductor device to be inspected having different terminal arrangements and terminals on the inspection unit side in the semiconductor test device according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a pin assignment table in the semiconductor test device according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a pin assignment table in the semiconductor test device according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a description example of a test program stored in a storage unit of a semiconductor test device according to an embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of the semiconductor test device according to the embodiment of the present invention.

FIG. 11 is an overall configuration diagram showing a semiconductor test device according to an embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a description example of a test program used in the semiconductor test device according to the embodiment of the present invention.

FIG. 13 is a flowchart showing the operation of the semiconductor test device according to the embodiment of the present invention.

FIG. 14 is an overall configuration diagram showing a conventional semiconductor test device.

FIG. 15 is an explanatory diagram showing a description example of a test program of a conventional semiconductor test device.

FIG. 16 is a flowchart showing an inspection procedure of a semiconductor device to be inspected by a conventional semiconductor test device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 control unit (control means), 2 input / output units (input means), 6a-6h signal generation / measurement unit (inspection unit), 11, 17 semiconductor device to be inspected, 1
2 data storage unit, 13 sequence storage unit, 14b test condition indirect designation data, 15-pin assignment table, A, B, C, D terminals on semiconductor device side to be tested, ~ terminals (terminals on inspection unit side), 20
0,300,400 Semiconductor test equipment.

Claims (3)

[Claims] 1. A plurality of inspection units in which a test condition for inspecting a semiconductor device to be inspected is set, and a test order of the semiconductor device to be inspected by each of the inspection units and the test condition are set in the inspection unit. Input means for inputting a test program, a storage means for storing the test program input and generated by the input means, and the semiconductor devices to be inspected in the test order according to the test conditions set in the inspection unit. A control means for inspecting, and a signal generated based on a test condition set for each of the inspection units and used for testing the semiconductor device under test is given to the semiconductor device under test according to the test order. Sometimes the test data obtained from the semiconductor device to be inspected is compared with an expected value to inspect the semiconductor device to be inspected. In the conductor test apparatus, the storage means is composed of a sequence storage unit in which a setting command regarding a test order of the semiconductor device under test is stored and a data storage unit in which test conditions of the semiconductor device under test are stored, and the control is performed. Means for obtaining and setting in the inspection unit by referring to the test condition stored in the data storage unit based on the test condition indirect designation data of the setting instruction related to the test order stored in the sequence storage unit. Test equipment. 2. A plurality of inspection units in which a test condition for inspecting a semiconductor device to be inspected is set, and a test order of the inspected semiconductor device by each of the inspection units and the test condition are set in the inspection unit. Input means for inputting a test program, a storage means for storing the test program input and generated by the input means, and the semiconductor devices to be inspected in the test order according to the test conditions set in the inspection unit. A control means for inspecting, and a signal generated based on a test condition set for each of the inspection units and used for testing the semiconductor device under test is given to the semiconductor device under test according to the test order. Sometimes the test data obtained from the semiconductor device to be inspected is compared with an expected value to inspect the semiconductor device to be inspected. In the conductor test apparatus, a pin assign table storing terminal connection information indicating a correspondence relationship when the terminal on the semiconductor device side to be inspected and the terminal on the inspection unit side are connected is provided, and the control means is the pin assign table. The semiconductor test device is characterized in that the test condition directly described in the test program stored in the storage means is set to the inspection unit corresponding to the terminal of the semiconductor device to be inspected, based on the terminal connection information. 3. A plurality of inspection units in which a test condition for inspecting a semiconductor device to be inspected is set, and a test order of the inspected semiconductor device by each of the inspection units and the test condition are set in the inspection unit. Input means for inputting a test program, a storage means for storing the test program input and generated by the input means, and the semiconductor devices to be inspected in the test order according to the test conditions set in the inspection unit. A control means for inspecting, and a signal generated based on a test condition set for each of the inspection units and used for testing the semiconductor device under test is given to the semiconductor device under test according to the test order. Sometimes the test data obtained from the semiconductor device to be inspected is compared with an expected value to inspect the semiconductor device to be inspected. In the conductor test apparatus, the storage means is composed of a sequence storage unit in which a setting command related to a test order of the semiconductor device under test is stored and a data storage unit in which test conditions of the semiconductor device under test are stored. A pin assignment table storing terminal connection information indicating a correspondence relationship between the terminals on the semiconductor device side to be inspected and the terminals on the inspection unit side is provided, and the control means includes terminals of the pin assignment table. From the data storage unit to the inspection unit corresponding to the terminal of the semiconductor device to be inspected based on the connection information, indirectly designated by the test condition indirect designation data of the setting instruction regarding the test order stored in the sequence storage unit. Semiconductor test equipment characterized by setting test conditions obtained by reference .