JPH0855024A - Instruction decoder circuit - Google Patents

Abstract

PURPOSE:To provide an instruction decoder circuit capable of maintaining a succession property with the decoder circuit of a conventional computer at the time of adding a new instruction to the redundant part of an instruction code provided with redundancy. CONSTITUTION:The decoder circuit of a microcomputer is provided with a first instruction code part 14 corresponding to the instruction code provided with the redundant part on an instruction map and a second instruction code part composed of an AND circuit 11 for responding to the specified instruction code included in the redundant part of the instruction code provided with the redundant part and a counter 12 for detecting that the output signals of the AND circuit 11 are successively generated for the prescribed number of times and outputting a specified instruction. The counter 12 is reset by the generation of the instruction code other than the specified instruction code. The instruction corresponding to the specified instruction code included in the redundant part is prevented from being erroneously outputted along with the inputted instruction code at the time of inputting the instruction code provided with the redundancy in a succeeded software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer instruction decoder circuit, and more particularly to a circuit structure of an instruction decoder for decoding a multi-bit instruction system having redundant instructions on an instruction map.

[0002]

2. Description of the Related Art An instruction decoder circuit of a conventional microcomputer will be described with reference to FIG. This figure shows
This is an instruction system map which has redundant instruction codes in part on the instruction map, each instruction code being composed of 8 bits. I7 to I, which form the upper 4 bits
Each instruction code is composed of a combination of 4 bits and I3 to I0 bits forming the lower 4 bits.

In FIG. 3, the upper 4 bits and the lower 4 bits are displayed in hexadecimal notation (hexadecimal display) of 0 to F to form a map. For example, the instruction “ADD_A, #n
"4" indicates an instruction for performing an addition operation on the accumulator A and the 4-bit immediate data included in the instruction code and storing the sum in the accumulator A. This instruction is mapped to "0x (hexadecimal display)" = "0000xxxx (binary display)" on the map. Here, x is an arbitrary number.

FIG. 4 shows a partial circuit configuration of a decoder circuit for decoding the instruction system displayed in the mapping manner. For example, the instruction “ADD_A, #n
4 ”is (I) for each bit I7 to I0 of the instruction code.
7, I6, I5, I4, I3, I2, I1, I0) = "
0000 × XXX × ”input. When this instruction code is input, it is decoded by the corresponding AND circuit 41 whose output becomes“ 1 ”in response to it. Similarly, it is illustrated in the figure. The instruction code “CALL_addr” is “010
00XXXXX (binary display) ", the instruction code" SE
"T_CF" is 011000XX (binary display)
In addition, the instruction code “RST_CF” is 0111001xx
(Binary display), the instruction code "RT" is 111
"00000 (binary display)", and the decoder circuit decodes each instruction in each decoding unit that responds to each of these.

As described above, the decoder circuit includes the instruction decoding unit corresponding to each instruction included in the instruction system, and any output of the instruction decoding unit corresponding to the input instruction code is "1". The instruction system is decoded according to

In FIG. 3, a carry flag (hereinafter C
The instruction codes “SET_CF” and “RST_CF” which are set and reset instructions (abbreviated as “F”) do not require immediate data, and thus can correspond to one specific code on the instruction map. For example, each of these is "60 (hexadecimal display)" or "65
(Hexadecimal display) "is not a problem. However, in the instruction system illustrated in FIG. 3, since there is a margin of code on the instruction map, redundancy is provided instead of full decoding. The configuration of the corresponding decoding unit of the circuit is simplified.In addition, in FIG.3, the instruction code with redundancy has these "SET_CF" and "RST_C".
Only "F".

[0007]

For example, in order to expand a family of microcomputers, it may be necessary to increase the kinds of instructions in a microcomputer which is newly manufactured. In such a case, the redundant portion of the instruction code having redundancy on the instruction map is assigned to a newly required instruction and defined. However, in this case, it is particularly required that the existing software can be used on the newly manufactured microcomputer. Therefore, in the new microcomputer, it is necessary to devise the decoder circuit so as to maintain the inheritance with the decoder circuit of the conventional microcomputer.

In view of the above, the present invention decodes each instruction code of the new instruction system assigned to the redundant portion of the instruction code having redundancy on the instruction map, and decodes each instruction code of the conventional instruction system. It is an object of the present invention to provide an instruction decoder circuit that is capable of maintaining the inheritance of conventional software.

[0009]

In view of the above, the instruction decoder circuit of the present invention is arranged corresponding to each instruction code included in an instruction system having redundant instructions in at least a part on the instruction map. A first instruction decoding unit responsive to the input of one redundant instruction code in an instruction decoder circuit of a microcomputer for decoding the instruction system, comprising a plurality of instruction decoding units responsive to the input of the respective instruction codes; A specific code detecting section for detecting an input of a specific instruction code included in the one redundant instruction code on an instruction map, and counting the output of the specific code detecting section,
A second instruction decoding unit, which comprises a counter for detecting a predetermined number of outputs from the specific code detection unit and responds to a predetermined number of inputs of the specific instruction code, is provided.

In the decoder circuit of the present invention, the second circuit
It is preferable that the counter of the instruction decoding unit is reset when the input of all the instruction codes other than the specific instruction code.

[0011]

In the instruction decoder circuit of the present invention, the counter of the second instruction decoding section counts the output of the specific code detecting section in response to the input of the specific instruction code, and when the predetermined number of times is counted, the specific instruction is output This command is output as if it existed. On the other hand, when an instruction code including a specific instruction code as a redundant portion is input, the input instruction code is decoded by the first instruction decoding unit, and by the second decoding unit, this instruction code is input. There is also no case where a specific instruction is erroneously output as a specific instruction code being input. Therefore, both the conventional instruction code including the redundant portion and the added specific instruction code can be decoded without any trouble.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further described below with reference to the drawings. FIG. 1 shows an instruction decoder circuit according to an embodiment of the present invention. The instruction system decoded by the instruction decoder circuit of this embodiment is
It is a conventional instruction system shown in FIG. 3 and a new instruction system in which another instruction is simply added to a part of the redundant portion of “SET_CF” without changing the overall configuration.

Since the decoder circuit of the present embodiment has a newly added instruction, the instruction decoder circuit shown in FIG. 4 has a second decoding unit for decoding a specific instruction code "INC_ @ HL". I am adding. With such a configuration, the instruction decoder circuit of the present embodiment adds the conventional instruction code including the instruction code “SET_CF”, which is an instruction including the redundant portion in the instruction map, and the specific portion added to the redundant portion of the instruction code “SET_CF”. You can decipher each instruction code without any trouble.

The specific instruction code "INC_ @ H" illustrated
“L” is “increment the number in the cell of the RAM specified by the address stored in the HL register”.
It is an instruction. The second decoding unit for decoding this instruction "INC_ @ HL" is "011000 ×" in binary display.
An AND circuit 11 that responds to the input of one specific instruction code “0110001 ×” in the redundant portion of the instruction code “SET_CF” that forms “×”, a counter 12 that counts the output of this AND circuit 11, and an AND circuit. The output of 11 and the negation of the input of all instruction codes are two inputs, and the NOR circuit 13 that resets the counter by the output is provided.

In the above configuration, when the code corresponding to the specific instruction "INC_ @ HL" is input, the AND circuit 11 outputs "1" each time in response to the input. When the AND circuit 12 detects that a specific instruction code has been input a predetermined number of times, for example, four times in succession, the counter 12 causes the count end signal (overflow signal).
Generate. The counter 12 has a specific instruction code “I
Whenever an instruction code other than "NC_ @ HL" occurs, it is reset each time. Therefore, if the specific instruction code does not occur a predetermined number of times in succession, the specific instruction is not executed.

In the decoder circuit of the present embodiment, first, "01" is displayed in binary corresponding to the instruction "SET_CF".
When the code "1000XX" is input, the AND circuit 14 forming the first decoding unit outputs the "SET_CF" signal. Further, when the specific instruction code “0110001 ×” forming the redundant portion of the instruction “SET_CF” is input four times in a row, the counter 12 of the second decoding unit generates an overflow signal and the instruction “INC_ @ HL” Is output. This causes the microcomputer to execute this particular instruction "INC_ @ HL".

In the above, in the decoder circuit of this embodiment, when one specific instruction of the redundant portion of the redundant instruction code is generated, the signal for executing the instruction "SET_CF" is continuously output from the AND circuit 14 four times. Is output. Therefore, it is necessary to consider in advance the measures such as removing the influence of the instruction "SET_CF" on the software including this specific instruction or on the hardware.

In place of the above configuration, the instruction "INC_ @ H
A configuration in which "L" is executed only by one code input is also conceivable. However, if such a configuration is adopted, when the instruction code “SET_CF” having a redundant portion is input, the bit I1 is not specified, so depending on the state of the bit I1, in addition to the instruction “SET_CF”, the instruction “IN
C_ @ HL "may also be output. In this embodiment, when the instruction "SET_CF" is input, the instruction "INC_ @ HL" is not output at the same time,
Therefore, the conventionally used instruction "SET_CF"
Inheritance of software including is maintained, and it is not necessary to modify it.

FIG. 2 shows the configuration of a decoder circuit according to the second embodiment of the present invention. In the decoder circuit shown in the figure, the instruction system in which the specific instruction "INC_ @ HL" is additionally allocated to the redundant portion of the instruction "RST_CF" having the redundant portion and the instruction system before that can be decoded.
The instruction “RST_CF” corresponds to the code “011001XX”, and the instruction “INC_ @ HL” corresponds to the code “0.
In the second embodiment, the configuration of the second decoding unit including the AND circuit and the counter is similar to that of the previous embodiment. By continuously inputting the instruction code of, for example, four times, the instruction “INC_ @ HL” is output.

The configuration of each of the above embodiments is merely an example, and the decoder circuit of the microcomputer of the present invention is
Various modifications and variations are possible from the configurations of the above-described embodiments.

[0021]

As described above, the decoder circuit of the microcomputer of the present invention can be operated only when the specific instruction code included in the redundant portion of the instruction code having the redundant portion is continuously input a predetermined number of times. By generating a specific instruction corresponding to a specific instruction code, this instruction can be decoded, and an instruction code including the specific instruction code in the redundant portion can be decoded. Therefore, the present invention has a remarkable effect that a new instruction can be added to the microcomputer while using the conventional software.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a decoder circuit of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a decoder circuit of a microcomputer according to a second embodiment of the present invention.

FIG. 3 is a map diagram of an instruction system having an instruction code having a redundant portion.

FIG. 4 is a circuit diagram of a decoder circuit of a conventional microcomputer.

[Explanation of symbols]

 11, 21 AND circuit 12, 22 Counter 13, 23 NOR circuit 14, 24 AND circuit

Claims (2)

[Claims] 1. A plurality of instruction decoding units, each of which is arranged corresponding to each instruction code included in an instruction system having at least a part of redundant instructions on an instruction map and responds to the input of each instruction code. An instruction decoder circuit of a microcomputer for decoding the instruction system, a first instruction decoding unit responsive to input of one redundant instruction code, and a specification included in the one redundant instruction code on an instruction map Of a specific code detecting section for detecting the input of the instruction code, and a counter for counting the output of the specific code detecting section and detecting a predetermined number of outputs from the specific code detecting section. An instruction decoder circuit comprising: a second instruction decoding unit that responds to a predetermined number of inputs. 2. The instruction decoder circuit according to claim 1, wherein the count value of the counter is reset when an instruction code other than a specific instruction code in the instruction system is input.