JPH03266141A - Microprocessor system - Google Patents

Abstract

PURPOSE:To adds an auxiliary memory and then correct a main memory without replacing the main memory by comparing address data that a comparing circuit sends to the main memory with data stored in registers, and making the auxiliary memory active when the address data indicates a corrected area. CONSTITUTION:When a microprocessor 4 sends out the address data so as to read data out of the main memory 1, the comparing circuit 6 compares the high-order digit bits of the address data with data stored in the registers 5A and 5B. When there is matching data, it is judged that the data indicates the corrected area, the block of the auxiliary memory 2 including the corrected area is specified, and a signal which makes the main memory 1 active is sent to the auxiliary memory 2 to read data out. When there is no matching data, it is judged that the data indicates a part which need not be corrected and an active signal is sent to the main memory 1 to read data out of the main memory 1. Consequently, a ROM stored with a program is corrected partially.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to microprocessor systems.

[Prior Art] Conventionally, when an error is detected in the ROM of the main memory that stores the program of a microprocessor system, or when an attempt is made to make a partial correction, two methods have been taken as a countermeasure for the correction. was. One is to rebuild the entire ROM and replace it completely, and the other is to replace the ROM in the first auxiliary memory that stores the rewritten data for the part that needs to be corrected.
This is a method of adding a second auxiliary memory ROM and a second auxiliary memory ROM in which data that can be used to identify a modification location is stored at the address of the modification location in the main memory ROM.

[Problems to be Solved by the Invention] Among the conventional methods described above, the former requires a lot of time and effort to create a replacement ROM, and it is difficult to remove a faulty memory and replace it with a good ROM. In some cases, it is physically difficult, and in the latter case, instead of just adding parts, multiple ROMs are required as auxiliary memory, so it is not possible to modify the program memory economically. There is a drawback.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor system in which partial modification of a ROM storing a program of a microprocessor system can be realized economically by simply adding one auxiliary memory ROM.

[Means for Solving the Problems 1] The microprocessor system of the present invention includes a microprocessor, and a program connected to the microprocessor by a data bus and a β-bit address bus, which has a portion that requires modification. is stored in a ROM with a capacity of 2L bytes.
The main memory has a total capacity of 2m'' bytes and is divided into 2n blocks of equal capacity, each block stores the modified data of the main memory, and the lower m-n bits of the address bus are stored in each block. R that is input as an address within each block and outputs the read data to the data bus.
an auxiliary memory consisting of an OM, and 2n registers corresponding to each block of the auxiliary memory and storing data indicating the upper 9-m+n bits of the start address of the portion to be modified in the main memory corresponding to the block; , the upper 9-m+n bits of the address bus, the output of each of the registers, and a signal for activating the main memory are input, and the address data input from the address bus is compared with the output of the register. If there is a match with the output of one of the registers, the signal that activates the main memory is converted into a signal that activates the auxiliary memory, and the signal that activates the main memory is converted into a signal that activates the auxiliary memory, and the signal is sent along with the n-bit address signal pointing to the block corresponding to the matched register. and a comparison circuit that sends a signal that activates the main memory to the main memory as it is if there is no register with a matching output when compared.

[Operation] When the microprocessor outputs address data to read data from the main memory, a comparison circuit compares the upper bits of the address data with the data stored in each register and determines which ones match. If there is, the block of auxiliary memory that includes the modified area is designated as a modified area and a signal is sent to the auxiliary memory to activate the main memory, so if data is read from the auxiliary memory and there is no match. sends an active signal to the main memory because it is a part that does not require modification, so data is read from the main memory.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the microprocessor system of the present invention, and FIG. 2 is a detailed diagram of the comparator circuit 6. In FIG.

In the microprocessor system of this embodiment, n=17,
In the example where m = 15 and n = 1, microprocessor 4 and ! = 17-bit address bus 8 and the program of the microprocessor 4 are stored, 2' = 2
” = 128 Kbyte capacity and address 0AOOO(H
1 to 0A02F (H) Main memory l (ROM) with one location that requires modification, and 2" = 2m11' =
32 bytes in capacity, 2m' = 2' = divided into 2 16 byte blocks 2A, 2B each containing the modified program of the main memory 1, lower m-n = of the address bus 8; 15-1=11-m+
n = 17 - 15 + 1 = registers SA, 5B each storing 3 bits of address data, and upper It-m + n = 3 bits of address data C of address bus 8 are sent to the output i of each register SA, 5B. compared to
Blocks 2A and 2B if either one is equal
The address n=1 bit signal and the active signal g of the auxiliary memory 2 are sent to the auxiliary memory 2, and if they are not equal, only the active signal f of the main memory 1 is sent to the main memory 1.
and a comparator circuit 6 which sends data to.

Next, the operation of this embodiment will be explained.

Main memory 1 address 0AOOO(H) ~ 0A02F
When modifying the data in (H), main memory 1 is divided into 8 blocks of 16 bytes each, and the block containing the part to be modified is 08000 (H) to 0BFFF (H
), therefore, block 2A of auxiliary memory 2 contains 080
Write the correction data from 00 (H) to 0BFFF (H) in advance, and write the start address of the block that needs correction to register 5A, 08000 (formerly the upper 3 bits 010 (
Stores 2m. Required data is similarly stored in block 2B and register 5B for other modified parts.

Address data a is osooo (old ~ 0BFFF (
H), the comparator circuit 6 converts the active signal e into the active signal g of the auxiliary memory 2, making the auxiliary memory 2 active, and the main memory l does not become active. The dividing circuit 7 (FIG. 2) connects the block 2A of the auxiliary memory 2 corresponding to each register 5A, 5B.
, 2B is output to address h, and when output 1 of register 5A and address data C match, that is, address data a is 08000.
fHl ~ 0BFFF (Between Hl, 0 is output to address h and block 2A is selected. When address data C and the output k of register 5B match, address h becomes 1 and block 2B is selected. Ru.

Furthermore, when address data C does not match with either output i of registers 5A or 5B, active signal e
is converted into an active signal f and sent to the main memory 1,
Data in main memory 1 will be read. Therefore, by replacing the data area with the auxiliary memory 2, it is possible to modify up to two blocks of data without replacing the main memory 1.

In this embodiment, the memory replacement unit is 2m-11=2''
= Data area of main memory 1 and auxiliary memory 2 as 16 bytes 2' - "" = 2 '' = 8 blocks and 2'
=2'=2 blocks, but the size and number of blocks can be changed by using m and n as variables for β. Namely.

Depending on the number and size of parts of main memory l that need modification,
The number and size of the corresponding blocks of the auxiliary memory 2 are determined, and the required capacity of the auxiliary memory 2 is determined.

Further, a microprocessor system such as this embodiment can be realized at extremely low cost by using ICs such as gate arrays and PALs.

〔Effect of the invention〕

As explained above, in the present invention, conditioned program data is stored in the auxiliary memory in blocks that are set commonly in the main memory and the auxiliary memory, and a comparison circuit stores address data to be sent to the main memory in a register. The auxiliary memory is activated when it is a modified area compared to the data being added, so by adding auxiliary memory, main memory can be modified without replacing the main memory. The capacity and number of parts can be kept to a minimum depending on the size and number of parts to be corrected.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the microprocessor system of the present invention, and FIG. 2 is a detailed diagram of the comparator circuit 6. In FIG. DESCRIPTION OF SYMBOLS 1... Main memory, 2... Auxiliary memory, 4... Microprocessor, 5A, 5B-... Register, 6... Comparison circuit, 7... Cutting circuit. 8...Address bus.

Claims (1)

[Scope of Claims] 1. A microprocessor, which is connected to the microprocessor by a data bus and an l-bit address bus, stores a program that partially requires modification, and has a capacity of 2^l bytes; R.O.
The main memory consists of M and the total capacity is 2^m bytes, 2^
It is divided into n blocks of equal capacity, and the modified data of the main memory is stored in each block, and the lower m-n bits of the address bus are inputted as addresses within each block, and the read data is An auxiliary memory consisting of a ROM, which is output to the data bus, and data corresponding to each block of the auxiliary memory and indicating the upper l-m+n bits of the start address of the part to be modified in the main memory corresponding to the block. 2^n registers to be stored,
The upper l-m+n bits of the address bus, the output of each of the registers, and a signal for activating the main memory are input, and the address data input from the address bus is compared with the output of the register, and one of the registers is determined. If the output of the register matches, the signal that activates the main memory is converted into a signal that activates the auxiliary memory, and the signal that activates the auxiliary memory is converted into a signal that activates the auxiliary memory, and the signal is output to the auxiliary memory along with an n-bit address signal pointing to the block corresponding to the matched register. and a comparison circuit that sends a signal that activates the main memory to the main memory as it is if there is no register with a matching output when compared.