JPH08137762A - Parity check system - Google Patents

Abstract

PURPOSE: To use the storage capacity of ROM without waste by executing parity check with a parity outputted from a selector and data outputted from a program memory in a parity arithmetic part. CONSTITUTION: The part of a remaining address, which is a part except a part inputted to a parity memory 2, is inputted to a selector 3. A part of a bit string outputted from the parity memory 2 is outputted to the selector 3 as the parity corresponding to data stored in a program memory 1. Parity check is executed in the parity arithmetic part 4 with the parity outputted from the selector 3 and data outputted from the program memory 1. Thus, the storage capacity of ROM can be used without waste when ROM is used as the parity memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check system for checking a program or the like stored in a read only memory.

[0002]

2. Description of the Related Art Generally, read only memory (ROM)
When the program is stored in, some bit values may change due to aging, etc., so that the contents are regularly checked. As a method for this, there are a sum check method and a parity check method. In the sum check method, the sum of the data stored in the ROM for each byte or word from address 0 to the last address (m-1) is added to the final address m.
Stored in. And at any time, programmatically 0
The addition from the address to the address (m-1) is executed, and the result is compared with the total value stored in the address m in advance.

On the other hand, in the parity check method, the ROM
Parity is calculated for each byte or word of the data stored in, and the parity is stored in the ROM for parity. Then, when the data is read from the ROM, a parity operation is performed on the read data, and the operation result is compared with the previously stored parity to perform a check.

[0004]

However, the above-mentioned conventional techniques have the following problems. That is, R
When the OM is monitored by the sum check, this is performed by the program. Therefore, while the sum check is being performed, another program cannot be executed, which may affect the execution of the original program. In addition, it is virtually impossible to always monitor, and the program is executed at intervals of a certain time interval between executions of the original program. On the other hand, when the monitoring of the ROM is performed by the parity check, the memory such as the ROM generally has a structure of n × 8 bits or n × 16 bits, and has a small structure of n × 1 bits. For this reason, an n × 8 bit ROM is usually used as the parity memory instead of the n × 1 bit ROM, in which case only one of each 8 bits is used to store the parity. Only bits, so most of the storage capacity is wasted. In addition, it is disadvantageous in terms of cost and mounting space.

[0005]

The parity check method of the present invention is characterized by the following points in order to solve the above-mentioned problems. (1) A program memory and a parity memory for inputting a part of the address input to the program memory are provided. A selector that inputs the remaining address part other than the part input to the parity memory as a selector input and outputs a part of the bit string output from the parity memory as the parity corresponding to the data stored in the program memory. Prepare A parity operation unit is provided for performing a parity check with the parity output from the selector and the data output from the program memory.

(2) In (1), the parity memory outputs an 8-bit bit string by inputting a part of the address to the program memory, and the selector:
Three bits of the address to the program memory are input as selector inputs, and one bit of the 8-bit bit string output from the parity memory is output as a parity bit to the parity operation unit.

[0007]

[Action]

(1) When the addresses Ax to A0 from the processor are input to the program memory, the 2 ^y- bit data D2 ^y -1 to D0 corresponding to the addresses are read out. On the other hand, address A
When the upper part Ax to Ay of x to A0 is input to the parity memory, the corresponding 2 ^y- bit data Dp2 ^y -1 to
Dp0 is read. Then, the lower parts Ay-1 to A0 of the addresses Ax to A0 are supplied to the select input of the selector. In the selector, the data Dp2 ^y
Outputs any bit from -1 to Dp0. In the parity operation unit, this bit and the data D2 ^y -1 to D0 are input,
The parity obtained by calculation from the data D2 ^y -1 to D0 is collated with the parity of this bit. This confirms the validity of the data D2 ^y -1 to D0. As a result, n × 2
The capacity of the ROM having the ^y- bit configuration can be used without waste.

(2) In (1), particularly y = 3,
As a result of using the ROM having the n × 8 bit structure as the parity memory, the most popular ROM can be used, and the selector can be set to 8: 1 to suppress the complication of the structure.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the parity check method of the present invention. The illustrated apparatus includes a program memory 1, a parity memory 2, a selector 3, and a parity calculation unit 4. The program memory 1 is composed of a ROM and has a structure of, for example, n × 8 bits. That is, by inputting an x-bit address, data is output every 8 bits. The parity memory 2 is composed of a ROM and has a structure of n × 8 bits like the program memory 1,
Its capacity is 1/8 of the program memory 1. The parity memory 2 uses the upper n-3 bits of the x-bit address input to the program memory 1 as an address input. Parities are stored in the parity memory 2 as follows.

As shown in FIG. 2, the parity for the 8-bit data at the address 0 in the program memory 1 is stored in the "bit 0" at the address 0 in the parity memory 2. The parity for the 8-bit data at address 1 in the program memory 1 is stored in the “bit 1” at address 0 in the parity memory 2. The parity for the 8-bit data at the address 2 in the program memory 1 is stored in the “bit 2” at the address 0 in the parity memory 2. In this way, the parity corresponding to the data (program) stored in the program memory 1 is stored so as to fill each bit in order from “bit 0” of the lower address of the parity memory 2 without a gap.

The selector 3 has an 8-to-1 configuration and selects 1 bit in accordance with the select input of the 8-bit bit string. That is, as shown in FIG. 3, the select input of the selector 3 is connected to the lower 3 bits A2A1A0 of the x-bit address input to the program memory 1. Then, 8 output from the parity memory 2
One of the bits is output as the parity corresponding to the data read from the program memory 1. The parity operation unit 4 performs a parity operation on the data output from the program memory 1 and performs a parity check by comparing the operation result with the parity output from the selector 3.

Next, the operation of the above-mentioned device will be described. Addresses Ax to A from the processor 5 via the address bus
0 is sent. When the addresses Ax to A0 are input to the program memory 1, 8-bit data D7 to D0 corresponding to the addresses are read. For example, the address "00
1011 ”is input to the program memory 1, data“ 10001101 ”is output, and is input to the parity calculation unit 4. If the parity in this case is even parity, the result of the parity calculation is“ 1 ”. on the other hand,
When the higher order parts Ax to A3 of the addresses Ax to A0 are input to the parity memory 2, 8-bit data Dp7 to Dp0 corresponding thereto are read out. For example, it is assumed that the upper address part "001" is input to the parity memory 2 and the data (parity column) "01011000" is output and input to the selector 3.

The lower part A of the addresses Ax to A0
2 to A0 are supplied to the select input of the selector 3. For example, the lower address part "011" is supplied to the select input. As a result, “010
In 11000 ”, the rightmost one is selected as“ bit 0 ”, and“ 1 ”at the position of“ bit 3 ”is selected, and this bit value is collated with the value calculated by the parity calculator 4. Since the bit value is equal to the value “1” calculated by the parity calculator 4, the validity of the data “10001101” read from the address “001011” of the program memory 1 is confirmed as a result of the parity check.

In this way, the RO of n × 8 bit structure
The parity check can be performed using the capacity of M without waste. Therefore, it is possible to constantly monitor the program memory 1 in parallel with the execution of the program by the parity operation unit 4 separate from the processor that executes the program while reducing the cost and downsizing the device. still,
The present invention is not limited to the embodiments described above, and it goes without saying that various modifications are possible. For example,
The program memory 1 and the parity memory 2 are not limited to the configuration of n × 8 bits, but may have a configuration of n × 16 bits or the like, and the selector 3 may have a 16: 1 configuration. Further, the select input may be not the lower 3 bits of the address of the program memory 1 but the upper 3 bits, and the remaining address portion may be the address input of the parity memory 2. Further, the parity is not limited to 1 bit and may be a parity of 2 bits or more.

[0015]

As described above, according to the parity check method of the present invention, the selector for providing a part of the address of the program memory as the select input is provided. Therefore, the n × 1 bit ROM is used as the parity memory. Even if a readily available ROM having an arbitrary configuration is used instead of, the storage capacity of the ROM can be utilized without waste, which is advantageous in terms of cost and mounting space.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a parity check method of the present invention.

FIG. 2 is an explanatory diagram of a parity storage order in a parity memory 2.

FIG. 3 is an explanatory diagram of an operation at the time of parity check of the device according to the present invention.

[Explanation of symbols]

 1 Program Memory 2 Parity Memory 3 Selector 4 Parity Arithmetic Unit 5 Processor

Claims (2)

[Claims] 1. A program memory, a parity memory for inputting a part of an address input to the program memory, and a remaining address part other than a part input to the parity memory are input as selector inputs, A parity check is performed by a selector that outputs a part of the bit string output from the parity memory as the parity corresponding to the data stored in the program memory, and the parity output from the selector and the data output from the program memory. A parity check system characterized by comprising a parity operation unit for performing. 2. The parity memory outputs a bit string of 8 bits by inputting a part of the address to the program memory, and the selector selects 3 bits of the address to the program memory. 2. The parity check method according to claim 1, wherein 1 bit of an 8-bit bit string input as an input and output by the parity memory is output as the parity bit to the parity operation unit.