JPH07200416A - Memory system - Google Patents

Abstract

PURPOSE:To enable size reduction, simplification, and price reduction when the memory system is mounted on information equipment by storing a data word and data for detection corresponding to it in the same memory. CONSTITUTION:The ROM-A-2 is stored with the data word and the parity word corresponding to it. A read order circuit A-0 outputs information showing the area of the data word or parity word to be read out to an information address generating circuit A-1 under the control of a CPU 1 and also outputs information indicating one unit of parity words corresponding to the read data word among parity words corresponding to one address to a detection part 5. The detection part 5 performs error detection on the basis of the data for error detection read out of a specific storage location of the ROM-A-2 so as to detect a data error fo the data word and the word data read out corresponding to the data for detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory, particularly a ROM.
The present invention relates to a memory system that detects a data error in data stored in a memory.

[0002]

2. Description of the Related Art Conventionally, in information equipment such as a computer, information (program, data) necessary for system initialization or startup is stored in a ROM and turned on. In such a case, it is general to read the information in the ROM and perform the processing necessary for starting the system. In addition, in the ROM, processing when abnormalities occur in the system and it becomes impossible to continue the system operation (abnormal end processing, dump of analysis information, etc.)
Important programs and information such as programs related to the above, or programs related to processing for grasping the status of system components before the system is started (before you can log in to the system) are stored. There are many.

From the viewpoint of data error detection for data stored in ROM, the data in ROM can be distinguished as follows. In the field where reliability is not necessarily ensured, when data is stored in the ROM, the data is stored in the ROM without adding a parity bit, and the ROM is configured to be accessed. There are many information devices. On the other hand, it is indispensable to add a parity bit to store data in a ROM mounted on an information device in a field requiring reliability. In addition to ROM as memory, D
Even in the case of a RAM or the like, data to which error detection data such as ECC is added is stored, and a parity bit is also added to the address and data sent to the standard bus for error detection. Is common.

Therefore, in the past, most commercially available ROMs have 2 ⁿ bits per word (n = 1, 2, 3).
..), the configuration shown in FIG. 5 or 6 is adopted to add a parity bit.

First, the configuration example shown in FIG. 5 will be described. In this configuration example, data is stored in the ROM-A and R
The parity corresponding to OM-B is stored. RO above
The data of MA and the parity of ROM-B are stored in the area of the same address, and the same address is stored in R
By giving the data word and the corresponding parity bit to the OM-A and the ROM-B at the same time, the data word and the corresponding parity bit reach the parity check circuit 2. The parity check circuit 2 creates a parity bit from the read data word, compares it with the read parity bit, and outputs information regarding the presence or absence of a data error. When the required data width cannot be secured with the data of one address, the data and the parity bit are repeatedly read until the required data width is reached. The memory system having the configuration shown in FIG. 5 is suitable when the reliability of information is more important than the access speed for obtaining information.

However, according to the memory system having the above structure, a plurality of ROMs (two ROMs in the above example) are used.
It must be used, and the number of parts to be mounted increases, which may reduce reliability. In addition, since the parity bit is usually 1 bit, in the ROM in which the parity bit is stored, an unused area which is shown as an unused area in FIG. 5 and is not used (from the data length of one address to the number of bits of the parity bit). Area of data length)
If it is installed in an information device, it may hinder downsizing, simplification, and cost reduction.

In contrast to the above, a memory system can be constructed as shown in FIG. That is, a plurality of ROMs (see FIG.
In the above example, eight pieces of A0 to A7) are connected in parallel, and the information of the required data width can be read by one memory access. Also, for the parity word,
Store in ROM-B. In the storage area of the ROM-B having the same address as the ROM-A0 to A7, the ROM-A0 to A7 are stored.
The parity bit corresponding to the data of the address is continuously stored. The required address is ROM-A0
When the data is read out by giving it to A7 and ROM-B, 8-bit data is stored in one address of one ROM in the example of FIG. 6, so a 64-bit data word and the corresponding 8-bit data word are stored. Parity is the parity check circuit 3
To The parity check circuit 3 creates a parity bit from the read data word, compares it with the read parity bit, and outputs information regarding the presence or absence of a data error.

[0008]

According to the memory system having the above structure, although it is possible to read the data word and the parity having the required data width at one time, the number of ROMs increases as the data width increases. There are increasing problems. In the example of FIG. 6, nine ROMs are required due to the data width of 64 bits. Therefore, even if this conventional system is mounted on an information device, it is not possible to eliminate the risk of hindering downsizing, simplification, and cost reduction.

The present invention has been made to solve the problems of the conventional memory system as described above, and its purpose is to realize downsizing, simplification, and cost reduction when mounted in an information device. It is to provide a memory system capable. Another object of the present invention is to provide a memory system that enables high-speed reading of data as needed and guarantees a required high-speed operation when mounted on an information device.

[0010]

Therefore, the first aspect of the present invention is described.
In the invention described in (3), there is provided an information area in which a data word is stored and an error detection data area in which error detection data corresponding to the data word is stored. Memory for storing the error detection data to be stored, storage position information holding means having information on the storage position of the error detection data corresponding to the data word in the memory, and data error of the data word is detected. In order to do so, the error detection data is read from a predetermined storage position of the memory, the corresponding data word is read out based on the information of the storage position information holding means, and the error detection is performed based on these data. Configured the memory system.

According to the second aspect of the present invention,
There is an information area for storing a data word and an error detecting data area for storing error detecting data corresponding to the data word, and the data word and the error detecting data corresponding thereto are provided in each of the areas. A memory in which is stored, storage position information holding means having information on a storage position of the data word and error detection data corresponding to the data word, and a predetermined memory of the memory for detecting a data error of the data word. Reading means for reading the error detection data from the storage position and for reading the corresponding data word based on the information of the storage position information holding means;
Holding means for holding the error detecting data read by the reading means, and when the reading means reads a data word, the corresponding error detecting data is held based on the information of the storage position information holding means. The memory system is configured by including the error detecting means for detecting the error in the data word.

Further, in the invention according to claim 3 of the present invention,
There is an information area in which a data word is stored, and an error detection data area in which error detection data corresponding to the data word is stored. In each of the areas, a data word and error detection data corresponding thereto are provided. A memory in which is stored, storage position information holding means having information on a storage position of the data word and error detection data corresponding to the data word, and a predetermined memory of the memory for detecting a data error of the data word. Reading means for reading the error detection data corresponding to a plurality of data words from the storage position first, and then sequentially reading the corresponding data words word by word based on the information of the storage position information holding means, and this reading means. Holding means for holding error detection data corresponding to a plurality of data words read by the reading means, When one word of the data word is read out, error detection data for the data word of the one word is obtained from the holding means based on the information of the storage position information holding means, error detection data corresponding to the data word is detected. And a memory system.

Further, in the memory system according to the fourth aspect of the present invention, in addition to the above configuration, the memory includes:
The number-of-cycles information necessary for accessing the memory is set, the memory is accessed by the number of cycles indicated by the default value, and after the number-of-cycles information is read from the memory, It is characterized by comprising an access execution means for executing the access to the memory according to the number of cycles relating to the read information.

[0014]

According to the first aspect of the present invention, the data word and the error detection data corresponding to the data word are stored in the same memory. In addition to realizing simplification and cost reduction, it is possible to appropriately detect a data error and provide a highly reliable device.

According to the invention of claim 2 of the present invention,
The read error detection data is held, and the data error detection is performed for the read data word using this, and the data word and the corresponding error detection data are in the same memory. Even if it is impossible to read them at the same time when they are stored in, the proper data error detection is guaranteed.

According to the invention of claim 3 of the present invention,
In order to detect a data error in a data word, error detection data corresponding to a plurality of data words is first read from a predetermined storage position of the memory, and this is held, and then the corresponding data words are sequentially read word by word. Since the data is read, a data error check can be performed using the held error detection data every time this one word is read, and a higher speed can be secured as compared with the case where the error detection data is sequentially read as much as the corresponding data. You can

According to the invention of claim 4 of the present invention,
After the cycle number information is read from the memory, the memory is accessed according to the cycle number related to the read information, so that the information device is equipped with the memory having the access cycle number as necessary. Then, the required performance can be provided to the information device.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a block diagram of a memory system according to an embodiment of the present invention. A
Reference numeral -2 indicates a ROM, in which a data word and a parity word corresponding to the data word are stored. In the storage area of the ROM-A-2, an information area in which a data word is stored and a parity area in which a parity word is stored are provided separately. The correspondence between the data word in the information area and the parity word in the parity area will be described. In this example, one data word is stored for one address, and as shown in the figure, corresponding to m data words from data word n to data word (n + m), a predetermined one address in the parity area is stored. The corresponding parity word is stored. When the parity word stored in this one address is divided into m pieces, each unit is a data word n.
To data word (n + m).

Under the control of the CPU 1, the reading order circuit A-0 outputs information indicating the area of the data word or parity word to be read to the address generating circuit A-1 and corresponds to one address for the detecting section 5. Information indicating one unit (a predetermined block in the parity word) of the parity word corresponding to the read data word among the parity words is output. Address generation circuit A-
1 is generated by calculating the address of the ROM-A-2 corresponding to the given information (this calculation includes that by table search).

The detection unit 5 detects the data error of the data word based on the error detection data read from the predetermined storage position of the ROM-A-2 and the data word read correspondingly. Perform error detection. Specifically, the detection unit 5 includes a parity word holding circuit A-3 that holds the parity word read from the ROM-A-2, a parity word held in the parity word holding circuit A-3, and the parity word holding circuit. And a parity check circuit A-4 for detecting an error based on the data word read in correspondence with the above. The read order control circuit A-0, the address generation circuit A-1, the CPU 1, and the detection unit 5 read the error detection data from a predetermined storage position of a memory (ROM) in order to detect a data error in the data word, and read the read order. A corresponding data word is read based on the information of the control circuit A-0, and an error detection unit is constructed based on these data.

Further, at a predetermined address of the ROM-A-2, information on the number of cycles required to access the ROM-A-2 (information indicating how many system clock cycles are required for memory access) is stored. There is. The read order control circuit A-0 initially controls the address generation circuit A-1 so as to perform memory access with the number of cycles corresponding to the default value held by itself or given by the CPU 1. Here, the default values are ROMs with different access speeds that can be mounted on certain types of information equipment.
The number of cycles corresponding to the ROM having the slowest access speed. When the cycle number information necessary for accessing the ROM-A-2 is read from the predetermined address of the ROM-A-2, the CPU 1 gives this information to the read order control circuit A-0 together with the cycle number change instruction command. .
The read order control circuit A-0 controls the address generation circuit A-1 so that the memory access is performed by the number of cycles corresponding to the information from the next read cycle of the parity word.

FIG. 2 shows a more detailed configuration example of the above memory system. For example, 16-bit data is stored in one address of the ROM-B-3. 1
A 4-bit parity word is associated with the data word as one unit. Therefore, 4 of the data word
Each bit corresponds to one parity bit.

The CPU 1, the read sequence circuit B-0, the address generation circuit B-2, and the detection unit 5 are similar to the CPU 1, the read sequence circuit A-0, the address generation circuit A-1, and the detection unit 5 of FIG.
Since they correspond to each other and have the same configuration,
Portions related to different configurations will be described. The detection unit 5 has 16
A selector B- for selecting the 4 bits of the register B-4 having a bit width, the check parity check circuit B-6 for calculating and comparing the parity, and the register B-4 and sending the selected bit to the parity check circuit B-6. And 5 are provided.

The read order control circuit B-0 is a register B-
4 enable signal B-7, selector B-5 register B-4 position selection instruction signal B-8 for instructing selection of any 4 bits, parity check circuit B-
The parity check instruction signal B-9 for 6 is output as shown in FIG.

Initially, the read order control circuit B-0 sets the address generation circuit B-2 so that the memory access is performed in the cycle number 6 corresponding to the default value held by itself or given by the CPU 1. Control. Therefore, as shown in FIG. 4, initially, data is read from the ROM-B-3 in 6 cycles of the system clock. When the cycle number information (information indicating three cycles) necessary for accessing the ROM-B-3 is read from the predetermined address of the ROM-B-3, the CP
As shown in FIG. 4, U1 supplies this information to the read order control circuit B-0 together with the cycle number change instruction command. The read order control circuit B-0 performs RO with the number of cycles 3 corresponding to the information from the next cycle of reading the parity word.
The address generation circuit B-2 is controlled so as to access M-B-3. Subsequent access to the ROM-B-3 is performed in three system clock cycles.

FIG. 3 shows a read sequence after the access is performed in three cycles under the above control. Here, a case is shown in which error detection is performed for four words from data word n to data word (n + 3) in FIG. The read sequence circuit B-0 is C
Under the control of PU1, information indicating the area of the parity word to be read is given to the address generation circuit B-2 to instruct the corresponding address calculation. Address generation circuit B-2
Is generated by calculating the address of the ROM-B-3 corresponding to the given information (this calculation includes that by table search).

A parity word is read from the ROM-B-3 corresponding to the address output from the address generating circuit B-2. At this time, the read sequential circuit B-0 activates the enable signal B-7 for the register B-4. As a result, the parity word read above is set in the register B-4.

Next, the reading order circuit B-0 gives the information showing the area of the data word n which is the first data word corresponding to the above parity word to the address generating circuit B-2 and calculates the corresponding address. Give instructions. The address generation circuit B-2 is a ROM-B-3 corresponding to the given information.
It is generated by calculating the address of.

The data word n is read from the ROM-B-3 corresponding to the address output from the address generating circuit B-2. At this time, the read sequence circuit B-0 has 4 bits (+0 in the figure) associated with the first unit of the register B-4.
Position selection instructing signal B-8 for instructing selection of the 4 bits of the position) to the selector B-5 and the parity check instructing signal B-9
Is output as active.

The parity check circuit B-6 receives the data word n, calculates the parity word, compares the parity word obtained by this calculation with the parity word arrived via the selector B-5, and detects a data error. A signal indicating the presence or absence of is output.

Next, the reading order circuit B-0 gives the information showing the area of the data word (n + 1) which is the second data word corresponding to the above parity word to the address generating circuit B-2, and the corresponding address. Instruct the calculation. The address generation circuit B-2 is a ROM corresponding to the given information.
-It is generated by calculating the address of B-3.

The data word (n) from the ROM-B-3 corresponds to the address output from the address generating circuit B-2.
+1) is read. At this time, the read sequential circuit B-0
Supplies a position selection instruction signal B-8 for instructing selection of 4 bits (4 bits at position +1 in the figure) related to the second unit of the register B-4 to the selector B-5 and a parity check circuit. The parity check instruction signal B-9 is output as active for B-6.

The parity check circuit B-6 receives the data word (n + 1) and calculates the parity word. The parity word obtained by this calculation and the selector B-
5 is compared with the parity word arriving via 5, and a signal indicating the presence or absence of a data error is output. Similarly, the parity check is repeated for the data words (n + 2) and (n + 3). That is, the parity check for 4 data words is performed by repeating 3 cycles of the system clock 5 times. When the signal indicating the presence or absence of a data error output from the parity check circuit B-6 indicates that there is a data error, the data is treated as invalid.

In the above embodiments, one data word corresponds to one unit (4 bits in the embodiment of FIG. 2) parity word. However, in other embodiments, a plurality of data words are used. It corresponds to one unit (1 bit or more) of parity bits. For example, 4 data words correspond to 1-bit parity words. In such a case, the parity word holding circuit A-3 in the detection unit 5 of FIG. 1 is used not only to hold the parity word read from the ROM but also to hold the data word read from the ROM (of course, Will be bigger). When the number of held data words reaches a predetermined number, the parity check circuit A
-4 creates a parity word, compares it with the parity word read from the ROM held in the parity word holding circuit A-3, and outputs the result.

When a plurality of data words correspond to a parity word composed of 2 bits or more per unit (for example, 4 data words correspond to a parity word of 4 bits per unit), the detection of FIG. The parity word holding circuit A-3 in the unit 5 is used not only to hold the parity word read from the ROM, but also to hold the data word read from the ROM and the created parity word (of course, increase the capacity). . Then, when the number of held data words reaches a predetermined number, the parity check circuit A-4 creates a parity word for each data word and causes the parity word holding circuit A-3 to hold it. When the parity words corresponding to all the data words have been created, the parity word read from the ROM held in the parity word holding circuit A-3 and the created parity word are read and compared, and the result is output. .

In this way, a plurality of data words are
In the case where the unit corresponds to a parity word composed of 2 bits or more, in another embodiment, error detection is performed as follows. The parity check circuit A-4 creates a parity word each time a data word is read from the ROM and compares the parity word with the corresponding portion in the corresponding unit of the parity word held in the parity word holding circuit A-3.
After outputting the result, this operation is repeated.

Further, in the embodiments of FIGS. 1 and 2 described above, the memory is explained as a ROM, but the present invention is a RAM, an E.
It can also be applied to a memory capable of writing data, such as an EPROM. Further, although the parity word is used as the error detection data, various error detection data such as checksum data and CRC data are used in other embodiments. In the embodiments of FIGS. 1 and 2 described above, in the memory, the information area in which the data word is stored and the error detection data area in which the error detection data corresponding to the data word is stored are separated. However, it is not necessary for both areas to be separated, and even if both areas are arranged discretely,
It is sufficient to have both areas even when the area is secured so that the corresponding parity word and data word are continuous.

Further, although the present embodiment is a memory system which performs detection of a data error, a data error correction circuit is added to the present embodiment, and when a data error is detected, correction of the data error is performed. It can also be a memory system.

[0039]

As described above, according to the present invention as set forth in claim 1, since the data word and the error detection data corresponding to the data word are stored in the same memory, the memory is used as an information device. When it is installed in the device, it is possible to provide a highly-reliable device that realizes downsizing, simplification, and cost reduction and that appropriately detects a data error.

According to the present invention as defined in claim 2,
Since the read error detection data is held and the data error is detected for the read data word using this, the data word and the error detection data corresponding thereto are stored in the same memory. In this case, it is guaranteed that the data will be read continuously and appropriate data error detection will be performed.

According to the present invention as defined in claim 3,
In order to detect a data error in a data word, error detection data corresponding to a plurality of data words is first read from a predetermined storage position of the memory, and this is held, and then the corresponding data words are sequentially read word by word. Since the data is read, the data error check can be performed using the held error detection data each time this one word is read. Therefore, the number of times of reading can be reduced as compared with the case of sequentially reading the error detection data by the number of times corresponding to the number of data words, and the speedup of data error detection can be ensured.

Further, according to the present invention as set forth in claim 4, after the cycle number information is read from the memory, the memory access is executed according to the cycle number related to the read information. It is possible to equip the information device with a memory having the number of cycles as necessary and to provide the information device with necessary performance, in particular, memory access speed and performance related to data error detection processing in the memory. There is an effect that a grade information device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory system according to an embodiment of the present invention.

FIG. 2 is a more detailed configuration diagram of a memory system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an operation sequence of the memory system according to the embodiment of the invention.

FIG. 4 is a timing diagram showing an operation of the memory system according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional memory system.

FIG. 6 is a configuration diagram of a conventional memory system.

[Explanation of symbols]

1 CPU 5 Detector A-0, B-0 Read order control circuit A-1, B
-2 address generation circuit A-2, B-3 ROM A-3 parity word holding circuit A-4, B-6 parity check circuit B-4 register B-5 selector

Claims (4)

[Claims] 1. An information area in which a data word is stored and an error detection data area in which error detection data corresponding to the data word is stored, and a data word and the corresponding data word in each area. A memory in which error detection data is stored, a storage position information holding unit having information on a storage position in the memory of the error detection data corresponding to the data word, and a data error of the data word is detected. Therefore, a control unit for reading error detection data from a predetermined storage position of the memory, reading a corresponding data word based on the information of the storage position information holding means, and performing error detection based on these data is provided. Characteristic memory system. 2. An information area in which a data word is stored and an error detection data area in which error detection data corresponding to the data word is stored, and the data word and the corresponding data word in each area. A memory in which error detection data is stored, a storage position information holding unit having information on a storage position in the memory of the error detection data corresponding to the data word, and a data error of the data word is detected. Therefore, the error detecting data is read from a predetermined storage position of the memory, and the reading means for reading the corresponding data word based on the information of the storage position information holding means, and the error detecting data read by the reading means is held. Holding means for storing the data word when the data word is read by the reading means. Memory system characterized by comprising an error detection means for performing error detection for the data word to give the can corresponding error detection data from said holding means. 3. An information area in which a data word is stored and an error detection data area in which error detection data corresponding to the data word is stored, the data word in each of the areas and the corresponding data word. A memory in which error detection data is stored, a storage position information holding unit having information on a storage position in the memory of the error detection data corresponding to the data word, and a data error of the data word is detected. Therefore, reading means for reading error detecting data corresponding to a plurality of data words from a predetermined storage position of the memory first, and then sequentially reading corresponding data words one word at a time based on the information of the storage position information holding means. Holding means for holding error detection data corresponding to the plurality of data words read by the reading means, When one word of the data word is read by the recording / reading means, error detection data corresponding to the data word is obtained from the holding means based on the information of the storage position information holding means, and error detection is performed for the data word of the one word. A memory system comprising: 4. The memory is set with cycle number information required to access the memory, and the memory access is executed according to the cycle number indicated by a default value, and the cycle number information from the memory is executed. 4. The method according to claim 1, further comprising an access execution unit that executes the access to the memory according to the number of cycles of the read information after the reading is performed.
The memory system according to claim 1.