JPH0846056A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the chip occupation area of an input protective circuit and facilitate the high speed operation of an input circuit by a method wherein a resistance element which has stable nonlinear characteristics is formed on the polycrystalline silicon film or the metal film of an integrated circuit and a nonlinear resistance element composed of wiring layers and a thin insulating film formed between them is employed in the input protective circuit. CONSTITUTION:A second conductor 17 composed of a metal nitride film is formed on a first conductor 12 formed on a semiconductor substrate with an insulating layer 16 between them to constitute an MIM structure and a resistance element having nonlinear characteristics can be realized with the MIM structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a resistance element having a non-linear characteristic and a forming method thereof.

[0002]

2. Description of the Related Art As a resistance element having a MIM (metal insulator metal) structure, a two-terminal non-linear element having high resistance at low voltage and low resistance at high voltage is known.
For example, SM SZE "Physics of Semiconductor Device"
"p.614-p.624.

On the other hand, when the non-linear element is formed on the semiconductor substrate, the electrode must be formed on the insulating film having a thickness of 10 nm or less, but in general, it can be formed with the same structure as the MOS element.

However, as described above, the nonlinear element is
When the MOS structure is realized on the I substrate (for example, a silicon substrate), the element area becomes relatively large and the LSI chip area increases. Moreover, since one electrode of the non-linear element is the substrate, the injected carriers may diffuse in the substrate, which may cause a malfunction of the circuit formed on the substrate.

Although the nonlinear characteristic may be realized by a combination of a diode and a resistance element, there is a problem similar to the above. On the other hand, in an integrated circuit having a MOS type input circuit such as a MOS type integrated circuit, as an input protection circuit for protecting the MOS type input element from electrostatic breakdown, as shown in FIG. A diode D is inserted and connected between the input signal line between the input circuit 81 and the input circuit 81 and the power supply line or the ground line. This diode D does not turn on within the allowable range of the input voltage, but turns on by an excessive input voltage or negative voltage input, and protects the gate of the input element from electrostatic breakdown.

However, the diode D acts as a large parasitic capacitance with respect to the input line during normal operation (when the input voltage is within the allowable range), and the operating speed of the input circuit when the input signal has a high frequency. Cause a decrease in.

Further, since the diode D is formed on the surface of the semiconductor substrate, the area occupied by the input protection circuit increases and the chip cost increases. Further, the diode D conducts in the forward direction due to overshoot or undershoot of the input signal, and carriers are injected into the semiconductor substrate.
This carrier may diffuse in the substrate and cause malfunction of a circuit formed on the substrate.

[0008]

As described above, the LSI
When implementing a non-linear element with a MOS structure on a substrate,
There are problems that the chip area increases and carriers injected into the non-linear element diffuse in the substrate, which may cause a malfunction of the circuit formed on the substrate.

Further, when a diode is used as a protection circuit for a MOS type input circuit of a conventional integrated circuit, the area occupied on the chip increases and the chip cost rises, and the diode is input during normal operation. There is a problem that it acts as a large parasitic capacitance to the signal line, which causes a decrease in the operating speed of the input circuit when the input signal has a high frequency.In addition, carriers generated by overshoot or undershoot of the input signal are Spread the
There is a problem that a circuit formed on the substrate may malfunction.

The present invention has been made to solve the above-mentioned problems, and is a MIM in which a thin insulating layer is formed on the lower layer polycrystalline silicon or the metal film and the upper wiring on the integrated circuit substrate. Due to the structure, it is possible to realize a resistive element with stable nonlinear characteristics, and when used in an input protection circuit of an integrated circuit, it enables high-speed operation of the input circuit and realizes an input protection circuit that occupies a small area on the chip. It is an object of the present invention to provide a possible semiconductor device and a manufacturing method thereof.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A first conductor formed on a semiconductor substrate; an insulating layer formed on the first conductor; and a second conductor formed of a metal nitride film on the insulating layer. Is characterized by.

The method of manufacturing a semiconductor device according to the present invention is
A step of forming a first wiring layer on a semiconductor substrate; a step of oxidizing the first wiring layer to form an insulating film made of an oxide on the surface thereof; and a metal nitride film on the insulating film. And a step of forming a second wiring layer made of

[0013]

The semiconductor device of the present invention has a MIM structure in which a second conductor having a metal nitride film is formed on a first conductor such as polycrystalline silicon, amorphous silicon or a metal film via a thin insulating layer. As a result, a resistance element having stable nonlinear characteristics is realized.

Therefore, by forming a thin insulating layer between the wiring layers of the semiconductor element of the integrated circuit, it is possible to realize a resistance element having a non-linear characteristic, and if it is used in the input protection circuit of the integrated circuit, the high speed of the input circuit can be achieved. It becomes possible to realize an input protection circuit which can operate and occupies a small chip area.

In the present invention, the size of the non-linear element can be realized with a contact size (for example, several μm ² ). Then, by adjusting the element area and the film thickness of the insulating film, a sufficiently large resistance value can be realized in the allowable input voltage range, and the resistance value decreases with respect to an excessive input voltage such as static electricity, The gate of the input MOS transistor can be protected from electrostatic breakdown. Moreover, since carriers are not generated in the substrate due to slight undershoot and overshoot of the input signal, there is no risk of carriers spreading in the substrate and causing malfunction of the circuit.

The semiconductor device manufacturing method of the present invention is
In order to realize the MIM structure, the first conductor is oxidized to form a thin insulating film on the surface thereof, and the second conductor made of a metal nitride film is formed thereon, so that the insulating film made of an oxide is formed. It is possible to form a thin insulating layer with high yield without reducing hydrogen. Further, by adding one PEP process to the usual MOSLSI manufacturing process, it becomes possible to form the non-linear element in the MOSLSI.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 and 2 show a manufacturing process according to an embodiment of a method for manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 1A, the field oxide film 11 is formed on the semiconductor substrate 10 by a normal process.
After forming a, the well region 11b, and the gate insulating film 11c, the first layer wiring (MOS
(Including the gate electrode of the transistor) 12 is formed. Further, the drain / source region 11 of the MOS transistor
After forming d, a CVD oxide film (SiO ₂ ) 13 and a BPSG (boron phosphorus silicate glass) film 14 are formed as an interlayer insulating film by a (chemical vapor deposition) method, and POc is formed.
Flattening treatment is performed by a method such as heat treatment in an atmosphere of l ₃ .

Next, on the first-layer wiring 12, a portion where a resistance element having a non-linear characteristic is to be formed and a normal contact formation scheduled region are once exposed to the surface, so that a portion to be exposed is exposed. Photolithography is performed so as to mask the other parts with the resist pattern 15, and anisotropic etching such as RIE (reactive ion etching) is used to form the BPSG insulating film 14 and the CVD film.
The oxide film 13 and the gate insulating film 11c are etched. In this case, if the device is large enough that the conversion difference is not important, the CDE (chemical dry etching) method or N
Etching using H ₄ F (ammonium fluoride) may be performed.

Next, as shown in FIG. 1B, after the resist pattern 15 is peeled off, the exposed portion due to the etching is oxidized by thermal oxidation to oxidize the exposed portion of the first insulating film 16 made of an oxide. To form. In this case, thermal oxidation can be performed by various methods, for example, 900 ° C.
If the treatment is performed in the oxygen atmosphere for 10 minutes, a thin oxide film 16 of about 15 nm can be formed on the exposed portion of the polycrystalline silicon 12, and the portion covered with the BPSG film 14 is hardly oxidized.

Next, as shown in FIG. 2A, the first
After depositing an electrode material made of a metal nitride film 17 on the insulating film 16, the lithography process is performed so that the resist pattern 18 is masked except for a necessary portion of the electrode material, and the RIE method is used. The MIM structure is obtained by etching the metal nitride film 17. In this case, in the step of depositing and etching the metal nitride film 17, the TiN is formed by sputtering Ti, for example, in a nitrogen atmosphere, and then the etching processing time is usually set when etching the TiN. By slightly extending the process, the thin oxide film 16 existing in the portion that will be the normal contact region can be removed at the same time.

After that, the resist pattern 18 is peeled off, and a second step is performed by a normal process as shown in FIG.
The wiring 19 of the layer is formed. In this case, Ti, which is a normal wiring material, is sputtered, and subsequently, TiN and Al are sputtered, followed by etching to form the second-layer wiring 19. After that, the protective insulating film 20 is formed on the entire surface.

In the manufacturing process of the above embodiment, MIM
In order to realize the structure, the first-layer wiring (first conductor) 12 made of polycrystalline silicon is oxidized to form an oxide (thin insulating film) 16 on the surface thereof, and an electrode material is formed thereon. Since the metal nitride film 17 (second conductor) is formed as a thin film, the thin insulating layer 16 can be formed in good yield without reducing the insulating film made of an oxide.

In this case, the MOS LSI can be manufactured by adding one PEP process to the usual MOS LSI manufacturing process.
It becomes possible to form so that a non-linear element may be incorporated into. If the electrode material 17 is formed without using the above-described method, the first insulating film 16 may be reduced, and the yield is reduced in the process of simultaneously forming many elements such as an integrated circuit. To do.

The nonlinear element can be formed in a small area and its stray capacitance can be reduced not only by the manufacturing process of the above embodiment but also by the method of locally oxidizing the first wiring layer 12.

In addition, the MIM structure obtained by the manufacturing process of the above-mentioned embodiment has the first conductor 1 such as polycrystalline silicon.
Since the second-layer wiring 19 having the metal nitride film 17 is formed on the second insulating layer 16 via the thin insulating layer 16, it is possible to realize a resistance element having stable nonlinear characteristics. In this case, by forming the thin insulating layer 16 as described above between the wiring layers of the semiconductor element of the integrated circuit, the size of the non-linear element can be realized with a contact size.

FIG. 3 shows an example of voltage / current characteristics and resistance characteristics of the nonlinear element having the MIM structure formed as described above. In this example, as the thin insulating layer 16,
The case where the film thickness is about 2 nm and the area is 2 μm square is shown, and the characteristics can be adjusted by changing these values.

In the above embodiment, the polycrystalline silicon 1
Although the non-linear element having the thin insulating layer 16 is formed between 2 and TiN 17, the non-linear element can be formed between the metal wirings according to the above-described embodiment. In this case, in order to ensure the uniformity of the thin insulating layer between the metal wirings, it is desirable to use a natural oxide film of metal.

Further, when the surface of the first conductor 12 is TiN, TiO having a thickness of several tens nm is formed in the atmosphere, so this TiO film is used as an insulating layer. Also, the first
When the surface of the conductor 12 is Al, an AlO film is used as an insulating layer.

That is, as the first conductor, Si, G
Any of e, Ti, Al, and TiN can be used. Further, as the second conductor, TiN, WN, Al
Any of N can be used.

In general, since the insulating film of the element having the MIM structure is formed thin in order to obtain necessary electrical characteristics, even if the potential difference between both electrodes is zero, the tunnel probability is considerably high and the finite resistance is limited. The value shows the value and can be practically used even if the composition of the insulating film deviates from stoichiometry and a leak current occurs. Therefore, when the nonlinear element having the MIM structure formed as described above is used in the input protection circuit of the integrated circuit as described later, a leak current of about several tens of μA is allowed.

FIG. 4 shows an example of use of a non-linear element having an MIM structure formed in an integrated circuit as described above.
1 shows an example of an input protection circuit of an S-type integrated circuit. That is, the input protection circuit is configured by connecting the non-linear element 42 between the signal input pad 40 and the input signal line of the input circuit (for example, the CMOS inverter circuit 41) and the ground line.

In the above input protection circuit, the area of the non-linear element 42 and the film thickness of the insulating film are appropriately adjusted so that the non-linear element has a sufficiently large resistance value within the normal input voltage range. , Acts as a simple load element. In this case, for example, if a resistance value of about 500 KΩ is applied when an input voltage of 5 V is applied, a leak current of 10 μA is generated, but this is within the allowable range for a general logic type LSI.

On the other hand, when the voltage exceeds the normal input voltage range and becomes excessive (for example, when static electricity is input), for example, when the voltage becomes 10 times (50 V) 5 V, the resistance value of the nonlinear element 42 is increased. Becomes 1/10 of the above 500 KΩ (about 50 KΩ), and it becomes possible to release a large amount of charges to the ground potential in a short time, shorten the time for applying a high voltage to the gate of the input MOS transistor, and reduce its gate. The oxide film can be protected from electrostatic breakdown.

Moreover, since the characteristic of the non-linear element 42 is almost independent of the positive / negative of the voltage between both electrodes and the characteristic is determined by the potential difference, in the conventional input protection circuit, the input signal line, the power supply line and the ground line are connected. Input protection can be performed with a number smaller than the number (two) of diodes connected one by one between them.

FIG. 5 shows, as a modification of the input protection circuit of FIG. 4, one non-linear element 42 is connected between each of the input signal line, the power supply line and the ground line.

Further, since the non-linear element 42 does not generate carriers in the substrate due to slight undershoot and overshoot of the input signal, the carriers may diffuse in the substrate and cause malfunction of the circuit. Absent.

Further, since the non-linear element 42 can be realized with almost a contact size, it can be realized with a smaller area than the diode used in the conventional input protection circuit.
Moreover, since the stray capacitance depending on this area can be realized small, the chip occupation area of the input protection circuit can be small,
High-speed operation of the input circuit is possible.

When the purpose is to protect the gate oxide film of the input MOS transistor as described above, the thickness of the insulating film of the non-linear resistance element 42 is made smaller than that of the gate oxide film. It is necessary to make it easy for the FN current to flow.

FIG. 6 shows another modification of the input protection circuit. In this input protection circuit, the first resistor element R1 is inserted and connected to the input signal line between the signal input pad 40 and the nonlinear element 42, and the nonlinear element 42 and the input M
The second resistance element R2 is inserted and connected to the input signal line between the gate of the OS transistor.

As a result, when an excessive voltage is input, the gate of the MOS element is discharged according to the time constant of the resistance element and the gate capacitance of the input MOS transistor, and the voltage applied to the gate of the input MOS transistor is the above. Since it is divided by the resistance value of the resistance element and the resistance value of the non-linear element, the application time of the high voltage to the gate of the input MOS transistor can be extremely shortened, and the protection performance is improved.

FIG. 7 shows another modification of the input protection circuit. In this input protection circuit, the nonlinear element 42 and the diode D are connected in series between the input signal line, the power supply line, and the ground line, respectively.

Thus, within the normal input voltage range,
The diode D is in the off state, the load capacitance on the input signal line becomes light, and a small amount of current flows in response to slight undershoot and overshoot of the input signal.

On the other hand, when an excessive voltage is input, the diode D is turned on, the nonlinear element 42 has a low resistance value, and the gate oxide film of the input MOS transistor can be protected from electrostatic breakdown. The non-linear element according to the present invention can be used in a general circuit without any problem, and is not particularly limited to the protection circuit.

[0045]

As described above, according to the present invention, a resistance element having stable nonlinear characteristics can be formed on polycrystalline silicon or a metal film, and a thin insulating layer is formed between wiring layers of a semiconductor element. When the resistance element formed by the above is used for the input protection circuit, it is possible to provide a semiconductor device capable of operating the input circuit at high speed and realizing an input protection circuit that requires a small chip area, and a manufacturing method thereof. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of the process according to an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 3 is a diagram showing an example of voltage / current characteristics and resistance characteristics of a non-linear element having a MIM structure formed by the steps of FIGS.

FIG. 4 is a circuit diagram showing an example of an input protection circuit of an integrated circuit using a non-linear element formed by the steps of FIGS. 1 and 2.

5 is a circuit diagram showing a modified example of the input protection circuit of FIG.

FIG. 6 is a circuit diagram showing another modification of the input protection circuit of FIG.

FIG. 7 is a circuit diagram showing still another modification of the input protection circuit of FIG.

FIG. 8 is a circuit diagram showing an example of an input protection circuit of a conventional MOS integrated circuit.

[Explanation of symbols]

12 ... First layer wiring (including gate electrode), 13 ... C
VD oxide film film, 14 ... BPSG film, 15, 18 ... Resist pattern, 16 ... First insulating film (thin oxide film), 17
... Metal nitride film (TiN), 19 ... Second layer wiring, 2
0 ... Protective insulating film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 H01L 27/04 P

Claims (5)

[Claims] 1. A second conductor comprising a first conductor formed on a semiconductor substrate, an insulating layer formed on the first conductor, and a metal nitride film formed on the insulating layer. A semiconductor device comprising a resistance element having a non-linear characteristic consisting of: 2. The semiconductor device according to claim 1, wherein the insulating layer is an oxide film formed by oxidizing the surface of the first conductor. 3. The semiconductor device according to claim 1, wherein the resistance element is connected between an input signal line of a MOS type input circuit of an integrated circuit and a ground line or a power supply line, and is used as an input protection circuit. A semiconductor device characterized by: 4. A step of forming a first wiring layer on a semiconductor substrate, a step of forming an insulating film made of an oxide on the surface of the first wiring layer by oxidizing the first wiring layer, and a step of forming the insulating film on the insulating film. And a step of forming a second wiring layer made of a metal nitride film. 5. A step of forming a first layer wiring made of polycrystalline silicon on a semiconductor substrate, and forming an interlayer insulating film on the wiring, and then having a non-linear characteristic on the polycrystalline silicon. Masking a portion other than a portion where a resistance element is to be formed with a resist, performing anisotropic etching on the interlayer insulating film to expose a part of the polycrystalline silicon, and an exposed portion of the polycrystalline silicon. A step of forming an insulating film made of an oxide on the surface by oxidation by thermal oxidation, and depositing an electrode material made of a metal nitride film on the insulating film, and then, except for a necessary portion of the electrode material. Is masked with a resist, and anisotropic etching is performed on the electrode material.