JPH08330595A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE: To prevent generation of point defects due to the disconnection of a gate lead wire, by forming a connection part in a region where a plurality of electrodes do not intersect semiconductor channel layer, while excepting the region where the gate electrodes are connected with a gate wiring path. CONSTITUTION: Gate electrodes 2 connected with a crate wiring path 3 are arranged above a semiconductor channel layer. A plurality of the gate electrodes 2 are formed in the channel length direction for a thin film transistor. By using a side etching method offset structure is formed in the channel layer, and a pattern is formed to have a connection part in a region where a plurality of the gate electrodes do not intersect the semiconductor channel layer, while excepting the region where the gate electrodes are connected with the gate wiring path 3. In a display of an active matrix using a thin film transistor of top gate structure and dual structure, point defects can be remarkably reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to thin film transistors for active matrix displays. In particular,
A device structure for relieving the occurrence of defects in the manufacture and obtaining high productivity will be disclosed.

[0002]

2. Description of the Related Art Liquid crystal display devices (LCDs) are the mainstream of flat panel displays, and thin film transistors (TFTs) are used to meet the demands for colorization, high speed, and high image quality. The active matrix type LCD has been put to practical use.

Amorphous silicon (amorphous silicon, hereinafter abbreviated as a-Si) is generally used as a semiconductor layer in a TFT. However, when a larger screen / higher density display is required, it is necessary to write pixels in a short time. One of the methods for achieving this is to use polycrystalline Si, which has a higher mobility than a-Si.

Further, by using polycrystalline Si,
It is possible to improve the aperture ratio by miniaturizing the TFT and to integrate the driving circuit on the same substrate. As a result, the TFT-LCD using polycrystalline Si will be the next generation LC
Promising as D.

In order to manufacture a polycrystalline Si TFT, 10
A manufacturing method using a high temperature process of around 00 ° C has already been put into practical use. However, it must use a quartz substrate that can withstand high temperatures. On the other hand, a high-speed beam annealing method using a laser beam was used to obtain a-Si.
Is polycrystallized, 600 ℃ or less, preferably 400 ℃
It is possible to obtain polycrystalline Si by the following low temperature process. For example, Japanese Patent Laid-Open No. 4-226039 can be cited. In the case of this manufacturing method, a normal glass substrate for LCD (such as AN635 of Asahi Glass Co., 7059 of Corning Co., Ltd.) can be used.

As a result, even an LCD having a substrate size for a larger screen can be manufactured while maintaining high productivity. By using a normal glass substrate for LCD, most of the conventional processes can be used as they are. That is, the conventional large-scale a-Si TFT process can be used.

At present, most a-Si TFTs employ a bottom gate structure in which the gate electrode layer is located below the semiconductor channel layer. On the other hand, polycrystalline Si
In the TFT using, the gate electrode layer often has a top gate structure which is located above the semiconductor channel layer.

One of the reasons is that the CMO is obtained by the ion implantation method.
Since the S circuit can be easily manufactured, it is convenient for circuit integration. Depending on the process, the temperature of the gate electrode cannot be withstood during the formation of the polycrystalline Si, and thus the top gate, which is to be formed later, may be essential.

A characteristic feature of polycrystalline Si is a-Si.
The leakage current is larger than that of the above. There are various methods to solve this problem, and one method is to connect a plurality of transistors in series. For example,
Japanese Examined Patent Publication 5-44195 can be cited.

A TFT in which two transistors are connected in series
2 has a shape in which two gate electrodes are provided in the direction of the channel length of one TFT as shown in FIG. 2, and this is hereinafter referred to as a dual gate structure.

On the other hand, a TFT having one normal gate electrode as shown in FIG. 3 is called a single gate structure. The dual gate structure has the effects of reducing the leak current and improving the breakdown voltage between the source and drain.

For the above reasons, when polycrystalline Si is used as a pixel driving TFT of a liquid crystal display,
A top gate structure and a dual gate structure are often used.

However, in the top gate structure, since the gate electrode is located above the Si layer, the gate electrode is S.
The wire may break on the step of i. This state is shown in FIGS. 4 and 6. If this disconnection occurs on the step on the gate wiring bus side, the scanning potential cannot be applied to the gate electrode and TF
Since T does not operate normally, the TFT cannot operate normally, resulting in a point defect of the display.

Thus, in the case of the dual gate structure,
Even if only one of the two gate electrodes is broken, the TFT cannot operate normally. Therefore, the probability of point defects occurring is higher than that in the single gate structure. And this probability is closely related to the geometrical dimensions of the device structure. That is, the entire circuit is not reduced so much, and for example, the semiconductor channel of the TFT (L in FIG.
When the length is set to about μm and is relatively long, even if a cut is made in the electrode, it is less likely to be broken, which is not a big problem. However, as the channel length L becomes smaller as the liquid crystal display becomes finer, it becomes a serious problem.

[0015]

A TFT for driving a pixel of a TFT active matrix display made of polycrystalline Si.
If a top gate structure and a dual gate structure are used to form the structure, point defects due to the disconnection of the gate electrode are more likely to occur than in the case of the single gate structure. The object of the present invention is to eliminate such drawbacks.

[0016]

The present invention has been made to solve the problems in the preceding paragraph, that is, the gate electrode connected to the gate wiring bus is arranged above the semiconductor channel layer and In a thin film transistor in which a plurality of gate electrodes are provided in the channel length direction per thin film transistor, the plurality of gate electrodes have a connecting portion in a region which does not intersect with the semiconductor channel layer and which is not connected to the gate wiring bus. A thin film transistor characterized by the above. This is called the first invention.

Further, in the first invention, there is provided a thin film transistor characterized in that each of the plurality of gate electrodes has a width of 8 μm or less. This is called the second invention.

Also, in the first or second invention, there is provided a thin film transistor characterized in that the width of the connecting portion is set to 2 to 6 μm. This is called the third invention.

Further, in any one of the first to third inventions, the distance between the connecting portion and the semiconductor channel layer is 2 to
A thin film transistor having a thickness of 8 μm is provided. This is called the fourth invention.

Further, in any one of the first to fourth inventions, there is provided a thin film transistor characterized in that the thickness of the gate electrode is 100 nm or more and the semiconductor channel layer is 50 nm or more. This is called the fifth invention.

Further, there is provided a thin film transistor according to any one of the first to fifth inventions, which has a pixel area of 20000 μm ² or less. This is the sixth
Called invention.

Also, in any one of the first to sixth inventions, there is provided a thin film transistor characterized in that the gate electrode is made of one kind of metal. This is called the seventh invention.

Further, in the invention of any one of the seventh aspect, there is provided a thin film transistor characterized in that the gate electrode is made of Cr. This is called the eighth invention.

Further, in any one of the first to eighth inventions, there is provided a thin film transistor characterized in that a glass substrate is used and polycrystalline Si is used for a semiconductor channel. This is called the ninth invention.

A method of manufacturing a thin film transistor in which a gate electrode connected to a gate wiring bus is arranged above a semiconductor channel layer, and a plurality of gate electrodes are provided in the channel length direction for each thin film transistor,
An offset structure is formed in the semiconductor channel layer by using a side etching method, and the plurality of gate electrodes have a connection portion in a region which does not intersect the semiconductor channel layer and which is not connected to the gate wiring bus. Provided is a method of manufacturing a thin film transistor, which is characterized by forming a pattern on the substrate.

[0026]

In the dual gate structure, there are four locations (a, b, c, d in FIG. 5) where the gate electrode crosses the step of the Si island per TFT. Conventionally, when a disconnection occurs in one of two locations (a and c in FIG. 5) on the gate wiring bus side (FIG. 6), the correct potential cannot be applied to the gate electrode, and the TFT cannot operate normally. .

On the other hand, in the present invention, if only one portion is broken (FIG. 7), a correct potential is applied to the gate electrode, so that the TFT operates normally.

The probability of disconnection at one step is p (0 <
If p <1) and they are independent of each other, the probability that one TFT cannot operate normally due to disconnection of the gate electrode can be approximated as shown in Table 1 assuming that the channel length L per gate electrode is equal.

[0029]

[Table 1]

In the case of the dual gate, the probability of failure occurrence is 1- (1-p) ² = for the probability p of failure occurrence in a single gate, in other words, one gate electrode.
This is because 2p−p ² ≈2p (because normally p << 1). That is, in the case of the dual gate, a point defect due to the disconnection of the gate electrode occurs with a probability about twice that of the single gate. If L is equal, dual gate TF
Since the on-current at T is smaller than that at the single-gate TFT, in most cases, L is made smaller in the dual-gate TFT in order to make the on-current available.

Then, as described above, the disconnection is more likely to occur and p becomes larger, so that the probability of becoming a point defect becomes even larger. As a result, 2 of single gate
More than double.

According to the present invention, among all the steps (a), (b), (c) and (d) in FIG. 5, (1) when all four are disconnected,
(2) When three are disconnected, (3) When two are disconnected (except when both b and d are disconnected)
Moreover, the TFT cannot operate normally. In this case, the total probability that a defect will occur is as shown in the following formula 1.

[0033]

[Number 1] ^{p 4 +4 (1-p)} p 3 +5 (1-p) 2 p 2 = 5p 2 -6p 3 + 2p 4 ≒ 5p

Since p is generally very small, 5
p ² << 2p. That is, according to the present invention, the probability that point defects will occur due to disconnection of the gate electrode is significantly reduced.

There is also a certain relationship with the geometrical dimensions of each part of the thin film transistor. For example, the width of the gate electrode is substantially the channel length itself, and the area occupied by each thin film transistor is limited, so that it cannot be made too long. Usually, it is set to 8 μm or less (reference numeral D in FIG. 7). The gap between the two gate electrodes is about 3 to 8 μm (reference numeral C in FIG. 7). as well as,
The width of the connecting portion that connects the two gate electrodes is set to be approximately the same as the width of the gate electrode, but is set to approximately 2 to 6 μm (reference numeral B in FIG. 7). The present invention will be described below with reference to the drawings.

[0036]

【Example】

Example 1 A TFT active matrix type liquid crystal display was manufactured. A coplanar type TFT was used.

First, a SiN _x film having a thickness of 200 nm and an a-Si film as a base film is formed on a glass substrate by plasma CVD.
Of 100 nm and a SiN _x film of 50 nm were formed. next,
A necessary portion of a-Si was polycrystallized by HSBA (high-speed beam annealing method using an argon ion laser). After removing the SiN _x film from this substrate,
Was patterned into an island shape.

A SiO ₂ (silicon dioxide) film having a thickness of 120 nm was formed thereon as a gate insulating film by plasma CVD. Then, a 300 nm Cr film was formed by sputtering and patterned to form a gate electrode and a gate wiring bus. At this time, patterning is performed so as to have a dual gate structure, but the two gate electrodes are provided so as to be connected to each other on the side opposite to the gate wiring bus. The channel length L was 5 μm per gate electrode.

The gap between the two gate electrodes was 5 μm. The gate electrode was provided so as to be connected to the gate electrode bus located in one region with the semiconductor channel layer sandwiched therebetween, and to be connected in the remaining other region. It has a U-shaped pattern. The connection portion was provided so as to be sufficiently separated from the semiconductor channel layer and not to affect the occupied area. The distance from the semiconductor channel layer was 3 μm. further,
The SiO ₂ film was etched using this Cr as a mask.

Next, the gate electrode Cr was side-etched by immersing it again in the Cr etching solution. After that, P (phosphorus) ions were implanted with an ion implanter. Since the side etching was performed, an offset region was formed between the ion-implanted region and the region to be the channel. Here, an offset region of less than 1 μm was formed. The presence of this offset region improves the breakdown voltage between the source and drain. As described above, the disconnection of the gate electrode occurs mainly in this side etching step.

Subsequently, a SiN _x film was formed to a thickness of 300 nm by plasma CVD in order to insulate the gate electrode bus (wiring line) and the source / drain electrode bus (wiring). An ITO film to be a pixel electrode was formed to a thickness of 50 nm by sputtering and patterned. Then, the SiN _x film was patterned to make contact between the source / drain electrode bus and Si.

A 50 nm thick film of Cr and a 300 nm thick film of Al were formed thereon by sputtering, and the Al and Cr films were patterned to form source / drain electrode buses. Finally, a SiN _x film having a thickness of 400 nm was formed as a protective film by CVD and patterned. In this way, the source / drain electrode bus has a two-layer metal structure.

As described above, T using polycrystalline Si is used.
An FT substrate was obtained. A pixel TFT and its peripheral portion are shown in FIG. The number of TFTs on the substrate is about 300,000. This TF
A liquid crystal display was produced by combining the T substrate and the counter substrate. Further, using the same process, a substrate of a conventional dual gate structure TFT (FIG. 2) was produced and an LCD was produced. The number of TFTs in this LCD is about 330,000. The channel length, channel width, wiring width, etc. of the TFT are the same.

An image was displayed on the liquid crystal display thus obtained, and the number of point defects was examined. The conventional type is
Although depending on the substrate, tens to hundreds and dozens of point defects were observed. On the other hand, in the case where two gate electrodes are connected to each other on the opposite side of the gate wiring bus according to the present invention, only 0 to several point defects were observed.

[0045]

As described above, according to the present invention,
In an active matrix display using a TFT having a top gate structure and a dual gate structure, it was possible to significantly reduce point defects.

The present invention uses a large-sized glass substrate (diagonal size is 8 size≈20 cm or more, 300,000 pixels or more (eg, 640
A high production yield could be obtained in the production of a low-temperature formed polycrystalline SiTFT array substrate using a (× 480 active matrix display)). In particular, it has become possible to relieve connection defects at the stepped portions of a large number of thin film transistors provided in a large substrate area, and it is possible to easily form a liquid crystal display element free from display point defect defects.

Further, it has become possible to prevent wire breakage without using the conventionally known taper treatment of the Si layer. Therefore, it is possible to avoid the design rule of the thin film transistor which is required depending on the taper process. For example, it is not necessary to increase the channel width to secure the on-current, and in that case, it is possible to overcome secondary negative factors such as an increase in off-current and an increase in parasitic capacitance.

The gate electrode and the gate electrode bus are C
It is preferable to provide a single layer of metal such as r from the viewpoint of the entire manufacturing process. In this case, if the thickness of the metal is increased, stress is likely to occur, so that disconnection at a step is likely to occur. Further, the thickness of the internal semiconductor channel layer is also involved, and a certain thickness is required from the viewpoint of electrical characteristics and the like. Even in such a case, by using the present invention, a high manufacturing yield can be obtained. be able to.

As described above, according to the present invention, not only the defect relief can be achieved, but also stable productivity and high product performance can be obtained without affecting other manufacturing processes.

Further, the present invention can be applied in various ways within the range of not impairing its effect.

[Brief description of drawings]

FIG. 1 is a plan view illustrating an embodiment of the present invention.

FIG. 2 is a plan view of a conventional dual gate structure TFT.

FIG. 3 is a plan view of a conventional single gate structure TFT.

FIG. 4 is a cross-sectional view showing a disconnection state of a gate electrode.

FIG. 5 is a plan view showing a portion where a gate electrode crosses a step of a Si island in a dual gate structure TFT.

FIG. 6 is a plan view showing a state in which a gate electrode is broken in a conventional dual gate structure TFT.

FIG. 7 is a plan view showing how the gate electrode is broken in the present invention.

[Explanation of symbols]

 1: Si Island 2: Gate Electrode 3: Gate Wiring Bus 4: Source Electrode 5: Source Wiring 6: Drain Electrode 7: Pixel Electrode (ITO) 8: Gate Insulating Film 9: Base Film 10: Glass Substrate

Claims (9)

[Claims] 1. In a thin film transistor in which a gate electrode connected to a gate wiring bus is disposed above a semiconductor channel layer, and a plurality of gate electrodes are provided in the channel length direction per thin film transistor, the plurality of gate electrodes are provided. A thin film transistor having a connection portion in a region which does not intersect with the semiconductor channel layer and which is not connected to the gate wiring bus. 2. The width of each of the plurality of gate electrodes is 8 μm.
The thin film transistor according to claim 1, wherein the thickness is set to m or less. 3. The thin film transistor according to claim 1, wherein the width of the connection portion is 2 to 6 μm. 4. The thin film transistor according to claim 1, wherein the distance between the connection portion and the semiconductor channel layer is 2 to 8 μm. 5. The thin film transistor according to claim 1, wherein the gate electrode has a thickness of 100 nm or more and the semiconductor channel layer has a thickness of 50 nm or more. 6. The thin film transistor according to claim 1, wherein the pixel area is 20000 μm ² or less. 7. The thin film transistor according to claim 1, wherein the gate electrode is made of one kind of metal. 8. The thin film transistor according to claim 7, wherein the gate electrode is made of Cr. 9. A method of manufacturing a thin film transistor, wherein a gate electrode connected to a gate wiring bus is disposed above a semiconductor channel layer, and a plurality of gate electrodes are provided in the channel length direction for each thin film transistor. An offset structure is formed in the semiconductor channel layer by using an etching method, and the plurality of gate electrodes have a connection portion in a region which does not intersect with the semiconductor channel layer and which is not connected to the gate wiring bus. A method of manufacturing a thin film transistor, which comprises patterning.