JPH08330497A - Lead frame and semiconductor device having the same - Google Patents

Lead frame and semiconductor device having the same

Info

Publication number
JPH08330497A
JPH08330497A JP7133826A JP13382695A JPH08330497A JP H08330497 A JPH08330497 A JP H08330497A JP 7133826 A JP7133826 A JP 7133826A JP 13382695 A JP13382695 A JP 13382695A JP H08330497 A JPH08330497 A JP H08330497A
Authority
JP
Japan
Prior art keywords
lead frame
plating layer
minute
plated layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7133826A
Other languages
Japanese (ja)
Other versions
JP3127098B2 (en
Inventor
Masaaki Kato
正明 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP07133826A priority Critical patent/JP3127098B2/en
Publication of JPH08330497A publication Critical patent/JPH08330497A/en
Application granted granted Critical
Publication of JP3127098B2 publication Critical patent/JP3127098B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Led Device Packages (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain a strong adhesion with an adhesive agent and/or covering sealing resin by causing a plated layer to contain minute substances of the same composition as the adhesive agent, and causing the minute substances to be exposed above the surface of the plated layer. CONSTITUTION: On the surface of a lead frame 11, a semiconductor bare chip 12 is packaged with silver paste 13 interposed. Concretely, a raw material 14 for a lead frame of iron, copper alloy, iron-nickel alloy, etc., is coated with a primarily plated layer 16 containing minute epoxy balls 15 of the same composition as the silver paste 13. The primarily plated layer 16 is coated with a secondarily plated layer 17, and the minute epoxy balls contained in the primarily plated layer 16 protrude from the of the secondarily plated layer 17. Strong adhesion can be obtained since the silver paste 13 and the minute epoxy balls 15 have the same composition. In addition, it becomes possible to obtain bondability capable of excellent die bonding and wire bonding, since the surface of the lead frame is composed of a secondarily plated layer 17 of noble metals of silver, gold, and palladium.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップ搭載用の
リードフレームおよびこれを用いた半導体装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for mounting a semiconductor chip and a semiconductor device using the same.

【0002】[0002]

【従来の技術】従来のリードフレームを、例えば発光ダ
イオードランプ(LEDランプ)に使用されるリードフ
レームを用いて説明する。図6にそのリードフレームの
外観図を示す。
2. Description of the Related Art A conventional lead frame will be described using a lead frame used for a light emitting diode lamp (LED lamp), for example. FIG. 6 shows an external view of the lead frame.

【0003】従来のリードフレーム1は、チップ搭載用
リード2と結線用リード3とを有し、前記チップ搭載用
リード2の一端側には発光ダイオードチップを搭載する
反射カップ2aを備えてなる。図6中、4はタイバーで
あり、5は細条である。
A conventional lead frame 1 has a chip mounting lead 2 and a connection lead 3, and a reflection cup 2a for mounting a light emitting diode chip is provided at one end of the chip mounting lead 2. In FIG. 6, 4 is a tie bar, and 5 is a strip.

【0004】リードフレーム1を図7に従って具体的に
説明する。図7は、従来のリードフレームの製造工程図
である。
The lead frame 1 will be described in detail with reference to FIG. FIG. 7 is a manufacturing process diagram of a conventional lead frame.

【0005】前記リードフレーム1は、図7(a)に示
すようなリードフレーム素材(例えば、鉄,銅合金,鉄
ニッケル合金等)1aに、まず図7(b)に示すように
一次メッキ(銅メッキまたはニッケルメッキ)層1bが
形成され、さらに図7(c)に示すように二次メッキ
(銀メッキ,金メッキ又はパラジウムメッキ)層1cが
形成されてなる。
The lead frame 1 is formed by first plating a lead frame material (for example, iron, copper alloy, iron-nickel alloy, etc.) 1a as shown in FIG. 7 (a) with primary plating (see FIG. 7 (b)). A copper plating or nickel plating layer 1b is formed, and a secondary plating (silver plating, gold plating or palladium plating) layer 1c is further formed as shown in FIG. 7 (c).

【0006】該リードフレーム1を用いて発光ダイオー
ドランプ形成する際には、図6に示す前記素子搭載用リ
ード2の反射カップ2aに発光ダイオードチップが銀ペ
ーストを介して搭載され、該発光ダイオードチップと結
線用リード3の一端側とがボンディングワイヤにて接続
され、前記タイバー4を切断した後に透光性の封止用エ
ポキシ樹脂等の封止樹脂にて前記発光ダイオードチップ
及びリードフレーム1の一部が封止されてなる。前記リ
ードフレーム1の該封止樹脂にて封止されていない部分
には、場合によってその表面に半田メッキ或は錫メッキ
が施される。
When forming a light emitting diode lamp using the lead frame 1, a light emitting diode chip is mounted on the reflection cup 2a of the element mounting lead 2 shown in FIG. 6 through a silver paste, and the light emitting diode chip is mounted. And one end side of the connection lead 3 are connected by a bonding wire, and after cutting the tie bar 4, a part of the light emitting diode chip and the lead frame 1 is sealed with a sealing resin such as a translucent sealing epoxy resin. The part is sealed. A portion of the lead frame 1 which is not sealed with the sealing resin may be solder-plated or tin-plated on the surface in some cases.

【0007】[0007]

【発明が解決しようとする課題】上記リードフレーム1
は、その表面の二次メッキ層1c、即ち銀,金又はパラ
ジウムの表面がボンディング性に優れていることからダ
イボンドやワイヤーボンドには通常支障なく利用されて
いる。
The above-mentioned lead frame 1
Since the secondary plating layer 1c on the surface thereof, that is, the surface of silver, gold or palladium has excellent bonding properties, it is normally used for die bonding or wire bonding without any trouble.

【0008】しかしながら、これらボンディング性を損
なわないためには、メッキ表面の光沢度に注意を要し、
特にセレンSeの共析には注意を払わないと著しいボン
ディング性の低下を招くことになった。
However, in order not to impair these bonding properties, attention must be paid to the glossiness of the plating surface,
In particular, unless paying attention to the co-deposition of selenium Se, the bondability is remarkably deteriorated.

【0009】また、最適なボンディング性を得るために
は、高価な貴金属(銀、金、パラジウム等)をある一定
厚みメッキしなければならなく、コストアップの要因と
なっていた。
Further, in order to obtain the optimum bondability, expensive precious metal (silver, gold, palladium, etc.) must be plated to a certain thickness, which has been a factor of cost increase.

【0010】さらに、半導体チップをダイボンドするた
めの銀ペーストの主成分が銀とエポキシ樹脂であり、リ
ードフレーム1との密着性に関与しているのはそのエポ
キシ樹脂であり、リードフレーム1の表面の銀,金,パ
ラジウムのいずれもそのエポキシ樹脂との密着性が良く
なかった。
Further, the main components of the silver paste for die-bonding the semiconductor chip are silver and epoxy resin, and it is the epoxy resin that is involved in the adhesiveness with the lead frame 1, and the surface of the lead frame 1 None of the silver, gold and palladium had good adhesion to the epoxy resin.

【0011】加えて、リードフレーム1を封止する封止
樹脂についても、封止用エポキシ樹脂によるパッケージ
を行うと、その境目に剥離が生じ、水分の浸透が発生し
たりした。 本発明は、上記課題に鑑み、塗布される接着剤及び又は
被覆される封止樹脂との強固な密着性が得られるリード
フレームおよびこれを用いた半導体装置を提供すること
を目的とするものである。
In addition, with respect to the encapsulating resin for encapsulating the lead frame 1, when the encapsulating epoxy resin is used for packaging, peeling occurs at the boundary and water penetration occurs. In view of the above problems, the present invention has an object to provide a lead frame and a semiconductor device using the same, which can obtain strong adhesion with an applied adhesive and / or a sealing resin. is there.

【0012】[0012]

【課題を解決するための手段】本発明の請求項1記載の
リードフレームは、リードフレーム素材と、該リードフ
レーム素材を被覆するメッキ層とを備え、該メッキ層表
面に半導体チップが接着剤を介して搭載されるリードフ
レームにおいて、前記メッキ層は前記接着剤と同一組成
からなる微小物体を含有してなり、該微少物体がメッキ
層表面より露出してなることを特徴とするものである。
A lead frame according to claim 1 of the present invention comprises a lead frame material and a plating layer covering the lead frame material, and the semiconductor chip has an adhesive on the surface of the plating layer. In the lead frame mounted via the above, the plating layer contains a minute object having the same composition as the adhesive, and the minute object is exposed from the surface of the plating layer.

【0013】また、本発明の請求項2記載のリードフレ
ームは、前記メッキ層が前記微少物体を含有しリードフ
レーム素材を被覆する一次メッキ層と、貴金属よりなり
前記微少物体を外部に露出させた状態で前記一次メッキ
層を被覆する二次メッキ層とからなることを特徴とする
ものである。
According to a second aspect of the present invention, the lead frame is made of a noble metal and a primary plating layer in which the plating layer contains the minute object and covers the lead frame material, and the minute object is exposed to the outside. It is characterized by comprising a secondary plating layer which covers the primary plating layer in a state.

【0014】さらに、本発明の請求項3記載のリードフ
レームは、半導体チップの搭載部表面及び又はワイヤー
ボンド部表面に露出する微小物体を除去してなることを
特徴とするものである。
Further, the lead frame according to claim 3 of the present invention is characterized in that minute objects exposed on the surface of the mounting portion of the semiconductor chip and / or the surface of the wire bond portion are removed.

【0015】加えて、本発明の請求項4記載の半導体装
置は、上記リードフレームを備えてなる半導体装置であ
って、前記リードフレームは反射カップを備え、該反射
カップ内に異なる発光色の複数個の発光チップが配置さ
れ、該反射カップ内面の微少物体がその表面より突出し
てなることを特徴とするものである。
In addition, a semiconductor device according to a fourth aspect of the present invention is a semiconductor device including the lead frame, wherein the lead frame includes a reflection cup, and a plurality of different emission colors are provided in the reflection cup. One light emitting chip is arranged, and a minute object on the inner surface of the reflection cup is projected from the surface.

【0016】加えて、本発明の請求項5記載の半導体装
置は、上記リードフレームを備えてなる半導体装置であ
って、前記リードフレームの一部分が前記微小物体と同
一組成からなる封止樹脂にて封止されてなることを特徴
とするものである。
In addition, a semiconductor device according to a fifth aspect of the present invention is a semiconductor device including the lead frame, wherein a part of the lead frame is made of a sealing resin having the same composition as the minute object. It is characterized by being sealed.

【0017】加えて、本発明の請求項6記載の半導体装
置は、前記リードフレームの封止樹脂より突出する部分
表面に露出する微小物体を除去してなることを特徴とす
るものである。
In addition, a semiconductor device according to a sixth aspect of the present invention is characterized in that a minute object exposed on a partial surface of the lead frame protruding from the sealing resin is removed.

【0018】[0018]

【作用】上記構成によれば、本発明の請求項1記載のリ
ードフレームは、その表面、即ちメッキ層表面に露出す
る微小物体とメッキ層表面に塗布される接着剤とが同一
組成であることから、互いが強い密着力で結び付き半導
体チップを強固に固定することができる。 また、本発明の請求項2記載のリードフレームは、微少
物体が露出する部分以外が貴金属よりなる二次メッキ層
にて被覆されてなる構成なので、二次メッキ層表面のボ
ンディング性を向上することができる。
According to the above structure, in the lead frame according to claim 1 of the present invention, the minute object exposed on the surface, that is, the surface of the plating layer and the adhesive applied on the surface of the plating layer have the same composition. Therefore, the semiconductor chips can be firmly fixed to each other with a strong adhesion. Further, since the lead frame according to claim 2 of the present invention is configured such that the portion other than the portion where the minute object is exposed is covered with the secondary plating layer made of a noble metal, the bonding property of the surface of the secondary plating layer is improved. You can

【0019】さらに、本発明の請求項3記載のリードフ
レームは、半導体チップの搭載部表面及び又はワイヤー
ボンド部表面に露出する微小物体を除去してなる構成な
ので、その表面が梨地状で表面積が広くなり、接着剤と
リードフレームとの密着性を向上することができ、また
ワイヤーボンドのボンディング性を向上することができ
る。
Furthermore, since the lead frame according to claim 3 of the present invention has a structure in which minute objects exposed on the surface of the mounting portion of the semiconductor chip and / or the surface of the wire bond portion are removed, the surface is satin-like and has a surface area. It becomes wider, the adhesiveness between the adhesive and the lead frame can be improved, and the bondability of the wire bond can be improved.

【0020】加えて、本発明の請求項4記載の半導体装
置は、上記リードフレームに反射カップを備え、該反射
カップ内に発光色の異なる複数個の発光チップが配置さ
れ、該反射カップ内面の微少物体がその表面より突出し
てなる構成なので、複数個の発光チップより出射される
光は反射カップ内のリードフレーム表面で突出する微小
物体によって反射を繰り返し、該反射カップ内での光反
射を拡散することになり、複数個の発光チップの同時発
光時の色混合性を向上することができる。 加えて、本発明の請求項5記載の半導体装置は、上記リ
ードフレームの一部分が上記微小物体と同一組成からな
る封止樹脂にて封止されてなる構成なので、リードフレ
ームと封止樹脂との間においても強い密着力を得ること
ができる。
In addition, in the semiconductor device according to claim 4 of the present invention, the lead frame is provided with a reflection cup, a plurality of light emitting chips having different emission colors are arranged in the reflection cup, and the inner surface of the reflection cup is formed. Since a minute object projects from the surface, the light emitted from a plurality of light emitting chips is repeatedly reflected by the minute object projecting on the surface of the lead frame in the reflection cup, and diffuses the light reflection in the reflection cup. As a result, it is possible to improve the color mixing property when a plurality of light emitting chips emit light simultaneously. In addition, the semiconductor device according to claim 5 of the present invention is configured such that a part of the lead frame is sealed with a sealing resin having the same composition as the minute object. A strong adhesion can be obtained even in the interval.

【0021】加えて、本発明の請求項6記載の半導体装
置は、上記リードフレームの封止樹脂より突出する部分
表面に露出する微小物体を除去してなる構成なので、そ
の表面が梨地状で表面積が広くなり、実装部品として必
要な良好な半田付け性を得ることができる。
In addition, the semiconductor device according to claim 6 of the present invention has a structure in which minute objects exposed on the surface of the portion of the lead frame protruding from the sealing resin are removed. Can be widened, and good solderability required for mounting parts can be obtained.

【0022】[0022]

【実施例】図1は本発明の第一実施例よりなるリードフ
レームおよびこれを用いた半導体装置を示す断面図であ
る。
1 is a sectional view showing a lead frame according to a first embodiment of the present invention and a semiconductor device using the same.

【0023】本実施例のリードフレーム11は、表面に
半導体ベアチップ12が銀ペースト13を介して搭載さ
れるものであって、具体的に説明すると鉄,銅合金,鉄
ニッケル合金等のリードフレーム素材14を前記銀ペー
スト13と同一組成からなる微小エポキシボール15を
含有する一次メッキ層16にて被覆し、該一次メッキ層
16が二次メッキ層17にて被覆され、前記一次メッキ
層16に含有された微小エポキシボール15が前記二次
メッキ層17表面より突出してなるものである。
In the lead frame 11 of this embodiment, a semiconductor bare chip 12 is mounted on the surface via a silver paste 13. Specifically, a lead frame material such as iron, copper alloy, iron nickel alloy, etc. will be described. 14 is coated with a primary plating layer 16 containing fine epoxy balls 15 having the same composition as the silver paste 13, and the primary plating layer 16 is coated with a secondary plating layer 17 and contained in the primary plating layer 16. The minute epoxy balls 15 thus formed protrude from the surface of the secondary plating layer 17.

【0024】該リードフレーム11の製造工程を図2に
従って説明する。
The manufacturing process of the lead frame 11 will be described with reference to FIG.

【0025】まず、図2(a)に示すようなリードフレ
ーム素材14に、図2(b),(b′)に示すように、
銅メッキ液或はニッケルメッキ液の中に大きさがφ0.
3μm〜φ10μmからなる微少エポキシボール15を
分散させて激しく撹拌しながら電気メッキを行うことで
リードフレーム素材14上に微少エポキシボール15が
共析した一次メッキ層16を形成する。なお、図2
(b′)は同図(b)のA部拡大図である。
First, a lead frame material 14 as shown in FIG. 2 (a) is formed on the lead frame material 14 as shown in FIGS. 2 (b) and 2 (b ').
The size is φ0 in copper plating solution or nickel plating solution.
The minute epoxy balls 15 of 3 μm to φ10 μm are dispersed and electroplated with vigorous stirring to form the primary plating layer 16 on the lead frame material 14 in which the minute epoxy balls 15 are co-deposited. Note that FIG.
(B ') is an enlarged view of a portion A of FIG.

【0026】上記銅メッキ液及びニッケルメッキ液の代
表的なメッキ組成を図3に示す。これらのメッキ液から
なる一次メッキ層16は内部応力が高いことから前もっ
て下地に分散剤を含まない通常のメッキを施しておく場
合もある。また、リードフレーム素材14との密着力を
向上させるためにストライク銅メッキ或はストライクニ
ッケルメッキ(活性力を高めるための還元力の高いメッ
キ)を行う場合もある。
Typical plating compositions of the above copper plating solution and nickel plating solution are shown in FIG. Since the primary plating layer 16 made of these plating solutions has a high internal stress, there is a case in which a normal plating containing no dispersant is applied to the base in advance. In addition, strike copper plating or strike nickel plating (plating with high reducing power to enhance activity) may be performed in order to improve the adhesion with the lead frame material 14.

【0027】次に、図2(c),(c′)に示すよう
に、さらにその上に銀,金,パラジュウム等の貴金属を
前記微少エポキシボール15が完全に隠れない程度の厚
みでメッキを施し、二次メッキ層17を形成する。な
お、図2(c′)は同図(c)のB部拡大図である。
Next, as shown in FIGS. 2 (c) and 2 (c '), a noble metal such as silver, gold or palladium is further plated thereon with a thickness such that the minute epoxy balls 15 are not completely hidden. Then, the secondary plating layer 17 is formed. Incidentally, FIG. 2 (c ') is an enlarged view of portion B of FIG. 2 (c).

【0028】これによって、表面に微少エポキシボール
15が突出したリードフレーム11が得られる。
As a result, the lead frame 11 having the minute epoxy balls 15 protruding on the surface is obtained.

【0029】また、前記一次メッキ層16の形成後に、
図4に示すように、所定部分の微少エポキシボール15
の組成を溶剤によって溶解することによって、その表面
状態が梨地状で表面積を広く形成することができる。具
体的には、図4(a)に示すように一次メッキ層16を
形成した後、微少エポキシボール15を溶解する部分に
ついて図4(b)に示すようにエポキシボール溶解液に
浸し微少エポキシボール15を溶解する。これにより、
図4(c)に示すような構造となり、最後に図4(d)
に示すように二次メッキ層17を施してなる。
After the formation of the primary plating layer 16,
As shown in FIG. 4, a minute epoxy ball 15 in a predetermined portion
By dissolving the composition of (1) in a solvent, the surface state of the composition can be satin and a large surface area can be formed. Specifically, after the primary plating layer 16 is formed as shown in FIG. 4A, the portion in which the minute epoxy balls 15 are dissolved is dipped in an epoxy ball solution as shown in FIG. Dissolve 15. This allows
The structure shown in FIG. 4C is obtained, and finally, the structure shown in FIG.
The secondary plating layer 17 is applied as shown in FIG.

【0030】本実施例よりなるリードフレーム11は、
その半導体ベアチップ12搭載部分及びワイヤー18に
よるワイヤーボンディング部分において微少エポキシボ
ール15を除去しており、これによってその表面形状に
よりワイヤーボンディングのボンディング性を高め、更
に銀ペースト13とリードフレーム11との密着力をリ
ードフレーム11の表面積が大きくなった分だけ向上す
ることができる。
The lead frame 11 according to this embodiment is
The minute epoxy balls 15 are removed at the portion where the semiconductor bare chip 12 is mounted and the portion where the wires 18 are wire-bonded. This improves the bondability of wire bonding due to the surface shape thereof, and further the adhesive force between the silver paste 13 and the lead frame 11. Can be improved by the increase in the surface area of the lead frame 11.

【0031】また、本実施例においては、半導体ベアチ
ップ12搭載部分の微少エポキシボール15を除去した
が、除去しない構造であっても、銀ペースト13と微少
エポキシボール15とが同一組成からなることから強い
密着力を得ることができる。
Further, in this embodiment, the minute epoxy balls 15 on the portion where the semiconductor bare chip 12 is mounted are removed, but even if the structure is not removed, the silver paste 13 and the minute epoxy balls 15 have the same composition. A strong adhesion can be obtained.

【0032】さらに、リードフレーム表面が銀,金、パ
ラジューム等よりなる貴金属の二次メッキ層17からな
るので、従来同様、ダイボンド,ワイヤーボンドが良好
なボンディング性を得ることができる。しかも、リード
フレーム表面の数パーセント〜数十パーセントが微少エ
ポキシボール15で覆われていることから、従来よりも
貴金属のメッキ量を低減することができ、コスト低減を
図ることができる。
Further, since the surface of the lead frame is made of the noble metal secondary plating layer 17 made of silver, gold, palladium, etc., good bondability can be obtained by die bonding and wire bonding as in the conventional case. Moreover, since a few percent to several tens percent of the surface of the lead frame is covered with the minute epoxy balls 15, the plating amount of the noble metal can be reduced more than before, and the cost can be reduced.

【0033】上記リードフレーム11を半導体装置に用
いる、即ち、半導体ベアチップ12及び該半導体ベアチ
ップ12を搭載したリードフレーム11の一部を封止用
エポキシ樹脂19にて封止することにより、リードフレ
ーム11表面に突出した微少エポキシボール15と封止
用エポキシ樹脂19とが同一組成からなり、両者の間で
強い密着力を得ることができる。したがって、リードフ
レーム11と封止用エポキシ樹脂19との間より水分が
侵入することを防止でき、半導体装置として信頼性の向
上が図れる。
By using the lead frame 11 in a semiconductor device, that is, by sealing the semiconductor bare chip 12 and a part of the lead frame 11 on which the semiconductor bare chip 12 is mounted with a sealing epoxy resin 19, the lead frame 11 is formed. The minute epoxy balls 15 protruding on the surface and the sealing epoxy resin 19 have the same composition, and a strong adhesion can be obtained between them. Therefore, moisture can be prevented from entering between the lead frame 11 and the epoxy resin 19 for sealing, and the reliability of the semiconductor device can be improved.

【0034】また、前記リードフレーム11の封止用エ
ポキシ樹脂19より突出する部分表面に突出する微少エ
ポキシボール15を除去することにより、その表面が梨
地状で表面積が広くなり、表面実装部品として必要な良
好な半田付け性を備えた半導体装置を得ることができ
る。さらに、腐食電流の集中を防ぐことができ、錆びに
くくなり、屋外等の環境の悪いところでの使用される半
導体装置において好耐食性を持たせることができる。
By removing the minute epoxy balls 15 protruding from the surface of the lead frame 11 protruding from the encapsulating epoxy resin 19, the surface becomes matte and has a large surface area, which is necessary as a surface mount component. A semiconductor device having excellent solderability can be obtained. Further, the concentration of corrosion current can be prevented, rust is less likely to occur, and good corrosion resistance can be provided in a semiconductor device used in a bad environment such as outdoors.

【0035】図5(a)は、本発明の第二実施例よりな
るリードフレームおよびこれを用いた半導体装置を示す
断面図である。本実施例について、上記実施例と相違す
る点のみ説明する。
FIG. 5A is a sectional view showing a lead frame according to the second embodiment of the present invention and a semiconductor device using the same. Only the points of this embodiment different from the above embodiments will be described.

【0036】本実施例のリードフレーム21は、チップ
搭載用リード22と結線用リード23とからなり、前記
チップ搭載用リード22の一端側に発光色の異なる複数
個の発光ダイオードチップ24が搭載される反射カップ
22aを備えてなり、該リードフレーム21は、上記実
施例同様、リードフレーム素材を微小エポキシボール2
5を含有する一次メッキ層にて被覆し、該一次メッキ層
が二次メッキ層にて被覆され、前記一次メッキ層に含有
された微小エポキシボール25を前記二次メッキ層表面
より突出してなるものである。
The lead frame 21 of this embodiment comprises a chip mounting lead 22 and a connection lead 23, and a plurality of light emitting diode chips 24 of different emission colors are mounted on one end side of the chip mounting lead 22. The lead frame 21 is made of the same material as that of the above-described embodiment.
A primary plating layer containing 5 is coated with the primary plating layer with a secondary plating layer, and the minute epoxy balls 25 contained in the primary plating layer are projected from the surface of the secondary plating layer. Is.

【0037】前記発光ダイオードチップ24としては、
例えばレッド,グリーン,ブルーの3色の発光ダイオー
ドチップを用い、これによってフルカラー表現が可能と
なる。なお、図5においては、2つの発光ダイオードチ
ップをR,Yにて示している。
As the light emitting diode chip 24,
For example, a light emitting diode chip of three colors of red, green and blue is used, which enables full color expression. In FIG. 5, two light emitting diode chips are shown by R and Y.

【0038】これにより、従来のリードフレーム21′
を用いた半導体装置では、図5(b)に示すように、発
光ダイオードチップ24′から出た光束が反射カップ2
2a′内面で鏡面反射をしていたのに対し、本実施例の
上記リードフレーム21を用いた半導体装置では、図5
(a)に示すように、発光ダイオードチップ24から出
た光束は反射カップ22a内面に突出する微少エポキシ
ボール25で乱反射し、反射カップ22a内部で発光色
の異なる複数個の発光ダイオードチップ24が同時発光
した際に複数の発光色の色混合性を向上することができ
る。
As a result, the conventional lead frame 21 '
In the semiconductor device using, the light flux emitted from the light emitting diode chip 24 'is reflected by the reflection cup 2 as shown in FIG.
In contrast to the specular reflection at the inner surface of 2a ', the semiconductor device using the lead frame 21 of the present embodiment has the structure shown in FIG.
As shown in (a), the luminous flux emitted from the light emitting diode chip 24 is diffusely reflected by the minute epoxy balls 25 protruding on the inner surface of the reflection cup 22a, and a plurality of light emitting diode chips 24 having different emission colors are simultaneously generated inside the reflection cup 22a. It is possible to improve the color mixing property of a plurality of emission colors when emitting light.

【0039】[0039]

【発明の効果】以上説明したように、本発明の請求項1
記載のリードフレームによれば、その表面に露出する微
小物体と該表面に塗布される接着剤とが強い密着力で結
び付き、半導体チップが強固に固定することが可能なリ
ードフレームを提供することができる。
As described above, according to the first aspect of the present invention.
According to the described lead frame, a minute object exposed on the surface and an adhesive applied to the surface are bound by a strong adhesive force, and a lead frame capable of firmly fixing a semiconductor chip can be provided. it can.

【0040】また、本発明の請求項2記載のリードフレ
ームは、微少物体が露出する部分以外が貴金属よりなる
二次メッキ層にて被覆されてなる構成なので、二次メッ
キ層表面、即ちリードフレーム表面のボンディング性を
向上することができる。
The lead frame according to the second aspect of the present invention has a structure in which the secondary plating layer made of a noble metal is coated except for the portion where the minute object is exposed. Therefore, the surface of the secondary plating layer, that is, the lead frame. The surface bondability can be improved.

【0041】さらに、本発明の請求項3記載のリードフ
レームは、半導体チップの搭載部表面及び又はワイヤー
ボンド部表面に露出する微小物体を除去してなる構成な
ので、その表面が梨地状で表面積が広くなり、接着剤と
リードフレームとの密着性を向上することができ、また
ワイヤーボンドのボンディング性を向上することができ
る。
Further, since the lead frame according to claim 3 of the present invention has a structure in which minute objects exposed on the surface of the mounting portion of the semiconductor chip and / or the surface of the wire bond portion are removed, the surface is satin-like and has a surface area. It becomes wider, the adhesiveness between the adhesive and the lead frame can be improved, and the bondability of the wire bond can be improved.

【0042】加えて、本発明の請求項4記載の半導体装
置は、上記リードフレームに反射カップを備え、該反射
カップ内に発光色の異なる複数個の発光チップが配置さ
れ、前記反射カップ内面の微少物体がその表面より突出
してなる構成なので、複数個の発光チップより出射され
る光はそれぞれ反射カップ内で突出する微少物体によっ
て光反射を拡散することになり、複数個の発光チップの
同時発光時の色混合性が向上された半導体装置を提供す
ることができる。 加えて、本発明の請求項5記載の半導体装置は、上記リ
ードフレームの一部分が上記微小物体と同一組成からな
る封止樹脂にて封止されてなる構成なので、リードフレ
ームと封止樹脂とが強い密着力で結び付き、リードフレ
ームと封止樹脂との間より水分が侵入することを防止で
き、半導体装置の信頼性の向上が図れる。
In addition, in the semiconductor device according to the fourth aspect of the present invention, the lead frame is provided with a reflection cup, a plurality of light emitting chips having different emission colors are arranged in the reflection cup, and the inner surface of the reflection cup is formed. Since the minute objects project from the surface, the light emitted from a plurality of light emitting chips diffuses the light reflection by the protruding minute objects in the reflection cups, respectively, and the light emission of a plurality of light emitting chips occurs simultaneously. It is possible to provide a semiconductor device with improved color mixing properties. In addition, in the semiconductor device according to claim 5 of the present invention, a part of the lead frame is sealed with a sealing resin having the same composition as the minute object, so that the lead frame and the sealing resin are separated from each other. Bonding with a strong adhesive force can prevent moisture from entering between the lead frame and the sealing resin, and the reliability of the semiconductor device can be improved.

【0043】加えて、本発明の請求項6記載の半導体装
置は、上記リードフレームの封止樹脂より突出する部分
表面に露出する微小物体を除去してなる構成なので、そ
の表面が梨地状で表面積が広くなり、実装部品として必
要な良好な半田付け性を備えた半導体装置が得られる。
In addition, the semiconductor device according to claim 6 of the present invention has a structure in which minute objects exposed on the surface of the portion of the lead frame protruding from the sealing resin are removed, so that the surface is matte and has a surface area. Thus, a semiconductor device having good solderability required as a mounting component can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一実施例よりなるリードフレームお
よびこれを用いた半導体装置を示す断面図である。
FIG. 1 is a sectional view showing a lead frame according to a first embodiment of the present invention and a semiconductor device using the same.

【図2】図1に示すリードフレームの製造工程図であ
る。
FIG. 2 is a manufacturing process diagram of the lead frame shown in FIG.

【図3】銅メッキ液及びニッケルメッキ液の代表的なメ
ッキ組成を示す図である。
FIG. 3 is a diagram showing typical plating compositions of a copper plating solution and a nickel plating solution.

【図4】図1に示すリードフレームの製造工程図であ
る。
FIG. 4 is a manufacturing process diagram of the lead frame shown in FIG. 1;

【図5】(a)は本発明の第二実施例よりなるリードフ
レームおよびこれを用いた半導体装置を示す断面図であ
り、(b)は該実施例に対応する従来例を示す断面図で
ある。
5A is a sectional view showing a lead frame according to a second embodiment of the present invention and a semiconductor device using the same, and FIG. 5B is a sectional view showing a conventional example corresponding to the embodiment. is there.

【図6】従来のリードフレームを示す外観図である。FIG. 6 is an external view showing a conventional lead frame.

【図7】図6に示すリードフレームの製造工程図であ
る。
FIG. 7 is a manufacturing process diagram of the lead frame shown in FIG. 6;

【符号の説明】[Explanation of symbols]

11,21 リードフレーム 12 半導体ベアチップ(半導体チップ) 13 銀ペースト(接着剤) 14 リードフレーム素材 15,25 微少エポキシボール 16 一次メッキ層 17 二次メッキ層 19 封止用エポキシ樹脂 22 チップ搭載用リード 22a 反射カップ 24 発光ダイオードチップ(半導体チップ) 11,21 Lead frame 12 Semiconductor bare chip (semiconductor chip) 13 Silver paste (adhesive) 14 Lead frame material 15,25 Micro epoxy ball 16 Primary plating layer 17 Secondary plating layer 19 Encapsulating epoxy resin 22 Chip mounting lead 22a Reflection cup 24 Light emitting diode chip (semiconductor chip)

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 リードフレーム素材と、該リードフレー
ム素材を被覆するメッキ層とを備え、該メッキ層表面に
半導体チップが接着剤を介して搭載されるリードフレー
ムにおいて、 前記メッキ層は前記接着剤と同一組成からなる微小物体
を含有してなり、該微少物体がメッキ層表面より露出し
てなることを特徴とするリードフレーム。
1. A lead frame comprising a lead frame material and a plating layer covering the lead frame material, wherein a semiconductor chip is mounted on the surface of the plating layer via an adhesive, wherein the plating layer is the adhesive. A lead frame comprising a minute object having the same composition as that of the above, wherein the minute object is exposed from the surface of the plating layer.
【請求項2】 前記メッキ層は、前記微少物体を含有し
リードフレーム素材を被覆する一次メッキ層と、貴金属
よりなり前記微少物体を外部に露出させた状態で前記一
次メッキ層を被覆する二次メッキ層とからなることを特
徴とする請求項1記載のリードフレーム。
2. The plating layer includes a primary plating layer that covers the lead frame material and contains the minute object, and a secondary layer that covers the primary plating layer with a noble metal exposed to the outside. The lead frame according to claim 1, comprising a plated layer.
【請求項3】 半導体チップの搭載部表面及び又はワイ
ヤーボンド部表面に露出する微小物体を除去してなるこ
とを特徴とする請求項1記載のリードフレーム。
3. The lead frame according to claim 1, wherein minute objects exposed on the surface of the mounting portion of the semiconductor chip and / or the surface of the wire bond portion are removed.
【請求項4】 上記リードフレームを備えてなる半導体
装置であって、前記リードフレームは反射カップを備
え、該反射カップ内に異なる発光色の複数個の発光チッ
プが配置され、前記反射カップ内面の微少物体がその表
面より突出してなることを特徴とする半導体装置。
4. A semiconductor device comprising the lead frame, wherein the lead frame comprises a reflection cup, and a plurality of light emitting chips of different emission colors are arranged in the reflection cup, A semiconductor device characterized in that a minute object is projected from its surface.
【請求項5】 上記リードフレームを備えてなる半導体
装置であって、前記リードフレームの一部分が前記微小
物体と同一組成からなる封止樹脂にて封止されてなるこ
とを特徴とする半導体装置。
5. A semiconductor device including the lead frame, wherein a part of the lead frame is sealed with a sealing resin having the same composition as the minute object.
【請求項6】 前記リードフレームの封止樹脂より突出
する部分表面に露出する微小物体を除去してなることを
特徴とする請求項5記載の半導体装置。
6. The semiconductor device according to claim 5, wherein a minute object exposed on a surface of a portion of the lead frame protruding from the sealing resin is removed.
JP07133826A 1995-05-31 1995-05-31 Lead frame and semiconductor device using the same Expired - Fee Related JP3127098B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07133826A JP3127098B2 (en) 1995-05-31 1995-05-31 Lead frame and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07133826A JP3127098B2 (en) 1995-05-31 1995-05-31 Lead frame and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JPH08330497A true JPH08330497A (en) 1996-12-13
JP3127098B2 JP3127098B2 (en) 2001-01-22

Family

ID=15113952

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Country Link
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US9318677B2 (en) 2009-03-10 2016-04-19 Lg Innotek Co., Ltd. Light emitting device package
JP2011205100A (en) * 2010-03-25 2011-10-13 Lg Innotek Co Ltd Light-emitting element package and illumination system equipped with the same
US8309983B2 (en) 2010-03-25 2012-11-13 Lg Innotek Co., Ltd. Light emitting device package and lighting system having the same
JP2014078605A (en) * 2012-10-10 2014-05-01 Furukawa Electric Co Ltd:The Lead frame for optical semiconductor device, manufacturing method of lead frame for optical semiconductor device and optical semiconductor device
KR20140063539A (en) * 2014-03-31 2014-05-27 서울반도체 주식회사 Light emitting diode package
CN111312881A (en) * 2020-02-27 2020-06-19 盐城东山精密制造有限公司 Integrally formed LED device and manufacturing method thereof

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