JP6899226B2 - Semiconductor device - Google Patents

Description

The present invention relates to a surface mount type semiconductor device in which terminals are composed of metal leads .

As disclosed in Patent Document 1, a surface mount type semiconductor device in which terminals are made of metal leads is known. The semiconductor device includes a first lead having a die bond pad (lead of reference numeral 5), a semiconductor element mounted on the die bond pad (semiconductor chip of reference numeral 13), and a second lead having a wire bond pad (lead of reference numeral 7). ) And a case made of synthetic resin (package of reference numeral 11). The first lead and the second lead are terminals of the semiconductor device. Further, the semiconductor element is configured to be housed in a recess formed in the case. Further, in the semiconductor device, a bonding wire for connecting the semiconductor element and the wire bond pad of the second lead is provided, and the recess of the case is filled with a translucent resin. Both the first lead and the second lead are formed by punching the same conductive base material (metal plate material). Both the first lead and the second lead portion exposed to the outside from the case are L-shaped bent (forming).

Here, when the first lead and the second lead are formed by punching, burrs are formed on the edge of the surface located on the side opposite to the surface of the conductive base material to which the punch is pressed. In addition, sagging is formed on the edge of the surface of the conductive base material to which the punch is pressed. When the semiconductor device is mounted on a circuit board, if burrs are formed on the edges of the mounting surfaces (the surfaces of the first lead and the second lead facing the circuit board) in the first lead and the second lead, the said. When the protruding height of the burr becomes high, the adhesion of solder is hindered. Therefore, there is a concern that the mountability of the semiconductor device on the circuit board may be reduced.

Therefore, in order to ensure the mountability of the semiconductor device, when the surface in which the sagging is formed on the edge of the first lead and the second lead is used as the mounting surface, the first lead and the second lead are configured on the edge. The semiconductor element is mounted on the surface of the die bond pad on which the sagging is formed. Since the periphery of the sagging is a curved surface portion, the area ratio of the flat portion is reduced due to the influence of the sagging on the surface of the die bond pad on which the semiconductor element is mounted. Therefore, there is a concern that the bondability of the semiconductor element to the first lead (die bond pad) may decrease.

Japanese Unexamined Patent Publication No. 2006-203052

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which both the mountability on a circuit board and the bondability of a semiconductor element with respect to leads are improved.

The semiconductor device provided by the first aspect of the present invention has a semiconductor element, a first mounting surface and a first mounting back surface facing opposite sides in the thickness direction of the semiconductor element, and the first mounting surface. It has a first terminal portion whose surface faces the circuit board, a mounting surface whose surface faces the same direction as the back surface of the first mounting, and on which the semiconductor element is mounted, and the first terminal in the thickness direction of the semiconductor element. It has a first pad portion arranged apart from the portion, and a first support portion that stands up from the first terminal portion in the thickness direction of the semiconductor element and supports the first pad portion. A first lead integrally molded, and burrs are formed on both the edge of the back surface of the first mounting of the first terminal portion and the edge of the mounting surface of the first pad portion. It is characterized by being.

In the practice of the present invention, preferably, the protruding height of the burr formed on the edge of the back surface of the first mounting of the first terminal portion is the protrusion of the burr formed on the edge of the mounting surface of the first pad portion. Lower than height.

In the practice of the present invention, it is preferable that the second terminal portion has a second mounting surface and a second mounting back surface facing opposite sides in the thickness direction of the semiconductor element, and the second mounting surface faces the circuit board. A second pad portion having a connection surface facing the same direction as the back surface of the second mounting and arranged apart from the second terminal portion in the thickness direction of the semiconductor element, and the second terminal portion. It has a second support portion that stands up in the thickness direction of the semiconductor element and supports the second pad portion, is arranged apart from the first lead in a plan view, and is integrally molded. A second lead is further provided, and burrs are formed on both the edge of the back surface of the second mounting of the second terminal portion and the edge of the connecting surface of the second pad portion.

In the practice of the present invention, preferably, the protruding height of the burr formed on the edge of the back surface of the second mounting of the second terminal portion is the protrusion of the burr formed on the edge of the connecting surface of the second pad portion. Lower than height.

In the practice of the present invention, the first support portion preferably has a first inner side surface connected to the first mounting back surface of the first terminal portion, and the second support portion is the second terminal portion of the second terminal portion. It has a second inner surface that connects to the back surface of the second mounting, and the first inner surface and the second inner surface face each other.

In the practice of the present invention, burrs are preferably formed on both the edge of the first inner side surface of the first support portion and the edge of the second inner side surface of the second support portion.

In the practice of the present invention, preferably, the first lead and the second lead are both composed of the same conductive substrate.

In the practice of the present invention, the conductive base material is preferably composed of an alloy containing Cu as a main component.

In the practice of the present invention, preferably, the semiconductor element has an element main surface facing the same direction as the mounting surface of the first pad portion, and the element main surface and the connecting surface of the second pad portion are connected to each other. Further provided with a bonding wire to be connected.

In the practice of the present invention, preferably, the semiconductor element has an element back surface facing the side opposite to the element main surface, and has conductivity interposed between the element back surface and the mounting surface of the first pad portion. A bonding layer having the above is further provided.

In the practice of the present invention, an interior plating layer is preferably formed to cover the mounting surface of the first pad portion and the connecting surface of the second pad portion.

In the practice of the present invention, the interior plating layer is preferably composed of Ag.

In the practice of the present invention, the semiconductor element is preferably a light emitting diode.

In the practice of the present invention, a case made of synthetic resin preferably has a top surface of the semiconductor element facing in the same direction as the element main surface, and has a recess formed from the top surface and a recess for accommodating the semiconductor element. Further prepare.

In the practice of the present invention, the recess is preferably a bottom surface arranged parallel to the top surface of the case, and an inner peripheral surface that connects the bottom surface and the top surface and surrounds the semiconductor element. , And the inner peripheral surface is inclined with respect to the bottom surface.

In the practice of the present invention, preferably, a part of each of the mounting surface of the first pad portion and the connecting surface of the second pad portion is exposed from the bottom surface of the case.

In the practice of the present invention, the recess is preferably filled with a translucent sealing resin.

In the practice of the present invention, the semiconductor element is preferably a diode.

In carrying out the present invention, it is preferable to further include a sealing resin that covers the semiconductor element, the first pad portion, and the second pad portion.

In the practice of the present invention, the first support portion preferably has a first outer surface connected to the first mounting surface of the first terminal portion, and the second support portion is the second terminal portion of the second terminal portion. It has a second outer surface connected to a second mounting surface, and both the first outer surface and the second outer surface are exposed to the outside.

In the practice of the present invention, the first mounting surface of the first terminal portion, the first outer surface of the first support portion, the second mounting surface of the second terminal portion, and the second support portion are preferable. An exterior plating layer is formed to cover the second outer surface of the above.

In the practice of the present invention, the exterior plating layer is preferably composed of Ag.

The method for manufacturing a semiconductor device provided by the second aspect of the present invention supports a first pad portion and the first pad portion on a conductive base material having a front surface and a back surface facing opposite sides in the thickness direction. A first conductive member having a first support portion to be formed, a second pad portion separated from the first conductive member and located in the vicinity of the first pad portion, and a second support portion for supporting the second pad portion. A step of forming the second conductive member having the above by punching, a step of mounting the semiconductor element on the surface of the first pad portion, and connecting the semiconductor element and the surface of the second pad portion. A method of manufacturing a semiconductor device including a step of forming a bonding wire to be formed, wherein a punch is pressed from the back surface of the conductive base material in the step of forming the first conductive member and the second conductive member. The first processing includes a second processing of pressing a punch from the surface of the conductive base material, and the first processing forms the first pad portion and the second pad portion, and the second processing The first support portion and the second support portion are formed by the above.

In the practice of the present invention, preferably, in the step of forming the first conductive member and the second conductive member, the second process is performed after the first process is performed.

In the practice of the present invention, preferably, in the second processing, the first support portion and the second support portion are held in a state where the formed first pad portion and the second pad portion are sandwiched between a die and a stripper. Form.

In the semiconductor device according to the present invention, burrs are formed on the edge of the back surface of the first mounting surface facing the side opposite to the first mounting surface of the first terminal portion of the first lead facing the circuit board. In this case, no burrs are formed on the edge of the first mounting surface. With such a configuration, when the semiconductor device is mounted on the circuit board, the adhesion of solder to the first mounting surface is not hindered by burrs, so that the mountability of the semiconductor device on the circuit board is improved. Further, burrs are formed on the edge of the mounting surface of the first pad portion of the first lead on which the semiconductor element is mounted. By adopting such a configuration, the area ratio of the flat surface portion on the mounting surface becomes large, and the bondability of the semiconductor element to the first lead is improved. Therefore, according to the semiconductor device according to the present invention, it is possible to improve both the mountability on the circuit board and the bondability of the semiconductor element with respect to the lead.

According to the method for manufacturing a semiconductor device according to the present invention, the first conductive member corresponding to the first lead is formed by punching including the first processing and the second processing. In the first processing, the first pad portion is formed by pressing the punch from the back surface of the conductive base material. In the second processing, the first terminal portion is formed by pressing a punch from the surface of the conductive base material. By adopting such a manufacturing method, burrs can be formed on both the edge of the back surface of the first mounting of the first terminal portion and the mounting surface of the first pad portion.

Other features and advantages of the present invention will become more apparent with the detailed description given below based on the accompanying drawings.

It is a perspective view (permeating the sealing resin) of the semiconductor device which concerns on 1st Embodiment of this invention. It is a top view (permeating the sealing resin) of the semiconductor device shown in FIG. It is a bottom view of the semiconductor device shown in FIG. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. FIG. 5 is an enlarged cross-sectional view of a first terminal portion (first lead) of the semiconductor device shown in FIG. FIG. 5 is an enlarged cross-sectional view of a first pad portion (first lead) of the semiconductor device shown in FIG. FIG. 5 is an enlarged cross-sectional view of a second terminal portion (second lead) of the semiconductor device shown in FIG. FIG. 5 is an enlarged cross-sectional view of a second pad portion (second lead) of the semiconductor device shown in FIG. It is a top view explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing corresponding to the manufacturing process shown in FIG. It is a top view explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing corresponding to the manufacturing process shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing process of the semiconductor device shown in FIG. It is a perspective view of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a top view of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view taken along the line XXII-XXII of FIG. FIG. 2 is a cross-sectional view taken along the line XXIII-XXIII of FIG.

An embodiment for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
The semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 9. The semiconductor device A10 includes a semiconductor element 11, a bonding layer 12, a first lead 2, a second lead 3, a bonding wire 4, and a case 5.

FIG. 1 is a perspective view of the semiconductor device A10. FIG. 2 is a plan view of the semiconductor device A10. 1 and 2 are transparent to the sealing resin 6 for convenience of understanding. FIG. 3 is a bottom view of the semiconductor device A10. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a partially enlarged view of the first terminal portion 21 (first reed 2) of the semiconductor device A10, which will be described later. FIG. 7 is a partially enlarged view of the first pad portion 22 (first reed 2) of the semiconductor device A10, which will be described later. FIG. 8 is a partially enlarged view of the second terminal portion 31 (second lead 3) of the semiconductor device A10, which will be described later. FIG. 9 is a partially enlarged view of the second pad portion 32 (second lead 3) of the semiconductor device A10, which will be described later. 6 to 9 are cross-sectional views taken along the second direction Y, which will be described later.

The semiconductor device A10 shown in these figures is a SOP (Small Outline Package) type LED package surface-mounted on a circuit board. As shown in FIGS. 1 and 2, the shape of the semiconductor element 11 of the semiconductor device A10 in the thickness direction Z view (hereinafter referred to as “plan view”) is rectangular. Here, for convenience of explanation, the long side direction of the semiconductor device A10, which is perpendicular to the thickness direction Z of the semiconductor element 11, is referred to as the first direction X. Further, the short side direction of the semiconductor device A10, which is perpendicular to both the thickness direction Z and the first direction X of the semiconductor element 11, is referred to as the second direction Y.

The semiconductor element 11 is a central part of the function of the semiconductor device A10. The semiconductor element 11 according to this embodiment is a light emitting diode (LED). The semiconductor element 11 is a light emitting element in which a plurality of semiconductor layers are laminated with each other by, for example, a pn junction. When a current flows through the semiconductor device A10, the semiconductor element 11 emits light. The semiconductor element 11 emits blue light, red light, green light, or the like, depending on the substances constituting the laminated semiconductor layer. As shown in FIGS. 4 and 5, the semiconductor element 11 has an element main surface 111 and an element back surface 112 facing opposite sides in the thickness direction Z. A light emitting layer (not shown) is formed between the element main surface 111 and the element back surface 112, and the semiconductor element 11 emits light from the light emitting layer. For example, when emitting blue light, the main material of the semiconductor element 11 is GaN (gallium nitride), and InGaN (indium gallium nitride) is used for the light emitting layer. Further, a part of the element main surface 111 is a p-side electrode (anode), and the bonding wire 4 is connected to the p-side electrode. The p-side electrode conducts to the second lead 3 via the bonding wire 4. Further, the element back surface 112 is an n-side electrode (cathode). The n-side electrode conducts to the first reed 2 via the bonding layer 12.

As shown in FIGS. 2, 4 and 5, the bonding layer 12 is a portion interposed between the element back surface 112 of the semiconductor element 11 and the mounting surface 221 of the first pad portion 22 of the first reed 2, which will be described later. Is. The bonding layer 12 is made of a conductive material such as a synthetic resin (so-called Ag paste) containing an epoxy resin containing Ag as a main component. By the bonding layer 12, the semiconductor element 11 is mounted on the mounting surface 221 of the first pad portion 22 of the first lead 2, which will be described later by die bonding.

As shown in FIGS. 1 to 5, the first reed 2 is a conductive member on which the semiconductor element 11 is mounted and which serves as a cathode terminal when the semiconductor device A10 is mounted. The first reed 2 is composed of a conductive base material 80, which will be described later. The conductive base material 80 according to the present embodiment is composed of an alloy containing Cu as a main component. The first reed 2 is an integrally molded conductive base material 80 having a thickness of 100 to 200 μm. The first reed 2 has a first terminal portion 21, a first pad portion 22, and a first support portion 23.

As shown in FIGS. 3 and 4, the first terminal portion 21 is a portion that is exposed to the outside of the semiconductor device A10 and has a rectangular shape in a plan view. When mounting the semiconductor device A10, the first terminal portion 21 serves as a cathode terminal. The first terminal portion 21 conducts the wiring pattern formed on the circuit board via solder. The first terminal portion 21 has a first mounting surface 211 and a first mounting back surface 212 facing opposite sides in the thickness direction Z of the semiconductor element 11. When the semiconductor device A10 is mounted, the first mounting surface 211 faces the circuit board. The first mounting back surface 212 is a surface facing the same direction as the element main surface 111 of the semiconductor element 11, and faces the case 5.

As shown in FIG. 6, a burr 291 having a protruding height of Δh21 is formed on the edge of the first mounting surface 211 of the first terminal portion 21. The protrusion height Δh21 is 5 to 10 μm. Further, a sagging 292 forming a smooth curved surface is formed on the edge of the first mounting back surface 212 of the first terminal portion 21.

As shown in FIGS. 2, 4 and 5, the first pad portion 22 is separated from the first terminal portion 21 in the thickness direction Z of the semiconductor element 11 and is arranged parallel to the first terminal portion 21. It is a part. A part of the first pad portion 22 is covered with the case 5. The first pad portion 22 has a mounting surface 221 and a back surface 222 of the first pad facing opposite sides in the thickness direction Z of the semiconductor element 11. The mounting surface 221 is a surface that faces the same direction as the element main surface 111 of the semiconductor element 11 and the first mounting back surface 212 of the first terminal portion 21, and is the surface on which the semiconductor element 11 is mounted. The back surface 222 of the first pad faces the same direction as the first mounting surface 211 of the first terminal portion 21, and the entire surface is in contact with the case 5.

As shown in FIGS. 4 and 5, in the present embodiment, the interior plating layer 28, which is a metal thin film layer covering the mounting surface 221 of the first pad portion 22, is formed. The interior plating layer 28 according to the present embodiment is composed of Ag. The interior plating layer 28 may be composed of a Ni layer and an Ag layer laminated on each other. In this case, the Ni layer comes into contact with the mounting surface 221.

As shown in FIG. 7, a burr 293 having a protruding height of Δh22 is formed on the edge of the mounting surface 221 of the first pad portion 22. In the present embodiment, the protrusion height Δh22 is set lower than the protrusion height Δh21 of the burr 291 formed on the first mounting back surface 212 of the first terminal portion 21. Further, a sagging 294 forming a smooth curved surface is formed on the edge of the back surface 222 of the first pad of the first pad portion 22.

As shown in FIGS. 2 to 4, the first support portion 23 is a portion that stands up from the first terminal portion 21 in the thickness direction Z of the semiconductor element 11 and supports the first pad portion 22. The first support portion 23 has a first outer surface 231 and a first inner surface 232. The first outer surface 231 is a surface that is connected to the first mounting surface 211 of the first terminal portion 21 and is exposed to the outside of the semiconductor device A10. The first inner side surface 232 is a surface connected to the first mounting back surface 212 of the first terminal portion 21 and facing the case 5.

A burr 291 similar to the edge of the first mounting back surface 212 of the first terminal portion 21 shown in FIG. 6 is formed on the edge of the first inner side surface 232 of the first support portion 23. Further, on the edge of the first outer surface 231 of the first support portion 23, a sagging 292 similar to the first mounting surface 211 of the first terminal portion 21 shown in FIG. 6 is formed.

As shown in FIGS. 1 to 5, the second reed 3 is a conductive member that is arranged apart from the first reed 2 in the first direction X in a plan view and serves as an anode terminal when the semiconductor device A10 is mounted. Is. The second lead 3 is composed of a conductive base material 80, which will be described later. Therefore, both the first reed 2 and the second reed 3 are composed of the same conductive base material 80. Therefore, the thickness of the second reed 3 is the same as the thickness of the first reed 2. Further, the second reed 3 is formed by integrally molding the conductive base material 80 in the same manner as the first reed 2. The second lead 3 has a second terminal portion 31, a second pad portion 32, and a second support portion 33.

As shown in FIGS. 3 and 4, the second terminal portion 31 is a portion that is exposed to the outside of the semiconductor device A10 and has a rectangular shape in a plan view. When mounting the semiconductor device A10, the second terminal portion 31 serves as an anode terminal. The second terminal portion 31 conducts the wiring pattern formed on the circuit board via the solder. The second terminal portion 31 has a second mounting surface 311 and a second mounting back surface 312 facing opposite sides in the thickness direction Z of the semiconductor element 11. When the semiconductor device A10 is mounted, the second mounting surface 311 faces the circuit board. The second mounting back surface 312 is a surface facing the same direction as the element main surface 111 of the semiconductor element 11, and faces the case 5.

As shown in FIG. 8, a burr 391 having a protruding height of Δh31 is formed on the edge of the second mounting surface 311 of the second terminal portion 31. The protrusion height Δh31 is 5 to 10 μm. Further, a sagging 392 forming a smooth curved surface is formed on the edge of the second mounting back surface 312 of the second terminal portion 31.

As shown in FIGS. 2, 4 and 5, the second pad portion 32 is separated from the second terminal portion 31 in the thickness direction Z of the semiconductor element 11 and is arranged parallel to the second terminal portion 31. It is a part. A part of the second pad portion 32 is covered with the case 5. In the present embodiment, the portion of the first pad portion 22 on which the semiconductor element 11 is mounted is sandwiched between the second pad portions 32 from both sides in the second direction Y. The second pad portion 32 has a connection surface 321 facing opposite to each other in the thickness direction Z of the semiconductor element 11 and a second pad back surface 322. The connection surface 321 is a surface that faces the same direction as the element main surface 111 of the semiconductor element 11 and the second mounting back surface 312 of the second terminal portion 31 and to which the bonding wire 4 is connected. The back surface 322 of the second pad faces the same direction as the second mounting surface 311 of the second terminal portion 31, and the entire surface is in contact with the case 5.

As shown in FIGS. 4 and 5, in the present embodiment, the interior plating layer 38, which is a metal thin film layer covering the connection surface 321 of the second pad portion 32, is formed. The interior plating layer 38 has the same structure as the interior plating layer 28 described above, and is composed of Ag in the present embodiment. The interior plating layer 38 may be composed of a Ni layer and an Ag layer laminated on each other. In this case, the Ni layer comes into contact with the connection surface 321.

As shown in FIG. 9, a burr 393 having a protruding height of Δh32 is formed on the edge of the connection surface 321 of the second pad portion 32. In the present embodiment, the protrusion height Δh32 is set lower than the protrusion height Δh31 of the burr 391 formed on the second mounting back surface 312 of the second terminal portion 31. Further, a sagging 394 forming a smooth curved surface is formed on the edge of the back surface 322 of the second pad of the second pad portion 32.

As shown in FIGS. 2 to 4, the second support portion 33 is a portion that stands up from the second terminal portion 31 in the thickness direction Z of the semiconductor element 11 and supports the second pad portion 32. The second support portion 33 has a second outer surface 331 and a second inner surface 332. The second outer surface 331 is a surface that is connected to the second mounting surface 311 of the second terminal portion 31 and is exposed to the outside of the semiconductor device A10. The second inner side surface 332 is a surface connected to the second mounting back surface 312 of the second terminal portion 31 and facing the case 5. In the present embodiment, the second inner side surface 332 and the first inner side surface 232 of the first support portion 23 face each other.

A burr 391 similar to the edge of the second mounting back surface 312 of the second terminal portion 31 shown in FIG. 8 is formed on the edge of the second inner side surface 332 of the second support portion 33. Further, on the edge of the second outer surface 331 of the second support portion 33, a sagging 392 similar to the second mounting surface 311 of the second terminal portion 31 shown in FIG. 8 is formed.

As shown in FIGS. 1, 2 and 4, the bonding wire 4 has a connection surface 321 (second lead 3) between the p-side electrode, which is a part of the element main surface 111 of the semiconductor element 11, and the second pad portion 32. ) Is a metal wiring that connects to. The bonding wire 4 is composed of, for example, Au.

As shown in FIGS. 1 to 5, the case 5 is a member that houses the semiconductor element 11 and the bonding wire 4. The case 5 is made of a white synthetic resin, and is made of a synthetic resin having high mechanical strength and excellent heat resistance, such as bismaleimide triazine resin (BT resin), polyphthalamide (PPA), or polycarbonate. To. The case 5 has a top surface 51. Further, the case 5 is formed with a recess 52.

As shown in FIGS. 2, 4 and 5, the top surface 51 is a flat surface facing the same direction as the element main surface 111 of the semiconductor element 11. Further, as shown in FIGS. 2, 4 and 5, the recess 52 is a hollow region recessed from the top surface 51 and accommodating the semiconductor element 11 and the bonding wire 4. The recess 52 has a bottom surface 521 and an inner peripheral surface 522. The recess 52 has a bottom surface 521 and an inner peripheral surface 522. As shown in FIGS. 4 and 5, the bottom surface 521 is a surface that is arranged parallel to the top surface 51 and has a circular outer edge. From the bottom surface 521, a part of each of the mounting surface 221 of the first pad portion 22 and the connecting surface 321 of the second pad portion 32 is exposed. As shown in FIGS. 2, 4 and 5, the inner peripheral surface 522 is a surface that connects the outer edge of the bottom surface 521 and the inner edge of the top surface 51 and surrounds the semiconductor element 11. The inner peripheral surface 522 is inclined with respect to the bottom surface 521. Therefore, the shape of the recess 52 is a truncated cone shape.

As shown in FIGS. 4 and 5, the sealing resin 6 is a member that fills the recess 52 of the case 5 and covers the semiconductor element 11. The sealing resin 6 is a translucent synthetic resin, for example, a silicone resin. The sealing resin 6 may contain a phosphor (not shown). For example, when the semiconductor element 11 emits blue light, white light is emitted from the semiconductor device A10 by including the yellow phosphor in the sealing resin 6. Further, when the semiconductor element 11 emits purple near-ultraviolet rays, white light having high color rendering properties is emitted from the semiconductor device A10 by incorporating the phosphors having three colors of red, blue and green in the sealing resin 6. To.

As shown in FIGS. 4 and 5, the exterior plating layer 7 has a first mounting surface 211 of the first terminal portion 21, a first outer surface 231 of the first support portion 23, and a second mounting of the second terminal portion 31. It is a metal thin film layer that covers the surface 311 and the second outer surface 331 of the second support portion 33. The exterior plating layer 7 is composed of Ag. The exterior plating layer 7 may be laminated with an Ag layer and a Pd layer covering the Ag layer. In the present embodiment, the exterior plating layer 7 further includes the first mounting back surface 212 of the first terminal portion 21, the first inner side surface 232 of the first support portion 23, and the second mounting back surface 312 of the second terminal portion 31. And the second inner side surface 332 of the second support portion 33 are covered.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 10 to 19.

10 and 12 are plan views illustrating a manufacturing process of the semiconductor device A10. FIG. 11 is a cross-sectional view (the cross-sectional position is the XI-XI line of FIG. 10) corresponding to the manufacturing process shown in FIG. FIG. 13 is a cross-sectional view (the cross-sectional position is the line XIII-XIII of FIG. 12) corresponding to the manufacturing process shown in FIG. 14 to 19 are cross-sectional views for explaining the manufacturing process of the semiconductor device A10, and the cross-sectional positions of these cross-sectional views correspond to the cross-sectional positions of FIG. 4 showing the semiconductor device A10. The thickness directions Z, the first direction X, and the second direction Y of the conductive base material 80, which will be described later, shown in FIGS. 10 to 19 are the thickness directions Z of the semiconductor element 11 shown in FIGS. 1 to 9. , 1st direction X and 2nd direction Y.

First, as shown in FIGS. 10 to 13, both the first conductive member 81 and the second conductive member 82 are formed on the conductive base material 80 by punching. The first conductive member 81 corresponds to the first lead 2 of the semiconductor device A10, and the second conductive member 82 corresponds to the second lead 3 of the semiconductor device A10. The conductive substrate 80 has a front surface 801 and a back surface 802 facing opposite sides in the thickness direction Z. The conductive base material 80 according to the present embodiment is composed of an alloy containing Cu as a main component. The thickness of the conductive base material 80 is 100 to 200 μm.

As shown in FIG. 12, the first conductive member 81 has a first pad portion 811 and a first support portion 812. The first pad portion 811 is a portion on which the semiconductor element 841 described later is mounted and corresponds to the first pad portion 22 of the semiconductor device A10. The first support portion 812 is a portion that supports the first pad portion 811 and corresponds to the first terminal portion 21 and the first support portion 23 of the semiconductor device A10. Further, as shown in FIG. 12, the second conductive member 82 is separated from the first conductive member 81 in the first direction X, and has a second pad portion 821 and a second support portion 822. The second pad portion 821 is a portion to which the bonding wire 85 described later is connected and corresponds to the second pad portion 32 of the semiconductor device A10. The second pad portion 821 is located in the vicinity of the first pad portion 811. The second support portion 822 is a portion that supports the second pad portion 821 and corresponds to the second terminal portion 31 and the second support portion 33 of the semiconductor device A10.

The step of forming the first conductive member 81 and the second conductive member 82 includes the first processing B1 and the second processing B2. The first processing B1 is a punching processing in which the punch 881 is pressed from the back surface 802 of the conductive base material 80. Further, the second processing B2 is a punching processing in which the punch 881 is pressed against the surface 801 of the conductive base material 80. In the present embodiment, the second processing B2 is performed after the first processing B1 is performed. The first conductive member 81 and the second conductive member 82 are formed by the following procedure.

First, as shown in FIGS. 10 and 11, the first processing B1 is performed on the conductive base material 80. The conductive base material 80 is arranged on the die 882 so that the back surface 802 faces upward. In the present embodiment, the first pad portion 811 and the second pad portion 821 are formed by the first processing B1. At this time, a burr 293 is formed on the edge of the surface 801 of the first pad portion 811 and a burr 393 is formed on the edge of the surface 801 of the second pad portion 821.

Next, as shown in FIGS. 12 and 13, the second processing B2 is performed on the conductive base material 80. The conductive base material 80 is arranged on the die 882 so that the surface 801 faces upward, unlike the case of the first processing B1. In the present embodiment, the first support portion 812 and the second support portion 822 are formed by the second processing B2. Further, in the present embodiment, the first pad portion 811 and the second pad portion 821 are sandwiched between the die 882 and the stripper 883, and then the first support portion 812 and the second support portion 822 are held by the second processing B2. Form. At this time, a burr 291 is formed on the edge of the back surface 802 of the first support portion 812, and a burr 391 is formed on the edge of the back surface 802 of the second support portion 822. The first conductive member 81 and the second conductive member 82 are formed by the above procedure.

Next, as shown in FIG. 14, an interior plating layer 811a covering the surface 801 of the first pad portion 811 and an interior plating layer 821a covering the surface 801 of the second pad portion 821 are formed. The interior plating layer 811a corresponds to the interior plating layer 28 of the semiconductor device A10, and the interior plating layer 821a corresponds to the interior plating layer 38 of the semiconductor device A10. Both the interior plating layer 821a and the interior plating layer 821a are formed by electrolytic plating using the conductive base material 80 as a conductive path. The interior plating layer 811a and the interior plating layer 821a according to the present embodiment are composed of Ag.

Next, as shown in FIG. 15, a case 83 is formed which covers a part of each of the first pad portion 811 and the second pad portion 821. The case 83 is composed of a white synthetic resin, and the synthetic resin is, for example, a bismaleimide triazine resin or a polyphthalamide. The case 83 is formed by thermosetting the synthetic resin by, for example, transfer molding. At this time, the case 83 is formed with a recess 831 which is a hollow region having a truncated cone shape. A part of the surface 801 of the conductive base material 80 is exposed from the inside of the recess 831.

Next, as shown in FIG. 16, the semiconductor element 841 is mounted on the surface 801 of the first pad portion 811 by die bonding. The semiconductor element 841 corresponds to the semiconductor element 11 of the semiconductor device A10. When mounting the semiconductor element 841, first, the bonding material 842 is applied to the interior plating layer 811a that covers the surface 801 of the first pad portion 811. The bonding material 842 according to the present embodiment is, for example, a synthetic resin (so-called Ag paste) containing an epoxy resin containing Ag as a main component. Next, for example, the semiconductor element 841 adsorbed by the collet is transferred to the first pad portion 811 and adhered to the bonding material 842. Finally, the bonding material 842 is thermoset in a curing furnace or the like. The thermosetting bonding material 842 corresponds to the bonding layer 12 of the semiconductor device A10.

Next, as shown in FIG. 17, a bonding wire 85 connecting the semiconductor element 841 and the surface 801 of the second pad portion 821 is formed by wire bonding. The bonding wire 85 corresponds to the bonding wire 4 of the semiconductor device A10. The bonding wire 85 according to this embodiment is composed of, for example, Au.

Next, as shown in FIG. 18, the recess 831 of the case 83 is filled with the sealing resin 86 by potting. The sealing resin 86 corresponds to the sealing resin 6 of the semiconductor device A10. The sealing resin 6 according to this embodiment is, for example, a silicone resin containing a phosphor (not shown). At this time, the semiconductor element 841 and the bonding wire 85 are covered with the sealing resin 86.

Finally, as shown in FIG. 19, the conductive base material 80 is divided into individual pieces, and the first support portion 812 and the second support portion 822 are bent (formed). Here, before the conductive base material 80 is divided into individual pieces, the exterior plating layer 87 that covers the first support portion 812 and the second support portion 822 exposed from the case 83 is formed. The exterior plating layer 87 corresponds to the exterior plating layer 7 of the semiconductor device A10. The exterior plating layer 87 is formed by electrolytic plating using the conductive base material 80 as a conductive path. The exterior plating layer 87 according to the present embodiment is composed of Ag. After forming the exterior plating layer 87, the conductive base material 80 is divided into individual pieces by dicing, and both the first support portion 812 and the second support portion 822 are subjected to an L-shaped bending process. At this time, the back surface 802 of the first support portion 812 and the back surface 802 of the second support portion 822 both face the case 83. The individual piece in this state becomes the semiconductor device A10. By going through the above steps, the semiconductor device A10 is manufactured.

Next, the action and effect of the semiconductor device A10 will be described.

The semiconductor device A10 has a first terminal portion 21 and a first pad portion 22, and includes a first lead 2 integrally molded. A burr 291 is formed on the edge of the first mounting back surface 212 facing the side opposite to the first mounting surface 211 of the first terminal portion 21 facing the circuit board. In this case, the burr 291 is not formed on the edge of the first mounting surface 211 (the sagging 292 is formed). With such a configuration, when the semiconductor device A10 is mounted on the circuit board, the entire first mounting surface 211 becomes a smooth surface, and the adhesion of solder to the first mounting surface 211 is not hindered by the burr 291. The mountability of the semiconductor device A10 on the circuit board is improved. Further, a burr 293 is formed on the edge of the mounting surface 221 of the first pad portion 22 of the first lead 2 on which the semiconductor element 11 is mounted. By adopting such a configuration, the area ratio of the flat surface portion on the mounting surface 221 is increased, and the bondability of the semiconductor element 11 to the first reed 2 (first pad portion 22) is improved. Therefore, according to the semiconductor device A10, it is possible to improve both the mountability on the circuit board and the bondability of the semiconductor element with respect to the leads.

Further, the semiconductor device A10 has a second terminal portion 31 and a second pad portion 32, is integrally molded, and includes a second lead 3 arranged apart from the first lead 2 in a plan view. A burr 391 is formed on the edge of the second mounting back surface 312 facing the side opposite to the second mounting surface 311 of the second terminal portion 31 facing the circuit board. In this case, the burr 391 is not formed on the edge of the second mounting surface 311 (the sagging 392 is formed). With such a configuration, when the semiconductor device A10 is mounted on the circuit board, the entire second mounting surface 311 becomes a smooth surface, and the adhesion of solder to the second mounting surface 311 is not hindered by the burr 291. The mountability of the semiconductor device A10 on the circuit board is further improved.

Here, according to the manufacturing method of the semiconductor device A10, the first conductive member 81 corresponding to the first lead 2 and the second conductive member 82 corresponding to the second lead 3 are both the first processed B1 and the second. It is formed by punching including processing B2. In the first processing B1, the first pad portion 22 and the second pad portion 32 are formed by pressing the punch 881 from the back surface 802 of the conductive base material 80. In the second processing B2, by pressing the punch 881 from the surface 801 of the conductive base material 80, the first support portion 812 including the first terminal portion 21 and the second support portion 822 including the second terminal portion 31 Is formed. By adopting such a manufacturing method, burrs 291 can be formed on the edge of the first mounting back surface 212 of the first terminal portion 21, and burrs 293 can be formed on the edge of the mounting surface 221 of the first pad portion 22. .. At the same time, a burr 391 can be formed on the edge of the second mounting back surface 312 of the second terminal portion 31, and a burr 393 can be formed on the edge of the connection surface 321 of the second pad portion 32.

In the first reed 2, the protruding height Δh22 of the burr 293 formed on the edge of the mounting surface 221 of the first pad portion 22 is the burr 291 formed on the edge of the first mounting back surface 212 of the first terminal portion 21. It is lower than the protrusion height Δh21. Further, in the second lead 3, the protruding height Δh32 of the burr 393 formed on the edge of the connection surface 321 of the second pad portion 32 is the burr formed on the edge of the second mounting back surface 312 of the second terminal portion 31. It is lower than the protrusion height Δh31 of 391. With such a configuration, in the production of the semiconductor device A10, the bonding wire 85 can be formed without being hindered by the burrs 293 and 393.

Here, in the second processing B2 of the manufacturing method of the semiconductor device A10, the first support portion 811 and the first support portion 812 formed earlier are sandwiched between the die 882 and the stripper 883. It forms 812 and a second support 822. By adopting such a manufacturing method, the burr 293 formed on the edge of the surface 801 of the first pad portion 811 and the burr 393 formed on the edge of the surface 801 of the second pad portion 821 are both formed on the die 882 and the burr 393. It is crushed by the stripper 883. Therefore, in the semiconductor device A10, the protrusion height Δh22 of the burr 293 is set lower than the protrusion height Δh21 of the burr 291 and the protrusion height Δh32 of the burr 393 is set lower than the protrusion height Δh31 of the burr 391. Can be done.

The first support portion 23 of the first reed 2 has a first outer surface 231 exposed to the outside of the semiconductor device A10 and a first inner side surface 232 facing the case 5. Since the burr 291 is formed on the edge of the first inner surface 232, the burr 291 is not formed on the edge of the first outer surface 231 (the sagging 292 is formed). With such a configuration, when the semiconductor device A10 is mounted, the entire first outer surface 231 becomes a smooth surface, so that the formation of solder fillets on the first outer surface 231 can be promoted. This contributes to the improvement of the mountability of the semiconductor device A10 on the circuit board.

Similarly, the second support portion 33 of the second lead 3 has a second outer surface 331 exposed to the outside of the semiconductor device A10 and a second inner surface 332 facing the case 5. Since the burr 393 is formed on the edge of the second inner surface 332, the burr 391 is not formed on the edge of the second outer surface 331 (the sagging 392 is formed). With such a configuration, when the semiconductor device A10 is mounted, the entire second outer surface 331 becomes a smooth surface, so that the formation of solder fillets on the second outer surface 331 can be promoted. This contributes to the improvement of the mountability of the semiconductor device A10 on the circuit board.

In the present embodiment, the interior plating layer 28 that covers the mounting surface 221 of the first pad portion 22 is formed. The interior plating layer 28 has an effect of protecting the first pad portion 22 from impact when the semiconductor element 11 is mounted on the mounting surface 221 by die bonding. Further, in the present embodiment, the interior plating layer 38 that covers the connection surface 321 of the second pad portion 32 is formed. The interior plating layer 38 has an effect of protecting the second pad portion 32 from impact when the bonding wire 4 is connected to the connection surface 321 by wire bonding.

The semiconductor element 11 according to this embodiment is a light emitting diode. The semiconductor device A10 includes a case 5 in which a recess 52 for accommodating the semiconductor element 11 is formed. The recess 52 is parallel to the top surface 51 of the case 5, and is inclined with respect to the bottom surface 521 and the bottom surface 521 where a part of the first pad portion 22 on which the semiconductor element 11 is mounted is exposed, and the semiconductor element 11 is formed. It has an inner peripheral surface 522 surrounding the. With such a configuration, the light emitted from the semiconductor element 11 is reflected by the inner peripheral surface 522, and the light is diffused in the recess 52. This contributes to the improvement of the brightness of the light emitted from the semiconductor device A10.

Further, the recess 52 is filled with a translucent sealing resin 6. The sealing resin 6 has an effect of improving the extraction efficiency of light emitted from the semiconductor element 11.

[Second Embodiment]
The semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. 20 to 23. In these figures, the same or similar elements as the above-mentioned semiconductor device A10 are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 20 is a perspective view of the semiconductor device A20. FIG. 21 is a plan view of the semiconductor device A20. FIG. 22 is a cross-sectional view taken along the line XXII-XXII of FIG. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII of FIG.

The semiconductor device A20 shown in these figures is, for example, a SOP type package that is surface-mounted on a circuit board of an automobile electrical component. As shown in FIGS. 20 and 21, the shape of the semiconductor device A20 in a plan view is rectangular. The semiconductor device A20 is different from the semiconductor device A10 described above in the configurations of the semiconductor element 11 and the sealing resin 6. Further, as shown in FIGS. 20 to 23, the semiconductor device A20 does not include the case 5.

The semiconductor element 11 according to this embodiment is a diode, for example, a Schottky barrier diode. A part of the element main surface 111 is a p-side electrode (anode). The P-side electrode is mainly composed of, for example, an Al layer, on which a Ni layer and a Pd layer are laminated with each other toward the outside of the semiconductor element 11. In the present embodiment, a Schottky barrier is formed by interposing a metal thin film (not shown) between the inside of the semiconductor element 11 and the element main surface 111. The metal thin film is composed of, for example, Mo or Ti. Further, the element back surface 112 is an n-side electrode. In the present embodiment, the bonding wire 4 similar to the semiconductor device A10 is connected to the p-side electrode. Here, when the semiconductor device A20 is used for a large current, a metal piece is used instead of the bonding wire 4 to connect the p-side electrode (element main surface 111) and the second pad portion 32 to the connection surface 321 (second lead). 3) may be connected. The metal piece is composed of, for example, an alloy containing Cu as a main component.

As shown in FIGS. 20 to 23, the sealing resin 6 according to the present embodiment is a synthetic resin having electrical insulating properties and thermosetting properties. The synthetic resin is, for example, a black epoxy resin. The sealing resin 6 covers all of the semiconductor element 11, the first pad portion 22 (first reed 2), the second pad portion 32 (second reed 3), and the bonding wire 4.

Next, the action and effect of the semiconductor device A20 will be described.

Similar to the semiconductor device A10, the semiconductor device A20 has burrs 291 formed on the edge of the first mounting back surface 212 facing the side opposite to the first mounting surface 211 of the first terminal portion 21 facing the circuit board. In this case, the burr 291 is not formed on the edge of the first mounting surface 211. Therefore, the mountability of the semiconductor device A20 on the circuit board is improved.

Further, in the semiconductor device A20, like the semiconductor device A10, burrs 293 are formed on the edge of the mounting surface 221 of the first pad portion 22 of the first lead 2 on which the semiconductor element 11 is mounted. Therefore, the bondability of the semiconductor element 11 to the first reed 2 (first pad portion 22) is improved. Therefore, the semiconductor device A20 can also improve both the mountability on the circuit board and the bondability of the semiconductor element with respect to the leads.

The semiconductor element 11 according to this embodiment is a diode. In the present invention, the type of the semiconductor element 11 is not limited, and various types of the semiconductor element 11 can be applied as long as it can be mounted on the first reed 2.

The present invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be freely redesigned.

A10, A20: Semiconductor device 11: Semiconductor element 111: Element main surface 112: Element back surface 12: Bonding layer 2: First lead 21: First terminal portion 211: First mounting surface 212: First mounting back surface 22: First Pad part 221: Mounting surface 222: Back surface of first pad 23: First support part 231: First outer surface 232: First inner surface 28: Interior plating layer 291: Burr 292: Dripping 293: Burr 294: Dripping 3: First 2 lead 31: 2nd terminal part 311: 2nd mounting surface 312: 2nd mounting back surface 32: 2nd pad part 321: Connection surface 322: 2nd pad back surface 33: 2nd support part 331: 2nd outer surface 332: Second inner side surface 38: Interior plating layer 391: Burr 392: Dripping 393: Burr 394: Dripping 4: Bonding wire 5: Case 51: Top surface 52: Recessed portion 521: Bottom surface 522: Inner peripheral surface 6: Sealing resin 7: Exterior plating layer 80: Conductive base material 801: Front surface 802: Back surface 81: First conductive member 811: First pad portion 811a: Interior plating layer 812: First support portion 82: Second conductive member 821: Second pad portion 821a: Interior plating layer 822: Second support part 83: Case 831: Recession 841: Semiconductor element 842: Bonding material 85: Bonding wire 86: Encapsulating resin 87: Exterior plating layer 881: Punch 882: Die 883: Stripper Δh21, Δh22, Δh31, Δh32: Overhang height B1: First processing B2: Second processing Z: Thickness direction X: First direction Y: Second direction

Claims (16)

With semiconductor elements
A first terminal portion having a first mounting surface and a first mounting back surface facing each other in the thickness direction of the semiconductor element, and the first mounting surface facing the circuit board, and the first mounting back surface. oriented in the same direction, and which has the mounting surface on which the semiconductor element is mounted, a first pad part, wherein in the thickness direction are arranged spaced apart from the first terminal portion, the thickness from the first terminal portion is erected in a direction, and a first support portion supporting the first pad portion, as well as have a, a first lead which is integrally formed,
A sealing resin that covers the semiconductor element and at least a part of the first pad portion is provided.
Burrs are formed on both the edge of the back surface of the first mounting surface and the edge of the mounting surface .
The protruding height of the burrs formed on the edge of the mounting surface is lower than the protruding height of the burrs formed on the edge of the back surface of the first mounting.
The semiconductor element has an element main surface that faces in the same direction as the mounting surface.
Further provided with a bonding wire connected to the element main surface,
In a plan view, the burrs formed on the edge of the mounting surface are located on both sides in a direction orthogonal to the direction in which the bonding wire extends, and are located with the semiconductor element sandwiched between them. , Semiconductor device. A second terminal portion having a second mounting surface and a second mounting back surface facing each other in the thickness direction and having the second mounting surface facing the circuit board and the same direction as the second mounting back surface. A second pad that faces the above direction, has a connecting surface to which the bonding wire is connected, is arranged apart from the second terminal portion in the thickness direction, and is at least partially covered with the sealing resin. It has a portion and a second support portion that stands up from the second terminal portion in the thickness direction and supports the second pad portion, and is arranged apart from the first lead in the plan view. , And further equipped with an integrally molded second lead,
Burrs are formed on both the edge of the back surface of the second mounting surface and the edge of the connection surface.
The semiconductor device according to claim 1 , wherein the protruding height of the burr formed on the edge of the connecting surface is lower than the protruding height of the burr formed on the edge of the back surface of the second mounting. The first support portion has a first inner surface connected to the back surface of the first mounting.
The second support portion has a second inner surface connected to the back surface of the second mounting.
The semiconductor device according to claim 2 , wherein the first inner surface surface and the second inner surface surface face each other. The semiconductor device according to claim 3, wherein burrs are formed on both the edge of the first inner surface surface and the edge of the second inner surface surface. The semiconductor device according to any one of claims 2 to 4, wherein the first lead and the second lead are made of the same conductive substrate. The semiconductor device according to claim 5, wherein the conductive base material contains an alloy containing Cu as a main component. The semiconductor element has an element back surface that faces the side opposite to the element main surface.
The semiconductor device according to any one of claims 2 to 6, which has conductivity and further includes a bonding layer interposed between the back surface of the element and the mounting surface. The semiconductor device according to any one of claims 2 to 7 , further comprising an interior plating layer that covers the mounting surface and the connecting surface. The semiconductor device according to claim 8 , wherein the interior plating layer contains Ag. The semiconductor device according to any one of claims 2 to 9, wherein the semiconductor element is a light emitting diode. Further provided with a synthetic resin case having a top surface facing in the same direction as the element main surface and having a recess formed from the top surface and a recess for accommodating the semiconductor element.
The sealing resin has translucency and is
The semiconductor device according to claim 10 , wherein the recess is filled with the sealing resin. The recess has a bottom surface parallel to the top surface, and an inner peripheral surface connected to the bottom surface and the top surface and surrounding the semiconductor element.
The semiconductor device according to claim 11, wherein the inner peripheral surface is inclined with respect to the bottom surface. The semiconductor device according to claim 12 , wherein a part of each of the mounting surface and the connecting surface is exposed from the bottom surface. The first support portion has a first outer surface connected to the first mounting surface.
The second support portion has a second outer surface connected to the second mounting surface.
The semiconductor device according to any one of claims 2 to 13, wherein both the first outer surface and the second outer surface are exposed to the outside. The semiconductor device according to claim 14, further comprising an exterior plating layer that covers the first mounting surface, the first outer surface, the second mounting surface, and the second outer surface. The semiconductor device according to claim 15 , wherein the exterior plating layer contains Ag.

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