JPH08330476A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH08330476A JPH08330476A JP7133227A JP13322795A JPH08330476A JP H08330476 A JPH08330476 A JP H08330476A JP 7133227 A JP7133227 A JP 7133227A JP 13322795 A JP13322795 A JP 13322795A JP H08330476 A JPH08330476 A JP H08330476A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- semiconductor device
- bed
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置の
薄型化に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thinner resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の半導体装置を製造方法を例に図3
に示す。図３(a) は従来の１つの樹脂外囲器の中に１つ
の半導体チップを搭載した半導体装置の断面図を示し
た。ベット部101 及びリード107 は例えばアロイ( 鉄、
ニッケル合金) 、銅等からなる１枚の金属薄板の打ち抜
き加工により形成している。まず、一表面に電極パッド
106 を有する半導体チップ105 を樹脂接着剤103 により
ベッド部101 上に固定する。次にリード107 と半導体チ
ップ105 を電気的に接続する例えば直径が10μｍ程度の
金ワイヤ107 を、半導体チップ105 の電極パッド106 に
熱圧着する。2. Description of the Related Art A conventional semiconductor device manufacturing method is shown in FIG.
Shown in FIG. 3A shows a cross-sectional view of a semiconductor device in which one semiconductor chip is mounted in one conventional resin envelope. The bet 101 and the lead 107 are made of, for example, alloy (iron,
It is formed by punching a single thin metal plate made of nickel alloy), copper or the like. First, the electrode pad on one surface
A semiconductor chip 105 having 106 is fixed onto the bed portion 101 with a resin adhesive 103. Next, a gold wire 107 having a diameter of, for example, about 10 μm for electrically connecting the lead 107 and the semiconductor chip 105 is thermocompression bonded to the electrode pad 106 of the semiconductor chip 105.
【０００３】次にベッド部101 、半導体チップ105 、ワ
イヤ109 、リード107 を金型に封入し、例えばエポキシ
樹脂によりモールド成型することにより外囲器111 を形
成し、樹脂封止型半導体装置を完成させる。この樹脂封
止型半導体装置では、ベット部101 上に半導体チップ10
5 があり、半導体チップ105 の電極パッド106 が最上層
にある。このためワイヤ109 の占める領域だけ外囲器11
1 が大きくなってしまい、完成する樹脂封止型半導体装
置が厚くなってしまう。Next, the bed 101, the semiconductor chip 105, the wires 109, and the leads 107 are enclosed in a mold and molded with, for example, an epoxy resin to form an envelope 111, thus completing a resin-sealed semiconductor device. Let In this resin-sealed semiconductor device, the semiconductor chip 10 is placed on the bed 101.
5 and the electrode pads 106 of the semiconductor chip 105 are on the top layer. Therefore, only the area occupied by the wire 109
1 becomes large and the completed resin-sealed semiconductor device becomes thick.
【０００４】図３(b) は、従来の樹脂封止型半導体装置
の寸法を示した図であり、特に外囲器111 の厚さに影響
を及ぼすベッド部101 と、半導体チップ105 と、ベッド
部101 と半導体チップ105 を接着する樹脂接着剤103
と、半導体チップ105 とリード107 を電気的に接続する
ワイヤ109 のラウンド部109aの寸法について示した。FIG. 3 (b) is a diagram showing the dimensions of a conventional resin-sealed semiconductor device, in particular, the bed portion 101 that affects the thickness of the envelope 111, the semiconductor chip 105, and the bed. Resin adhesive 103 for bonding the part 101 and the semiconductor chip 105
The dimensions of the round portion 109a of the wire 109 that electrically connects the semiconductor chip 105 and the lead 107 are shown.
【０００５】例えばベッド部101 の厚さは約125 μｍで
ある。半導体チップ105 の厚さは約350 μm である。半
導体チップ105 とベッド部101 を接着する樹脂接着剤10
3 の厚さは約30μm である。半導体チップ105 とリード
107 を接続する、ワイヤ109のラウンド部109aの長さは
約140 μm である。以上の厚さを合計すると、外囲器11
1 の中に含まれる構造の厚さは、645 μm となる。ベッ
ド部101 、樹脂接着剤103 、半導体チップ105 の寸法を
小さくするためには、新たな技術の開発が必要となって
しまう。そこで、新たな技術を開発することなく、従来
技術を用いた外囲器111 のワイヤ109 のラウンド部109a
の占める割合をいかに小さくするかが、検討されてい
る。For example, the bed portion 101 has a thickness of about 125 μm. The semiconductor chip 105 has a thickness of about 350 μm. Resin adhesive 10 that bonds the semiconductor chip 105 to the bed 101
The thickness of 3 is about 30 μm. Semiconductor chip 105 and lead
The length of the round part 109a of the wire 109 connecting the 107 is about 140 μm. When the above thicknesses are added together, the envelope 11
The thickness of the structure contained in 1 is 645 μm. In order to reduce the dimensions of the bed portion 101, the resin adhesive 103, and the semiconductor chip 105, it is necessary to develop new technology. Therefore, the round part 109a of the wire 109 of the envelope 111 using the conventional technology is developed without developing a new technology.
How to reduce the proportion of the
【０００６】また、半導体チップ105 の電極パッド106
を有する面に高熱を発生する回路素子がある。しかしこ
の面上に直接熱伝導性の悪いエポキシ樹脂から構成され
る外囲器111 があるため、半導体チップ105 から発生す
る熱の放熱が出来ないという問題が生じる。Also, the electrode pad 106 of the semiconductor chip 105
There is a circuit element that generates high heat on the surface having. However, there is a problem that heat generated from the semiconductor chip 105 cannot be dissipated because the envelope 111 directly made of epoxy resin having poor heat conductivity is provided on this surface.
【０００７】[0007]
【発明が解決しようとする課題】従来の樹脂封止型半導
体装置を構成する、半導体チップと、ベッド部と、半導
体チップとベッド部を接着する樹脂接着剤の寸法を小さ
くするのは技術的に難しい。実際、多くの研究者が、樹
脂封止型半導体装置構成する素子の小型化に取り組んで
いるが、技術の達成は難しい。また、半導体チップ、ベ
ット部の厚さを安易に薄くしたり、樹脂接着材の量を少
なくすれば完成する樹脂封止型半導体装置の、耐久性、
信頼性という点で問題が生じてしまう。そのため、樹脂
封止型半導体装置を信頼性を維持したまま、いかに樹脂
封止型半導体装置を薄型化するかが問題となっている。
特にワイヤボンディング方式ではワイヤの占める寸法だ
け樹脂半導体装置の厚さが厚くなることが問題となって
いる。It is technically necessary to reduce the dimensions of the semiconductor chip, the bed portion, and the resin adhesive for bonding the semiconductor chip and the bed portion, which constitute the conventional resin-sealed semiconductor device. difficult. In fact, many researchers are working on the miniaturization of the elements constituting the resin-encapsulated semiconductor device, but it is difficult to achieve the technology. In addition, the durability of the resin-encapsulated semiconductor device completed by easily reducing the thickness of the semiconductor chip and the bed portion or reducing the amount of the resin adhesive,
There is a problem in terms of reliability. Therefore, how to make the resin-encapsulated semiconductor device thinner while maintaining the reliability of the resin-encapsulated semiconductor device has become a problem.
Particularly, in the wire bonding method, there is a problem that the resin semiconductor device becomes thicker by the size occupied by the wire.
【０００８】また従来の樹脂封止型半導体装置では、半
導体チップの素子を有する面上にはエポキシ樹脂から構
成されるモールド樹脂層がある。半導体チップの素子は
動作時に熱を発生するが、モールド樹脂層は熱導伝性が
悪いため半導体チップで発生した熱を放熱することが出
来ない。そのため樹脂封止型半導体装置の放熱性が悪
く、製品の信頼性に悪影響を及ぼす。Further, in the conventional resin-sealed semiconductor device, a mold resin layer made of epoxy resin is provided on the surface of the semiconductor chip having the elements. Although the element of the semiconductor chip generates heat during operation, the heat generated in the semiconductor chip cannot be dissipated because the mold resin layer has poor heat conductivity. Therefore, the heat dissipation of the resin-encapsulated semiconductor device is poor, which adversely affects the reliability of the product.
【０００９】本発明では、従来の素子から構成される樹
脂封止型半導体装置の薄型化及び放熱性向上を目的とす
る。An object of the present invention is to reduce the thickness and improve the heat dissipation of a resin-sealed semiconductor device composed of conventional elements.
【００１０】[0010]
【課題を解決するための手段】本発明に示す樹脂封止型
半導体装置は、一表面の周囲に電極パッドを配置した半
導体チップと、この半導体チップを設置するベッド部
と、電極パッドに電気的に接続されるリード部と、前記
半導体チップ及びリード部を被履する外囲器と、半導体
チップの一表面とベット部を接着する手段とを有する。
また、半導体チップの一表面とベット部を接着する領域
とは一表面の電極パッドを除いた領域であることを特徴
とする。また、ベット部とリード部は同一平面上になく
且つ半導体チップの一表面に近い平面上にあることを特
徴とする。SUMMARY OF THE INVENTION A resin-sealed semiconductor device according to the present invention has a semiconductor chip having electrode pads arranged around one surface, a bed portion on which the semiconductor chips are installed, and an electrical pad. A lead part connected to the semiconductor chip, an envelope for covering the semiconductor chip and the lead part, and means for adhering one surface of the semiconductor chip to the bed part.
Further, the region where the one surface of the semiconductor chip and the bed portion are bonded is characterized by being a region excluding the electrode pads on the one surface. Further, the bed portion and the lead portion are not on the same plane and are on a plane close to one surface of the semiconductor chip.
【００１１】[0011]
【作用】半導体チップの電極パッドの有する面と半導体
チップを支持するベッド部の間に半導体チップとベット
部を接着する手段を有し、且つ半導体チップ表面の電極
パッドのない領域とベット部を接着し、且つリード部は
半導体チップの電極パッドを有する面からベット部より
近い平面上にあるため、ワイヤの占める寸法がベット部
の厚さに含まれてしまう。そのため、ワイヤの占める寸
法が完成する樹脂封止型半導体装置の厚みに影響を及ぼ
さず、従来より薄型の樹脂封止半導体装置を完成するこ
とが出来る。A means for adhering the semiconductor chip and the bed portion is provided between the surface of the electrode pad of the semiconductor chip and the bed portion supporting the semiconductor chip, and the area without the electrode pad on the surface of the semiconductor chip and the bed portion are adhered. In addition, since the lead portion is located on a plane closer to the bed portion than the surface of the semiconductor chip having the electrode pads, the dimension occupied by the wire is included in the thickness of the bed portion. Therefore, the dimensions occupied by the wires do not affect the thickness of the completed resin-sealed semiconductor device, and a thinner resin-sealed semiconductor device than before can be completed.
【００１２】また、電極パッドを有する面上に接着する
手段及びベット部があるため半導体チップから発生する
熱の放熱性が向上する。Further, since the means for adhering and the bed portion are provided on the surface having the electrode pad, the heat dissipation of the heat generated from the semiconductor chip is improved.
【００１３】[0013]
【実施例】半導体装置の製造工程は、大きく２つの工程
に分けることが出来る。それはウエハー処理工程と組立
工程である。これらの工程は全く異なる性質を持ってお
り、ウエハー処理工程が本質的動作機能を作り出すのに
対して、組立工程の目的は実装形態の確保と機能保護で
ある。近年製品コストに占める組み立て工程の割合の増
大、信頼性要求レベルの向上、高集積化、微細化等に伴
って、組立技術の重要性が高まってきている。EXAMPLE A semiconductor device manufacturing process can be roughly divided into two processes. It is a wafer processing process and an assembly process. These processes have completely different properties, and while the wafer processing process creates the essential operating function, the purpose of the assembly process is to secure the mounting form and protect the function. In recent years, the importance of the assembly technique has been increasing with the increase in the ratio of the assembly process to the product cost, the improvement of the required reliability level, the high integration, the miniaturization and the like.
【００１４】図１に組立工程の各工程を順に追って説明
する。まず拡散済み半導体基板の裏面を研磨し、半導体
基板の厚みを組み立てに必要な厚さにする裏面研削工程
を行う（ａ）。次に半導体基板上に形成した、多数の素
子をダイシングにより、個別に分離する。ダイシング法
にはダイヤモンドスクライビング法とレーザースクライ
ビング法がある。個々に分離された素子を半導体チップ
と呼ぶ。これがダイシング工程である（ｂ）。次にウエ
ハーから個々に分離された半導体チップを、セラミック
外囲器やリードフレームの指定箇所に、指定された方向
に接合し、固定する。これがマウント工程である
（ｃ）。次にチップの表面にある電極と、外囲器の外に
出るリード電極とを接続する。この工程をボンディンデ
ィングと呼ぶ。ボンディング方法は、ワイヤボンディン
グとワイヤレスボンディングに大別される。また、特に
多ピンの半導体装置の場合では、全接続箇所の確実な接
合は素子信頼性から見ると重要である（ｄ）。次にチッ
プの保護のために、チップ全体を樹脂で覆うか、又は中
空にしたまま外周をプラスチック等で囲み、モールド工
程を行う（ｅ）。次に、金型の変形磨耗による隙間の発
生やリードフレームの厚さのばらつきにより発生したバ
リを取り、整形するデフラッシュ工程を行う（ｆ）。次
にリードフレームの不要な部分を切断するカット工程を
したり、リード部を曲げるベント工程をし、個別に所定
の形状にし、樹脂封止型半導体装置を完成させる
（ｇ）。Each step of the assembling process will be described in sequence with reference to FIG. First, the back surface of the diffused semiconductor substrate is polished to perform a back surface grinding step for adjusting the thickness of the semiconductor substrate to a thickness required for assembly (a). Next, a large number of elements formed on the semiconductor substrate are individually separated by dicing. The dicing method includes a diamond scribing method and a laser scribing method. Individually separated elements are called semiconductor chips. This is the dicing step (b). Next, the semiconductor chips individually separated from the wafer are bonded and fixed to specified positions on the ceramic envelope or the lead frame in the specified direction. This is the mounting step (c). Next, the electrodes on the surface of the chip are connected to the lead electrodes that go out of the envelope. This process is called bonding. Bonding methods are roughly classified into wire bonding and wireless bonding. Further, particularly in the case of a multi-pin semiconductor device, reliable joining at all connection points is important in terms of element reliability (d). Next, in order to protect the chip, the entire chip is covered with resin, or the outer periphery is surrounded by plastic or the like while being hollow, and a molding step is performed (e). Next, a deflashing step is performed to remove and shape burrs generated due to the generation of gaps due to deformation and wear of the mold and variations in the thickness of the lead frame (f). Then, a cutting process for cutting unnecessary portions of the lead frame and a bending process for bending the lead portion are performed to individually form the resin frame into a predetermined shape to complete the resin-sealed semiconductor device (g).
【００１５】本発明に示す樹脂封止型半導体装置の製造
方法は、以上の工程に従い製造される。図２(a) は本発
明に示す第１の樹脂封止型半導体装置の断面図であり、
図２(b) に、本実施例に示す第１の樹脂封止型半導体装
置の、モールディング工程前の上から見た平面図を示
す。The method of manufacturing a resin-sealed semiconductor device according to the present invention is manufactured according to the above steps. FIG. 2A is a sectional view of the first resin-encapsulated semiconductor device according to the present invention,
FIG. 2B shows a plan view of the first resin-encapsulated semiconductor device shown in this embodiment as seen from above before the molding step.
【００１６】本発明に示す樹脂封止型半導体装置は、一
表面10の周囲に電極パッド6 を配置した半導体チップ5
と、この半導体チップ5 を一表面10側で設置するベッド
部1と、電極パッド6 に電気的に接続されベット部1 の
載置面よりも半導体チップ5の一表面10に近い平面にあ
って電極パッド6 に例えば金ワイヤ9 により電気的に接
続される面を載置するリード部7 と、半導体チップ5 及
びリード部7 を被履する外囲器11と、半導体チップ5 の
一表面10とベット部1 を接着する樹脂接着材3とを有す
る。ここで、ベット部1 と半導体チップ5 の接着する領
域は、半導体チップ5 の一表面10の電極パッド6 を除い
た領域であることを特徴とする。The resin-encapsulated semiconductor device according to the present invention has a semiconductor chip 5 in which electrode pads 6 are arranged around one surface 10.
The bed part 1 on which the semiconductor chip 5 is installed on the one surface 10 side and the plane electrically connected to the electrode pad 6 and closer to the one surface 10 of the semiconductor chip 5 than the mounting surface of the bed part 1. A lead portion 7 on which a surface electrically connected by, for example, a gold wire 9 is placed on the electrode pad 6, a semiconductor chip 5 and an envelope 11 on which the lead portion 7 is mounted, and one surface 10 of the semiconductor chip 5. A resin adhesive (3) for adhering the bed portion (1). Here, the region where the bet portion 1 and the semiconductor chip 5 are adhered is characterized by being a region excluding the electrode pad 6 on the one surface 10 of the semiconductor chip 5.
【００１７】次に本発明の実施例に示す樹脂封止型半導
体装置を製造工程を例に示す。まず、ベット部1 、リー
ド7 及び吊りピン8 を例えばアロイ( 鉄、ニッケル合
金) 、銅等からなるの金属薄板を打ち抜き加工により形
成する。ここで金属薄板を打ち抜き加工する際、ベット
部1 はリード部7 に対して200 μm 程度デプレスする。
ベット部1 は8,000 μｍ程度のほぼ正方形である。次に
１辺が10,000μm 程度のほぼ正方形の半導体チップ5 の
一表面10上の周辺領域に電極パッド6 を形成する。次
に、電極パッド6 を形成した半導体チップ5 の一表面10
上にに樹脂接着材3からなる層を形成する。次に半導体
チップ5 上にベット部1 を位置合せし、プレスして半導
体チップ5 とベット部1 を接着する。ここで、ベット部
1 は樹脂接着剤3 のはみ出ることを考慮に入れて、半導
体チップ5 の一表面10より小さいか、半導体チップ5 の
電極パッドが露出する形であることが望ましい。例え
ば、ベット部1 の形は図１(b) に示す形が考えられる。
このような形にして、ベット部1の周辺と電極パッド6
を300 μm 程度離せば樹脂接着剤3 がはみ出して電極パ
ッド部6 と接触することを防ぐことが出来る。次に半導
体チップ5 の電極パッド6とリード7 を電気的に接続す
る。ここで、半導体チップ5 の電極パッド6 とリード7
を電気的に接続する手段とは、例えば直径10μｍ程度の
金ワイヤ9 と半導体チップ5 の電極パッド6 に熱圧着し
た時に形成する金ワイヤ9 先端部に形成されるボンディ
ングングボール部である。次に半導体チップ5 、ベット
部1 及びリード部7 を金型に封入し、例えばエポキシ樹
脂により外囲器11を形成し樹脂封止型半導体装置を完成
させる。Next, the manufacturing process of the resin-encapsulated semiconductor device according to the embodiment of the present invention will be described as an example. First, the bed portion 1, the leads 7 and the suspension pins 8 are formed by punching a thin metal plate made of, for example, alloy (iron, nickel alloy), copper or the like. Here, when punching the thin metal plate, the bed portion 1 is depressed by about 200 μm with respect to the lead portion 7.
The bed 1 is approximately 8,000 μm square. Next, the electrode pad 6 is formed in the peripheral region on the one surface 10 of the semiconductor chip 5 having a substantially square shape with one side of 10,000 μm. Next, one surface 10 of the semiconductor chip 5 on which the electrode pad 6 is formed
A layer made of the resin adhesive 3 is formed on the top. Next, the bet portion 1 is aligned with the semiconductor chip 5 and pressed to bond the semiconductor chip 5 and the bet portion 1 together. Where bet section
It is desirable that 1 is smaller than the one surface 10 of the semiconductor chip 5 or that the electrode pad of the semiconductor chip 5 is exposed in consideration of the protrusion of the resin adhesive 3. For example, the bet portion 1 may have the shape shown in FIG. 1 (b).
With this shape, the periphery of the bed 1 and the electrode pad 6
It is possible to prevent the resin adhesive 3 from squeezing out and coming into contact with the electrode pad portion 6 by separating them by about 300 μm. Next, the electrode pad 6 of the semiconductor chip 5 and the lead 7 are electrically connected. Here, the electrode pad 6 and the lead 7 of the semiconductor chip 5 are
The means for electrically connecting the is a bonding ball portion formed at the tip of the gold wire 9 formed when the gold wire 9 having a diameter of about 10 μm and the electrode pad 6 of the semiconductor chip 5 is thermocompression bonded. Next, the semiconductor chip 5, the bed portion 1 and the lead portion 7 are sealed in a mold, and the envelope 11 is formed of, for example, epoxy resin to complete the resin-sealed semiconductor device.
【００１８】ここで、半導体チップ5 とベッド部1 を接
着する手段とは、半導体チップ5 の素子を形成している
表面の保護という点を考慮に入れて、常温で処理を行え
る樹脂接着剤3 を用いる樹脂接着法が望ましい。また、
樹脂接着材3 は絶縁物であることが望ましい。この条件
を満たす接着剤として例えば住友デークラフト社製CRM
−1143が挙げられる。この接着剤は外囲器を構成するエ
ポキシ樹脂層より熱伝導性が良い。Here, the means for adhering the semiconductor chip 5 and the bed portion 1 is a resin adhesive 3 which can be treated at room temperature in consideration of protection of the surface of the semiconductor chip 5 on which the elements are formed. A resin bonding method using is preferable. Also,
The resin adhesive 3 is preferably an insulator. As an adhesive that satisfies this condition, for example, CRM manufactured by Sumitomo Day Craft Co., Ltd.
-1143 is mentioned. This adhesive has better thermal conductivity than the epoxy resin layer forming the envelope.
【００１９】図１(c) は、本実施例に示す第１の樹脂封
止型半導体装置の断面の寸法であり、特に外囲器の厚さ
に影響を及ぼすベッド部1 と、半導体チップ5 と、ベッ
ド部1 と半導体チップ5 を接着する樹脂接着剤3 と、半
導体チップ5 とリード7 を電気的に接続するワイヤ9 の
ラウンド部9aの寸法について示した。例えばベッド部1
の厚さは約125 μm である。半導体チップ5 の厚さは約
350 μm である。半導体チップ5 とベッド部1 を接着す
る樹脂接着剤3 の厚さは約30μm である。本実施例で
は、半導体チップ5 とリード7 を接続する、ワイヤ9 の
ラウンド部分9aの厚さは、樹脂接着剤3 とベッド部1 の
厚さに吸収されてしまう。そこで、従来例に比べると、
リード9 のラウンド部9aの寸法だけ樹脂封止型半導体装
置の厚さは小さくなる。以上の厚さを合計すると、樹脂
封止型半導体装置の中に含まれる構造の厚さは、505 μ
m となり、従来の樹脂封止型半導体装置と比べると、14
0 μm 程度小さくなる。この効果を得るためにはベット
部のデプレスが150 〜200 μｍ程度にすれば従来より薄
い樹脂封止型半導体装置を提供することが出来る。FIG. 1C shows the cross-sectional dimensions of the first resin-encapsulated semiconductor device according to this embodiment, and particularly the bed portion 1 and the semiconductor chip 5 that affect the thickness of the envelope. The dimensions of the resin adhesive 3 for bonding the bed portion 1 and the semiconductor chip 5 and the size of the round portion 9a of the wire 9 for electrically connecting the semiconductor chip 5 and the lead 7 are shown. Bed section 1 for example
Has a thickness of about 125 μm. The thickness of the semiconductor chip 5 is approx.
350 μm. The resin adhesive 3 for bonding the semiconductor chip 5 and the bed 1 has a thickness of about 30 μm. In this embodiment, the thickness of the round portion 9a of the wire 9 connecting the semiconductor chip 5 and the lead 7 is absorbed by the thickness of the resin adhesive 3 and the bed portion 1. Therefore, compared to the conventional example,
The thickness of the resin-sealed semiconductor device is reduced by the size of the round portion 9a of the lead 9. When the above thicknesses are summed up, the thickness of the structure contained in the resin-sealed semiconductor device is 505 μm.
m, which is 14 compared to conventional resin-sealed semiconductor devices.
It becomes about 0 μm smaller. In order to obtain this effect, if the depress of the bed portion is set to about 150 to 200 μm, it is possible to provide a resin-sealed semiconductor device thinner than before.
【００２０】また、半導体チップの電極パッド6 を有す
る表面10付近には高熱を発生する回路素子が形成されて
いる。表面10上に、外囲器11より熱伝導性の良い樹脂接
着剤3 の層と熱伝導性が良いベッド部がある。このた
め、従来の樹脂封止型半導体装置に比べて放熱性の良い
樹脂封止型半導体装置を提供することが出来る。A circuit element that generates high heat is formed near the surface 10 having the electrode pad 6 of the semiconductor chip. On the surface 10, there are a layer of the resin adhesive 3 having better thermal conductivity than the envelope 11 and a bed section having better thermal conductivity. Therefore, it is possible to provide a resin-encapsulated semiconductor device having better heat dissipation than the conventional resin-encapsulated semiconductor device.
【００２１】[0021]
【発明の効果】本実施例に示すように、半導体チップの
電極を有する面とベッド部の間に接着する手段を有する
構造にしたため、ワイヤのラウンド部の寸法だけ樹脂封
止型半導体装置の厚さを薄くすることが出来る。As shown in the present embodiment, since the structure having the means for adhering between the surface of the semiconductor chip having the electrodes and the bed portion is employed, the thickness of the resin-sealed semiconductor device is equal to the size of the round portion of the wire. The thickness can be reduced.
【００２２】また、半導体チップの電極を有する面上に
熱伝導性の良いベット部があるため、従来の樹脂半導体
装置に比べて半導体チップから発生する熱の放熱性が向
上する。そのため、樹脂封止型半導体装置の信頼性が向
上する。Further, since the bed portion having good thermal conductivity is provided on the surface of the semiconductor chip having the electrodes, the heat radiation performance of the heat generated from the semiconductor chip is improved as compared with the conventional resin semiconductor device. Therefore, the reliability of the resin-encapsulated semiconductor device is improved.
【図１】図１は樹脂封止型半導体装置の製造工程フロー
である。FIG. 1 is a manufacturing process flow of a resin-sealed semiconductor device.
【図２】図２は本発明の実施例を示す樹脂封止型半導体
装置の断面図(a) 、上面図(b)、及び寸法を示した断面
図(c) である。FIG. 2 is a sectional view (a), a top view (b), and a sectional view (c) showing dimensions of a resin-encapsulated semiconductor device showing an embodiment of the present invention.
【図３】図３は従来の樹脂封止型半導体装置の断面図
(a) 及び寸法を示した断面図(b)である。FIG. 3 is a sectional view of a conventional resin-sealed semiconductor device.
It is sectional drawing (b) which showed (a) and dimensions.
1 ベッド部 3 樹脂接着剤 5 半導体チップ 6 電極パッド 7 リード 8 吊りピン 9 、9a ワイヤ 10 一表面 11 外囲器 1 Bed part 3 Resin adhesive 5 Semiconductor chip 6 Electrode pad 7 Lead 8 Hanging pin 9, 9a Wire 10 One surface 11 Enclosure
Claims (5)
体チップと、この半導体チップを設置するベッド部と、
前記電極パッドに電気的に接続されるリード部と、前記
半導体チップ及びリード部を被履する外囲器と、前記半
導体チップの前記一表面と前記ベット部を接着する手段
とを有することを特徴とする樹脂封止型半導体装置。1. A semiconductor chip in which electrode pads are arranged around one surface, and a bed portion on which the semiconductor chip is installed,
It has a lead part electrically connected to the electrode pad, an envelope for covering the semiconductor chip and the lead part, and a means for adhering the one surface of the semiconductor chip and the bed part. And a resin-encapsulated semiconductor device.
ト部を接着する領域とは前記一表面の前記電極パッドを
除いた領域であることを特徴とする請求項１記載の樹脂
封止型半導体装置。2. The resin-encapsulated semiconductor according to claim 1, wherein the region where the one surface of the semiconductor chip and the bed portion are bonded is a region excluding the electrode pad on the one surface. apparatus.
になく且つこのリード部は前記半導体チップの前記一表
面に近い平面上にあることを特徴とする請求項１記載の
樹脂封止型半導体装置。3. The resin-sealed mold according to claim 1, wherein the bet portion and the lead portion are not on the same plane and the lead portion is on a plane close to the one surface of the semiconductor chip. Semiconductor device.
体チップと、この半導体チップを前記一表面側で設置す
るベッド部と、前記電極パッドに電気的に接続され前記
ベット部の載置面よりも前記半導体チップの前記一表面
に近い平面にあって前記電極パッドに電気的に接続され
る面を載置するリード部と、前記半導体チップ及びリー
ド部を被履する外囲器と、前記半導体チップの前記一表
面と前記ベット部を接着する手段とを有することを特徴
とする樹脂封止型半導体装置。4. A semiconductor chip in which electrode pads are arranged around one surface, a bed portion on which the semiconductor chip is installed on the one surface side, and a mounting surface of the bed portion electrically connected to the electrode pads. A lead portion on which a surface that is closer to the one surface of the semiconductor chip and that is electrically connected to the electrode pad is mounted, and an envelope that covers the semiconductor chip and the lead portion. A resin-encapsulated semiconductor device comprising a means for adhering the one surface of a semiconductor chip and the bed portion.
る領域は、前記半導体チップの前記一表面の前記電極パ
ッドを除いた領域であることを特徴とする請求項４記載
の樹脂封止型半導体装置。5. The resin-encapsulated semiconductor according to claim 4, wherein a region where the bet portion and the semiconductor chip are bonded is a region excluding the electrode pad on the one surface of the semiconductor chip. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7133227A JPH08330476A (en) | 1995-05-31 | 1995-05-31 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7133227A JPH08330476A (en) | 1995-05-31 | 1995-05-31 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08330476A true JPH08330476A (en) | 1996-12-13 |
Family
ID=15099708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7133227A Pending JPH08330476A (en) | 1995-05-31 | 1995-05-31 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08330476A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007048994A (en) * | 2005-08-11 | 2007-02-22 | Akita Denshi Systems:Kk | Semiconductor device and its manufacturing method |
| WO2014041648A1 (en) * | 2012-09-12 | 2014-03-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1995
- 1995-05-31 JP JP7133227A patent/JPH08330476A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007048994A (en) * | 2005-08-11 | 2007-02-22 | Akita Denshi Systems:Kk | Semiconductor device and its manufacturing method |
| WO2014041648A1 (en) * | 2012-09-12 | 2014-03-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5902305B2 (en) * | 2012-09-12 | 2016-04-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US9322837B2 (en) | 2012-09-12 | 2016-04-26 | Renesas Electronics Corporation | Semiconductor device |
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