JPH08321967A - Image horizontal direction distortion correction circuitry - Google Patents

Abstract

PURPOSE: To obtain the image horizontal direction distortion correction circuitry in which a correction value can be easily revised and an image horizontal direction distortion is corrected by use of common components, regardless of the screen size. CONSTITUTION: A PLL circuit 2 generates a write clock signal of a prescribed period synchronously with a horizontal synchronizing signal to write video signal data in a line memory 1 and a horizontal period counter 24 counts the write clock signal for one horizontal scanning period from the start of horizontal scanning and designates an address of a ROM 4 depending on the count. Then correction data based on the horizontal direction distortion of an image stored in the ROM 4 are read corresponding to the position for one horizontal scanning period and the read correction data are converted into an analog signal by a D/A converter 5 and the phase is shifted by a phase shifter 6. The clock signal synchronized with the horizontal synchronizing signal is frequency- modulated by an analog signal whose phase is shifted by a PLL circuit 3 and the video signal data are read out of the line memory 1 by using the clock signal subject to frequency modulation as a read clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image horizontal distortion correction circuit which can be used in a receiver such as a television receiver,
More specifically, the present invention relates to a horizontal image distortion correction circuit that changes a video signal to correct horizontal distortion of an image.

[0002]

2. Description of the Related Art A conventional image horizontal distortion correction circuit is shown in FIG.
Horizontal output transistor 1
1 and a damper diode 12, a capacitor 13 and a deflection coil 14, which turns on and off the transistor 11 by the horizontal oscillation output, and causes a sawtooth wave current to flow through the deflection coil 14. However, in such a conventional method, the waveform of the sawtooth wave current flowing in the deflection coil 14 becomes an S-shaped waveform as shown by the solid line in FIG. 5, and therefore, as shown in FIG. By connecting a series circuit of the coil 15 and the capacitor 16, the S-shaped waveform shown in FIG. 5 is corrected to be linear as shown by the broken line. 1
H indicates one horizontal scanning period.

[0003]

However, since the horizontal distortion of the image differs depending on the size of the cathode ray tube, when the above-mentioned conventional horizontal deflection circuit is used, a correction coil and a correction coil having different characteristics are used. There is a problem that dedicated parts such as capacitors are required for each size of the cathode ray tube, that is, for each screen size.

An object of the present invention is to provide an image horizontal distortion correction circuit in which the correction value can be easily changed and the distortion in the image horizontal direction can be corrected by common components regardless of the screen size. To do.

[0005]

An image horizontal distortion correction circuit according to the present invention generates a line memory for storing one line of video signal data and a write clock signal of a constant cycle in synchronization with a horizontal synchronizing signal. Writing clock signal generating means for supplying to a line memory, a ROM in which correction data based on horizontal distortion of an image is stored at a position corresponding to one horizontal scanning period, and one horizontal direction based on the writing clock signal. A correction signal generating unit that generates a horizontal position signal indicating a position during a scanning period, reads correction data based on the horizontal position signal from the ROM, converts the correction data into an analog signal, and outputs the analog signal as a correction signal, and the horizontal synchronization signal. A synchronized clock signal is generated, the clock signal is frequency-modulated by the correction signal, and the frequency-modulated And a read clock signal generating means for supplying to the line memory as a clock signal read lock signal, and outputs the video signal data read out from the line memory as corrected image signal data.

[0006]

The horizontal image distortion correction circuit according to the present invention is
Video signal data is written in the line memory by a write clock signal having a constant cycle which is synchronized with the horizontal synchronizing signal. The video signal data written in the line memory has the correction data read from the ROM based on the horizontal position signal indicating the position in one horizontal scanning period generated based on the write clock signal and converted into the analog signal. A clock signal which is a correction signal and is synchronized with the horizontal synchronizing signal is frequency-modulated by the correction signal. The frequency-modulated clock signal is supplied to the line memory as a read clock signal, and the video signal data is read from the line memory based on the read clock signal. However, since the cycle of the read clock signal is changed based on the correction signal, the horizontal distortion of the image is corrected.

[0007]

The present invention will be described below with reference to examples. FIG.
FIG. 3 is a block diagram showing a configuration of an embodiment of an image horizontal distortion correction circuit according to the present invention.

The image horizontal distortion correction circuit of this embodiment is
Line memory 1, PLL circuit 2, PLL circuit 3, ROM
4, a D / A converter 5 and a phase shifter 6. The line memory 1 has a storage capacity capable of storing a video signal converted into digital data, that is, video signal data for one line. The line memory 1 supplies the video signal data converted into digital data to the line memory 1 , And the video signal data read from the line memory 1 is sent as corrected video signal data.

The PLL circuit 2 generates a clock signal of a constant cycle in synchronization with the horizontal synchronizing signal (HD), and the PLL circuit 2
Is supplied as a write clock signal (WCK) for the line memory 1 to write video signal data to the line memory 1, and
The horizontal position information corresponding to the video signal data is read out to the ROM 4 and sent as address data.

The PLL circuit 3 generates a clock signal whose cycle is changed based on the correction data stored in the ROM 4, and the clock signal generated by the PLL circuit 3 is used as a read clock signal (RCK) for the line memory 1.
To read the video signal data from the line memory 1.

The PLL circuit 2 divides the oscillation output of the voltage control oscillator 23, which supplies the oscillation output as a write clock signal (WCK) to the line memory 1, and the oscillation output of the voltage control oscillator 23, and outputs it to the phase comparator 21. A horizontal position counter 24 for counting the oscillation output, and a horizontal position counter 24
Of the horizontal sync signal (HD) and a phase comparator 21 for smoothing the output of the phase comparator 21 and supplying the output to the voltage controlled oscillator 23 as a frequency control voltage. There is.

The voltage controlled oscillator 23 is, for example, 4 fsc (f
sc is set to the free-running oscillation frequency of the color subcarrier, and the horizontal position counter 24 is set to the voltage controlled oscillator 23.
The oscillating output of 1 is divided by 910 and supplied to the phase comparator 21, and the count value obtained by counting the oscillating output of the voltage controlled oscillator is supplied to the ROM 4 as address data. here,
The horizontal position counter 24 counts the oscillation output of the voltage controlled oscillator 23 for one horizontal scanning period from the start of horizontal scanning, and outputs the count value as the address data of the ROM 4.

The ROM 4 stores correction data for correcting the horizontal distortion of the image, that is, data for expanding and contracting the image according to the horizontal position to correct the horizontal distortion in correspondence with the horizontal scanning position. There is. The correction data read and addressed by the count value from the horizontal position counter 24 and read from the ROM 4 is converted into an analog signal by the D / A converter 5. D
The analog signal converted by the / A converter 5 is phase-shifted by a predetermined phase by the phase shifter 6 and output.

The PLL circuit 3 includes, for example, a voltage controlled oscillator 34 that supplies the oscillation output to the line memory 1 as a read clock signal (RCK), a frequency divider 35 that divides the oscillation output of the voltage controlled oscillator 34, and a frequency divider. The phase comparator 31 for phase-comparing the frequency-divided output of the frequency divider 35 and the horizontal synchronizing signal, the loop filter 32 for smoothing and outputting the output of the phase comparator 31, and the output of the loop filter 32 and the phase shifter 6 The output is added and the added output is supplied as a frequency control voltage to the voltage controlled oscillator 34.

The voltage controlled oscillator 34 is set to a free-running oscillation frequency of, for example, 4 fsc, and the frequency divider 35 is set to a frequency division ratio 910 that divides the oscillation output of the voltage controlled oscillator 34 by 910. Therefore, the oscillation frequency from the voltage controlled oscillator 34 is frequency-divided by the frequency divider 35 by 910, and phase-compared with the horizontal synchronizing signal (HD) by the phase comparator 31. The phase comparison output from the phase comparator 31 is smoothed by the loop filter 32, added by the adder 33 with the output from the phase shifter 6, and supplied to the voltage controlled oscillator 34 as a voltage control signal. As a result, the oscillation output of the voltage controlled oscillator 34 is synchronized with the horizontal synchronizing signal (HD) and is substantially frequency-modulated by the correction data read from the ROM 4, and the read clock signal (RCK) is generated. The cycle will be changed based on the correction data.

The operation of this embodiment configured as described above will be described. As shown in FIG. 2A, originally B
An example will be described in which the display image, which should be circular as shown in FIG. For example, there is a case where the left side portion of the image shrinks and the right side portion expands even if the both ends and the center of the image are properly adjusted.
This corresponds to the case where the S-shaped waveform distortion described above exists. In such a case, the correction data based on the distortion which becomes the analog signal having the waveform shown in FIG. 2B when converted into the analog voltage is written in the ROM 4 in correspondence with the position in the horizontal scanning direction. Has been.

One line of the input video data is sequentially written in the line memory 1 by the write clock signal (WCK) generated by the PLL circuit 2 having a constant cycle synchronized with the horizontal synchronizing signal (HD). During this writing, corresponding correction data is read from the ROM 4 on the basis of the position on the one line of the video signal data written in the line memory 1 from the horizontal position counter 24, that is, the D / A conversion. Converter 5 converts the analog signal into an analog signal, and the adder 33 adds the output to the loop filter 33 to change the oscillation frequency of the voltage controlled oscillator 34 based on the added output.

That is, the oscillation frequency of the voltage-controlled oscillator 34, that is, the frequency of the read clock signal (RCK) appears to be frequency-modulated by the output level from the D / A converter 5, and C in FIG. Since the level of the output analog signal from the D / A converter 5 is low at the level of the section, the oscillation frequency of the voltage controlled oscillator 34 is controlled to be low, and the time interval of the video signal data read from the line memory 1 is extended. Since the level of the output signal from the D / A converter 5 is high at the level of the D section in FIG. 2B, the oscillation frequency of the voltage controlled oscillator 34 is controlled to be high, and the video signal data read from the line memory 1 is controlled. 2 is shortened, the image based on the video data read from the line memory 1 is expanded / contracted. Elliptical image is corrected in circular image is made a correction to be compressed in the horizontal scanning direction in the case of.

Therefore, by using the correction data stored in the ROM 4 as the correction data based on the distortion of the image in the horizontal scanning direction, the distortion of the image in the horizontal scanning direction is corrected, and the screen size is changed. Also, if the distortion states are similar, the distortion is corrected by the common component. Further, even when the distortion state is different, it can be dealt with by rewriting the correction data stored in advance in the ROM 4 based on the distortion.

Although the operation of the phase shifter 6 has not been described in the above description, the operation of the phase shifter 6 will be described next.

By supplying the D / A converted output of the ROM 4 to the phase shifter 6, the phase shifter 6 performs a phase shift, and the D / A converted waveform is indicated by an arrow in FIG. It can be moved to the left and right, and the phase shift by the phase shifter 6 can finely adjust the correction of the horizontal distortion of the image. For example, the waveform E based on the correction data shown by the solid line in FIG. 3 is the analog signal waveform based on the correction data shown in FIG. When the phase E of the waveform E is delayed by the phase shifter 6, the analog signal indicated by the broken line F in FIG. 3 is supplied from the phase shifter 6 to the adder 33, which is most compressed by the correction. The position in the horizontal scanning direction is closer to the right side of the position in the horizontal scanning direction in FIG.

When the phase E of the waveform E is advanced by the phase shifter 6, the analog signal indicated by the alternate long and short dash line G in FIG. 3 is supplied to the adder 33 from the phase shifter 6. The position in the horizontal scanning direction that is most compressed by the correction is closer to the left side of the position in the horizontal scanning direction in FIG. Therefore, by adjusting the amount of phase shift by the phase shifter 6, it is possible to perform fine adjustment for slightly correcting the distortion of the corrected image and fine adjustment for the correction amount based on the data stored in the ROM 4. Such fine adjustment can be performed by adjusting the amount of phase shift of the phase shifter without changing the data stored in the ROM 4.

[0023]

As described above, according to the image horizontal distortion correction circuit according to the present invention, the horizontal distortion of the image is corrected by correcting the video signal, so that it is common regardless of the size of the screen. It is possible to obtain the effect that the correction can be performed by the parts. Further, there is an effect that the correction amount can be easily changed by rewriting the correction data based on the distortion.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an image horizontal distortion correction circuit according to the present invention.

FIG. 2 is a schematic diagram of an image and correction data for explaining the operation of an embodiment of the image horizontal distortion correction circuit according to the present invention.

FIG. 3 is a schematic diagram of correction data used to explain the operation of an embodiment of an image horizontal distortion correction circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a horizontal distortion correction circuit using a conventional horizontal deflection circuit.

FIG. 5 is a waveform diagram of a deflection current for explaining the operation of a horizontal distortion correction circuit using a conventional horizontal deflection circuit.

[Explanation of symbols]

 1 line memory 2 and 3 PLL circuit 4 ROM 5 D / A converter 6 phase shifter 21 and 31 phase comparator 22 and 32 loop filter 23 and 34 voltage control oscillator 24 horizontal position counter 33 adder 35 frequency divider

Claims (4)

[Claims] 1. A line memory for storing video signal data for one line, a write clock signal generating means for generating a write clock signal of a constant cycle synchronized with a horizontal synchronizing signal and supplying the same to the line memory, and a horizontal image. A ROM in which correction data based on directional distortion is stored corresponding to a position in one horizontal scanning period, and a horizontal position signal indicating a position in one horizontal scanning period is generated based on the write clock signal, and the horizontal position signal is generated. Correction signal generating means for reading correction data based on a position signal from the ROM and converting it into an analog signal and outputting it as a correction signal; and a clock signal which is synchronized with the horizontal synchronizing signal and which is generated by the correction signal. Frequency-modulate and supply the frequency-modulated clock signal to the line memory as a read clock signal Read clock signal generating and means, image horizontal distortion correction circuit and outputting the video signal data read out from the line memory as corrected image signal data that. 2. The image horizontal distortion correction circuit according to claim 1, wherein the correction signal generating means counts the write clock signal for one horizontal scanning period from the start of horizontal scanning, and addresses the ROM by the count value. And a horizontal position counter, and a D / A conversion means for converting the correction data read from the ROM into an analog signal. 3. The image horizontal distortion correction circuit according to claim 1, wherein the correction signal generating means counts the write clock signal for one horizontal scanning period from the start of horizontal scanning, and addresses the ROM by the count value. An image including a horizontal position counter, a D / A converter for converting the correction data read from the ROM into an analog signal, and a phase shifter for shifting the analog signal by a predetermined phase. Horizontal distortion correction circuit. 4. The horizontal image distortion correction circuit according to claim 1, wherein the read clock signal generating means includes an adder for adding the clock signal and the correction signal and frequency-modulating the clock signal with the correction signal. An image horizontal distortion correction circuit characterized by: