JPH07298086A - Horizontal linearity correction circuit - Google Patents

Abstract

PURPOSE:To provide a horizontal linearity correction circuit in which stable operation is attained against fluctuation in temperature or power supply voltage without nonuniformly extended slave screen display or on-screen display even when the middle of image is compressed and the surrounding of the image is expanded while a video image whose aspect ratio is 4:3 is fully displayed on the screen of a display device whose aspect ratio is 16:9. CONSTITUTION:A video signal itself is compressed or expanded by using a memory 125 without selecting a linearity (S-shaped correction) of a deflection system, a read clock for the memory 125 is generated by a digital controlled oscillator 113 based on a write clock and the digital controlled oscillator 113 is modulated by a parabolic signal in the horizontal direction and the desired display mode is realized. The frequency read digitally is controlled and parabolic modulation is applied to the video signal stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal linearity correction circuit used for a television receiver having a wide aspect ratio (16: 9) display screen.

[0002]

2. Description of the Related Art In recent years, television receivers having an aspect ratio of 16: 9 (hereinafter referred to as wide TV receivers) have become widespread. When receiving the signal sent at the current 4: 3 in the wide TV receiver, the 16: 9 display is effectively used by relatively shrinking the central part of the screen and extending it toward the peripheral part. However, a method of displaying a 4: 3 image as naturally as possible is being adopted.

FIG. 5 shows a screen display example when a crosshatch pattern signal which is a video signal having an aspect ratio of 4: 3 is displayed on a display having an aspect ratio of 16: 9.

In FIG. 5, (a) is a mode for displaying a 16: 9 video signal, and a 4: 3 signal extends in the horizontal direction as a whole. (b) is a mode in which the left and right sides are compressed to 3/4, and a 4: 3 signal is displayed in a normal aspect ratio. However, blank areas with no signal are displayed on the left and right sides of the screen. In (c), the central part of the screen is compressed and stretches toward the periphery, so the most important central part does not look like a horizontal stretch, and the peripheral part of relatively low importance stretches horizontally. By widening the image to fill the 16: 9 screen, the wide screen can be fully utilized even in the current 4: 3 broadcast.

As is well known, in a CRT (cathode ray tube) used as a display means, the movement amount (deflection speed) of the electron beam on the tube surface is larger in the peripheral portion than in the central portion. The horizontal deflection current is subjected to a correction called S-shaped correction so as to reduce the value in comparison with the central portion.

That is, in the horizontal deflection circuit, a DC blocking capacitor called an S-shaped correction capacitor is connected in series with the horizontal deflection coil, and the series resonance current of this capacitor and the horizontal deflection coil is superposed on the sawtooth wave current for horizontal deflection. The current is corrected by bending it into an S shape. The linearity in the horizontal direction of the screen can be improved by properly selecting the value of the S-shaped correction capacitor.

Therefore, conventionally, as a method for realizing the mode shown in FIG. 5 (c), it is realized by changing the deflection speed by switching the horizontal linearity correction characteristic (S-shaped characteristic) of the horizontal deflection circuit. Was there.

FIG. 6 shows a horizontal deflection current waveform controlled by a horizontal linearity correction circuit in a conventional deflection system.

In FIG. 6, reference numeral 301 denotes an S-shaped corrected horizontal deflection current, which maintains the horizontal linearity on the screen, and is shown in FIG. 5 (a) (or FIG. 5). As shown in (b)), the cross hatch is displayed evenly. Reference numeral 302 indicates a horizontal deflection current waveform which is hardly subjected to the above S-shaped correction, whereby the peripheral portion of the screen in the horizontal direction becomes longer than the central portion, as shown in FIG. 5 (c). Is displayed. Reference numeral 302
In order to obtain the horizontal deflection current of, the S-shaped correction capacitor may be switched so that the capacity of the S-shaped correction capacitor becomes large.

By the way, in order to realize the screen mode shown in FIG. 5 (c), by switching the horizontal linearity correction (S-shaped correction) of the deflection system, the deflection speed is changed in the central portion and the peripheral portion of the screen. , So the picture-in-picture (P
When the (IP) display or the on-screen display is performed, the child screen display and the on-screen character display, which are displayed on the left and right of the screen that normally do not need to be changed, expand horizontally and the size changes. It is displayed in a uniform size), and the display quality deteriorates.

In order to enter the screen mode described above, it is necessary to switch the capacitance of the S-shaped correction capacitor connected in series to the horizontal deflection coil so as to have a large capacitance. However, such switching of circuit elements should be performed. However, it is difficult to perform stable correction for maintaining the screen mode when the temperature or the power supply voltage fluctuates.

[0012]

As described above, when displaying an image having an aspect ratio of 4: 3 on a display device having an aspect ratio of 16: 9, the central portion of the screen is relatively shrunk and the peripheral portion is relatively shrunk. If the horizontal linearity correction amount of the horizontal deflection circuit is switched so as to extend as much as possible, when sub-screen display or on-screen display is performed, these displays stretch horizontally and become uneven, resulting in poor display quality. Further, there is a problem in that stable operation cannot be performed with respect to changes in temperature and power supply voltage.

Therefore, in view of the above problems, the present invention has a horizontal linearity which does not affect the sub-screen display or the on-screen display, and can perform a stable operation even with respect to temperature and power supply voltage fluctuations. It is an object to provide a correction circuit.

[0014]

According to a first aspect of the present invention, there is provided a horizontal linearity correction circuit which synchronizes with a horizontal synchronizing signal of an input video signal and has a frequency n times (n is a natural number) the horizontal synchronizing frequency. A first clock generating means for generating a first clock signal and a second clock signal having a frequency of m times (m is a natural number); and an oscillation frequency depending on a digital control signal using the second clock signal as a reference clock. Controlled,
Digital control clock generating means for generating a third clock signal, and correction signal generating means for generating the digital control signal so that the third clock signal becomes a lower clock in the peripheral portion than in the central portion in the horizontal direction of the screen. And a memory means for inputting the video signal, writing the video signal with the first clock signal, reading the video signal with the third clock signal, and outputting the video signal with corrected horizontal linearity.

According to a second aspect of the present invention, in the horizontal linearity correction circuit according to the first aspect, the digital control clock generating means operates with the second clock signal as a reference clock, and a cycle is generated by the digital control signal. An integrator circuit that outputs a controlled sawtooth wave signal, a sine converter circuit that converts the sawtooth wave signal from this integrator circuit into a sine wave signal, and a sine wave signal from this sine converter circuit to an analog signal It is characterized by comprising a D / A converter and a waveform shaping circuit for converting the sinusoidal signal from the D / A converter into a rectangular wave-shaped third clock signal.

According to a third aspect of the present invention, in the horizontal linearity correction circuit according to the first aspect, the correction signal generating means is
It is characterized in that it is composed of a parabolic generating circuit for generating a parabolic wave signal of a horizontal cycle as a digital control signal.

A horizontal linearity correction circuit according to a fourth aspect of the present invention inputs a luminance signal and converts it into a digital luminance signal, a first A / D converter, and two color difference signals.
A multiplexing circuit that outputs these signals by time division multiplexing, a second A / D converter that converts the output of this multiplexing circuit into a digital color signal, and a horizontal synchronizing signal of the input luminance signal. A clock generation circuit for generating a timing signal having a horizontal synchronization frequency, a first clock signal having a frequency n times (n is a natural number) and a second clock signal having a frequency m times (m is a natural number) the horizontal synchronization frequency. A parabola generating circuit for generating a parabolic wave signal having a horizontal period;
Digitally controlled oscillator for generating a digital oscillation signal whose oscillation frequency is controlled in accordance with the parabolic wave signal using the clock signal as a reference clock, and a first D / A for converting the output of this digitally controlled oscillator into an analog signal.
A converter, a waveform shaping circuit for converting a signal from the first D / A converter into a rectangular wave-shaped third clock signal, a timing signal from the clock generation circuit, a first clock signal and the waveform A timing generation circuit for receiving a third clock signal from the shaping circuit and generating a write timing signal and a read timing signal;
The digital luminance signal from the A / D converter of
The digital color signal from the A / D converter is input, the write timing signal is used to write with the first clock signal, the read timing signal is used to read with the third clock signal, and the central portion of the screen is displayed in a horizontal cycle. A line memory that outputs a digital luminance signal and a digital chrominance signal that are compressed and expanded toward the periphery,
Input the digital luminance signal from this line memory,
A second D / A converter for converting into an analog luminance signal and a third D / A converter for inputting a digital color signal from the line memory and converting a first color difference signal in the color signal into an analog color difference signal. An A converter and a fourth D / A converter for inputting a digital color signal from the line memory and converting a second color difference signal in the color signal into an analog color difference signal are provided.

[0018]

According to the present invention, when displaying an image having an aspect ratio of 4: 3 on a display device having an aspect ratio of 16: 9, the peripheral portion is controlled as compared with the central portion of the screen by controlling the writing and reading of the image signal into the memory means. Expand the section to fill the screen. A read clock is generated by a digitally controlled oscillator included in the digitally controlled clock generating means, and a digital oscillation signal of the digitally controlled oscillator is digitally modulated by a parabolic wave signal having a horizontal period to perform expansion processing.

By controlling the read clock of the memory means, the video signal itself is made a signal which is compressed in the central portion of the screen and expanded toward the peripheral portion in the horizontal scanning period. In the horizontal deflection circuit, the normal horizontal linearity correction (S The deflection processing is performed. As a result, the video signal corresponding to the parent screen becomes a signal that is compressed in the central portion of the screen and extends toward the peripheral portion, while the child screen display signal and the on-screen display signal are subjected to normal horizontal linearity correction (S-shaped correction). ), The linearity of the screen display of the sub-screen display portion and the on-screen display portion is maintained, and a high-quality superimpose display can be realized.

Further, since the horizontal linearity correction signal can be digitally controlled, stable operation can be performed even with temperature and power supply voltage fluctuations.

[0021]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a horizontal linearity correction circuit 100 according to an embodiment of the present invention.

In FIG. 1, a luminance signal Y is input to an input terminal 101, and the luminance signal is converted into a digital luminance signal 103 by an A / D converter 102.

The color difference signals (RY) and (BY) are input to the input terminals 104 and 105, respectively, and the multiplex circuit 10
Supplied to 6. The multiplexing circuit 106 outputs the RY signal and the B-
The Y signal is time-division multiplexed and output to the A / D converter 108. The A / D converter 108 converts the color signal 107 output from the multiplexing circuit 106 into a digital signal, and outputs the digital color signal.
Generates 109. Since the color signal has a signal band lower than that of the luminance signal, the color signals are multiplexed before A / D conversion in order to reduce the number of A / D converters having a large circuit scale.

A horizontal synchronizing signal HD synchronized with the horizontal synchronizing portion of the input luminance signal is input to the input terminal 110, and the horizontal synchronizing signal HD is guided to the clock generating circuit 111. The clock generation circuit 111 outputs a horizontal frequency timing signal 150, a clock signal 112 and a clock signal 151, which are integral multiples of the horizontal synchronization frequency, in synchronization with the horizontal synchronization signal HD. In this embodiment, when the horizontal synchronizing frequency is fH,
A frequency of 910 × fH is selected for the clock signal 112 and a frequency of 2730 × fH is selected for the clock signal 151.

The parabolic generator circuit 114 generates a signal 115 of a parabolic wave having a horizontal period, and the digitally controlled oscillator 11
Output to 3. FIG. 2 shows the waveform of the parabolic wave signal. Although the parabolic wave signal 115 is actually a digital signal, it is shown in FIG. 2 as an image converted into an analog signal.

Clock signal 151 and parabolic wave signal 11
5 is led to the digitally controlled oscillator 113. The digitally controlled oscillator 113 operates with the clock signal 151 as a reference clock, and the oscillation frequency is controlled by the parabolic wave signal 115 to generate a digital oscillation output 116.

The digitally controlled oscillator output 116 is a D / A
After being converted into a sine wave analog signal 118 by the converter 117, a rectangular wave clock signal 120 is converted by the waveform shaping circuit 119.
Is converted to. The clock signal 120 is parabolic-modulated such that the frequency is high in the center of the screen and becomes lower toward the periphery in the horizontal cycle.

The timing generation circuit 121 receives the timing signal 150, the clock signal 112 and the clock signal 120 and generates a write timing signal 122 and a read timing signal 123. Write timing signal 122
Is a signal for controlling the writing of the line memory 103, and is generated according to the clock signal 112. The read timing signal 123 is a signal for controlling the read of the line memory 125, and is generated according to the clock signal 120.

The line memory 125 is written by the clock signal 112 by the write timing signal 122, read by the clock signal 120 by the read timing signal 123, and outputs a luminance signal output 126 and a color signal output 127.
Since the frequency of the clock signal 120 is high in the central part of the screen in the horizontal cycle and becomes lower toward the peripheral part, the luminance signal output 126 and the chrominance signal output 127, which are the outputs of the line memory 125, contract in the central part of the screen. , The more it grows toward the periphery.

The D / A converter 131 converts the digital luminance signal output 126 into an analog signal and outputs the analog luminance signal Y.
Is output to the output terminal 132.

The D / A converter 133 converts the color difference signal R-Y in the digital color signal output 127 into an analog signal and outputs the analog color difference signal R-Y to the output terminal 135.

The D / A converter 134 converts the color difference signal BY in the digital color signal output 127 into an analog signal and outputs the analog color difference signal BY to the output terminal 136.

According to the above configuration, the video signal itself is compressed / expanded by using the digital memory 125 without switching the linearity of the deflection system. The clock on the reading side of the memory 125 is digital from the clock on the writing side. It is realized by the control oscillator 113, and the digital control oscillator 113 is digitally modulated by a parabolic signal in the horizontal direction. Parabola modulation can be stably applied to the video signal by digitally controlling the read frequency.

FIG. 3 shows an example of the configuration of the digitally controlled oscillator 113.

In FIG. 3, the digitally controlled oscillator 113
Is composed of an integrating circuit 300 including an adder 301 and a D flip-flop 302, and a sine converting circuit 303.
The integrator circuit 300 operates by using the clock 151 as a clock and outputs the sawtooth wave integrated signal 304, and the period of the integrated output 304 is controlled by the parabolic wave signal 115. The sine conversion circuit 303 converts the integral output 304 of the sawtooth wave into a sine wave signal, and outputs the digitally controlled oscillator output 11
Output as 6.

Since the frequency of the digitally controlled oscillator output 116 changes in proportion to the amplitude value of the parabolic wave signal 115 as a control signal, the frequency is high in the central portion and becomes low as it goes to the peripheral portion.

Compared to an analog voltage controlled oscillator (VCO), the digitally controlled oscillator oscillates stably without fluctuations in oscillation frequency due to fluctuations in ambient temperature or power supply voltage, and has good linearity in frequency changes with respect to control signal signals. The oscillation frequency can be controlled with ideal characteristics.

FIG. 4 shows the above-described horizontal linearity correction circuit 100.
FIG. 21 is a block diagram showing a configuration example in which is applied to a television receiver with a PIP function (that is, a two-screen television receiver).

In FIG. 4, a composite color video signal (a composite color video signal having an aspect ratio of 4: 3) on the main screen side is input to the input terminal 11, and the video / chroma processing circuit 12 is inputted.
And the deflection processing circuit 13. The video / chroma processing circuit 12 performs Y / C separation and color demodulation, and outputs a luminance signal Y and color difference signals RY and BY. Also,
In the deflection processing circuit 13, the horizontal and vertical synchronization signals are separated, and horizontal and vertical deflection sawtooth wave signals are generated to generate a CRT.
It is supplied to the horizontal and vertical deflection yokes 19 of the (cathode ray tube) 20. The CRT 20 has a horizontally long size with an aspect ratio of 16: 9.

The luminance signal Y and the color difference signals RY and BY from the video / chroma processing circuit 12 are the horizontal linearity correction circuit.
At 100, writing / reading control to / from the internal memory is performed by using the writing clock W and the reading clock R, and the peripheral portion is expanded as compared to the central portion of the screen and output as a parent screen signal. It is supplied to the input terminal a of the superposition switch 17. As the horizontal linearity correction circuit 100, a circuit similar to that shown in FIG. 1 is used. The output from the video / chroma processing circuit 12 is passed through the switch 17 to the CRT.
There are three signal lines in the line up to 20, but
For simplicity, only one signal line is shown.

On the other hand, the input terminal 14 is supplied with a composite color video signal on the child screen side (composite color video signal with an aspect ratio of 4: 3) and is supplied to the video / chroma processing circuit 15. In the video / chroma processing circuit 15, Y / C separation and color demodulation are performed, and a luminance signal Y and color difference signals RY, B are obtained.
-Y is output and supplied to the child screen size conversion circuit 16 in the next stage. The small screen size conversion circuit 16 is composed of an A / D converter, a field memory and a D / A converter, and the luminance signal Y and the color difference signals RY and BY from the video / chroma processing circuit 15 are stored in the memory. Writing and reading are performed by using the writing clock W and the reading clock R, and are output as a child screen signal in a state where the time axis is compressed in the horizontal direction and the scanning lines are thinned in the vertical direction. It is supplied to the input terminal b of the parent-child superposition switch 17. Although there are three signal lines from the output of the video / chroma processing circuit 15 to the CRT 20 via the switch 17, only one signal line is shown for simplification.

The parent-child superimposing switch 17 is designed so that its input terminals a and b are switched by a control signal from a control means (not shown). When the PIP display is not performed, the switch 17 is an input terminal. fixedly switched to a,
From the output terminal c, the parent screen signal is passed through the color output circuit 18 to C
It is supplied to the cathode of RT20. When the PIP display is performed, the child screen display period is controlled to be switched to b and the parent screen display period is controlled to be a, and the child screen signal is superimposed on the parent screen signal and output from the output terminal c. Output circuit 18
And is supplied to the cathode of the CRT 20. The color output circuit 18 is a circuit for generating the three primary color signals R, G, B from the luminance signal Y and the color difference signals RY, BY and supplying them to the CRT 20.

In such a circuit, when the PIP display is performed, the signal for the main screen is corrected by the horizontal linearity correction circuit 100 so as to extend it toward the peripheral portion of the screen, as shown in FIG. 5 (c). On the screen having an aspect ratio of 16: 9, the central portion is contracted and the peripheral portion is expanded, and the deflection processing circuit 13 can be displayed in a normal S-shape correction (linearity correction). Since it is doing the signal for the sub-screen (screen size compressed signal)
Is always displayed in a uniform size regardless of where it is superimposed on the screen. Therefore, the inconvenience that the sub-screen display is stretched laterally and unevenly is solved.

In FIG. 4, the case where the child screen is displayed on the parent screen has been described. However, instead of the child screen signal by the child screen size conversion circuit 16 in FIG. 4, the on-screen display circuit turns on. If a screen signal is supplied to the input terminal b of the switch 17 and the switch 17 is selectively switched using an on-screen insertion control signal, the same can be applied to the case of performing on-screen display. .

[0045]

As described above, according to the present invention, when the video signal written in the memory is read out without switching the linearity correction amount (S-shaped correction amount) of the deflection system, the reading frequency is digitally read. By controlling the screen mode, a screen mode that is compressed in the central part of the screen and expanded in the peripheral part is created, so that the circuit element of the deflection system is switched or the frequency is analogized by using a voltage controlled oscillator (VCO). Compared to the case of changing, stable operation can be performed even with temperature and power supply voltage fluctuations, and even if sub-screen display or on-screen display is performed, these displays may stretch horizontally unevenly. It is possible to realize superimpose display with high display quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a horizontal linearity correction circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a digital control signal (parabolic wave signal) used in the embodiment of FIG.

3 is a block diagram showing a configuration of a digitally controlled oscillator used in the embodiment of FIG.

4 is a block diagram showing a main part of a two-screen television receiver configured by using the horizontal linearity correction circuit of the embodiment of FIG.

FIG. 5 is a diagram showing an example of a screen display in each operation mode of the wide TV receiver.

FIG. 6 is a waveform diagram of a horizontal deflection current of a horizontal linearity correction circuit provided in a conventional deflection system.

[Explanation of symbols]

102 ... A / D converter 106 ... Multiplexing circuit 108 ... A / D converter 111 ... Clock generation circuit (first clock generation means) 113 ... Digitally controlled oscillator 114 ... Parabola generation circuit (correction signal generation means) 121 ... Timing Generating circuit 125 ... Line memories (memory means) 113, 117 and 119 ... Digital control clock generating means 131 ... D / A converter 133 ... D / A converter 134 ... D / A converter

Claims (4)

[Claims] 1. A first frequency n times (n is a natural number) a horizontal synchronization frequency in synchronization with a horizontal synchronization signal of an input video signal.
Second clock signal and frequency m times higher (m is a natural number)
And a digital control clock generating means for generating a third clock signal, the oscillation frequency of which is controlled in accordance with the digital control signal using the second clock signal as a reference clock. Correction signal generating means for generating the digital control signal so that the third clock signal has a lower clock in the peripheral portion than in the central portion in the horizontal direction of the screen, and the first clock signal to which the video signal is input Written in and read out by the third clock signal,
A horizontal linearity correction circuit comprising: a memory unit that outputs a video signal whose horizontal linearity is corrected. 2. The horizontal linearity correction circuit according to claim 1, wherein the digital control clock generating means operates with the second clock signal as a reference clock,
An integration circuit that outputs a sawtooth wave signal whose period is controlled by a digital control signal, a sine conversion circuit that converts the sawtooth wave signal from this integration circuit into a sine wave signal, and a sine wave signal from this sine conversion circuit. A D / A converter for converting the analog signal into an analog signal, and a sine wave signal from the D / A converter into a rectangular wave third signal.
And a waveform shaping circuit for converting into a clock signal. 3. The horizontal linearity correction circuit according to claim 1, wherein the correction signal generating means is composed of a parabola generating circuit which generates a parabolic wave signal having a horizontal period as a digital control signal. 4. A first A / D converter for inputting a luminance signal and converting it into a digital luminance signal, and a multiplexing circuit for inputting two color difference signals and time-division multiplexing these signals for output. The second for converting the output of this multiplexing circuit into a digital color signal
A / D converter, and a timing signal having a horizontal synchronizing frequency, a first clock signal having a frequency n times the horizontal synchronizing frequency (n is a natural number) and m in synchronization with the horizontal synchronizing signal of the input luminance signal. A clock generating circuit for generating a second clock signal having a frequency twice (m is a natural number), a parabolic generating circuit for generating a parabolic wave signal having a horizontal period, and the parabolic shape using the second clock signal as a reference clock. A digitally controlled oscillator that generates a digitally oscillated signal whose oscillation frequency is controlled according to the wave signal, a first D / A converter that converts the output of the digitally controlled oscillator into an analog signal, and a first D / A converter A waveform shaping circuit for converting the signal from the A converter into a rectangular clock-shaped third clock signal, and a timing signal and a first clock signal from the clock generation circuit. A timing generation circuit which inputs a third clock signal from the waveform shaping circuit and generates a write timing signal and a read timing signal, a digital luminance signal from the first A / D converter, and the second A / D converter. The digital color signal from the D / D converter is input, the write timing signal is used to write with the first clock signal, the read timing signal is used to read with the third clock signal, and the central portion of the screen is compressed in a horizontal cycle. A line memory that outputs a digital luminance signal and a digital chrominance signal that gradually expands toward the periphery and a digital luminance signal from this line memory are input,
A second D / A converter for converting into an analog luminance signal, and a third D / A converter for inputting the digital color signal from the line memory and converting the first color difference signal in the color signal into an analog color difference signal. An A converter and a fourth D / A converter for inputting a digital color signal from the line memory and converting a second color difference signal in the color signal into an analog color difference signal. Horizontal linearity correction circuit.