KR0147580B1 - 2 picture displaying in the wide television - Google Patents

Abstract

The present invention relates to a two-screen simultaneous viewing circuit in a wide television so that two 4: 3 screens can be simultaneously viewed in a wide television having a 16: 9 aspect ratio.

According to the present invention, a write clock locked to the synchronization signal of the main and sub screens is used for the frame memory of the main screen and the sub screen, and a clock locked to the synchronization signal of the main screen is used as the read clock of the main and sub screens. By synchronizing the sub-screens and changing the read clock described above, the video signal is cut or time-compressed so that two 4: 3 screens can be simultaneously viewed on a wide television having a 16: 9 aspect ratio.

Description

Two-screen simultaneous viewing on wide television

1 is a block diagram of a two-screen simultaneous viewing circuit in a wide television according to the present invention.

2 is an operation timing diagram of each part of FIG.

3 is a state diagram showing an embodiment of a two-screen simultaneous viewing screen according to the present invention.

* Explanation of symbols for main parts of the drawings

100: main screen processing circuit 200: sub screen processing circuit

300: deflection portion 400, 600: PLL portion

500: switching part 700: main / sub switching part

800: matrix 900: CRT

101,201 Tuner 102,202 Synchronous separation and color demodulation

103,203: A / D converter 104,204: frame memory

105,207: D / A converter 205: PIP processor

206: PIP / sub switching unit

The present invention relates to a two-screen simultaneous viewing circuit in a wide television so that two 4: 3 screens can be simultaneously viewed in a wide television having a 16: 9 aspect ratio.

Conventionally, a composite video signal of a 4: 3 screen is displayed on a distorted 16: 9 screen using a memory or a time compressed to a 4: 3 screen, and a picture in picture (PIP, Picture Out Picture; Wide television is implemented as a method of displaying POP).

However, the PIP or POP screen has a disadvantage in that it displays an advertisement before a program of a desired channel is started, rather than watching, and performs only a monitoring role of watching another channel as the main screen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to change the read clock of the frame memory to cut or time-compress an image signal so that two 4: 3 screens have a 16: 9 aspect ratio. It is to provide a two-screen simultaneous viewing circuit in a wide television to enable simultaneous viewing on a wide television.

A feature of the two-screen simultaneous viewing circuit in a wide television according to the present invention for achieving the above object is that in a wide television which is switched to enable simultaneous display of signals of different channels propagated over the air and displayed on a cathode ray tube. A screen simultaneous viewing circuit; After performing synchronization separation and color demodulation by tuning the frequency induced by the antenna, the luminance and color difference signals, which are color demodulated by the write clock locked to the synchronization signal, are stored in a first frame memory, and the read locked to the synchronization signal. Main screen processing means for reading cut, normal, time-compressed luminance and color difference signals from the first frame memory by a clock and a read enable signal; After performing synchronization separation and color demodulation by tuning the frequency induced in the antenna, the luminance and color difference signals, which are color demodulated by the write clock locked to the synchronization signal, are stored in a second frame memory, and synchronization of the main screen processing means is performed. Sub picture processing means for reading a cut, normal, time compressed luminance and color difference signal from the second frame memory by a read clock locked to the signal and a read enable signal; Main oscillating means for oscillating the write and the predetermined read signal locked to the synchronization signal output from the main screen processing means and outputting the write clock of the first frame memory and the read clock of the first and second frame memories; And a write signal locked to the synchronization signal of the sub picture processing means to be output to the second frame memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a two-screen simultaneous viewing circuit in a wide television according to the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a two-screen simultaneous viewing circuit in a wide television according to the present invention.

As a main screen processing circuit 100, a tuner 101 which tunes a high frequency induced by an antenna, converts the frequency into an intermediate frequency, and outputs the synchronization signal by separating a synchronization signal from an intermediate frequency output from the tuner 101. b) a synchronous separation and color demodulator 102 for outputting the luminance signal Y and the color difference signals RY and BY by outputting the color demodulator, and the luminance outputted from the synchronous separation and color demodulator 102; Analog / Digital (hereinafter referred to as A / D) converter 103 for converting a color difference signal into a digital signal, and storing the output of the A / D converter 104 by a write clock. And a D / A converter 105 for converting the digital signal read from the frame memory 105 into an analog signal by a read clock.

200 is a sub picture processing circuit, and the tuner 201, the sync separation and color demodulation unit 202, the A / D converter 203, the frame memory 204, and the D / A converter 207 are the main screens described above. The configuration is the same as that of the processing circuit 100. The PIP / sub-switching unit 206 of the sub picture processing circuit 200 selects the output of the frame memory 204 to output the sub picture or the PIP picture according to the selection signal, or the PIP processing part 205 processes the PIP. The selected signal is configured to be applied to the D / A converter 207.

In addition, 300 is a deflection unit, and the vertical and horizontal deflection currents are generated by the synchronization signals a and b outputted from the synchronous separation and color demodulation unit 102 of the main screen processing circuit 100 to generate the CRT 900. To the deflection coil. 400 is a phase lock loop (hereinafter, referred to as a PLL). A read / write of a frame memory is performed by a synchronous signal output from the synchronous separation and color demodulation unit 102 of the main screen processing circuit 100. The oscillator outputs a clock, and 500 denotes a switching unit, which provides a write clock output from the PLL unit 400 to the frame memory 104 of the main screen processing circuit 100, and reads one of the read clocks. The clock is provided to the frame memory 104 of the main screen processing circuit 100 and the frame memory 204 of the sub screen processing circuit 200.

The oscillator 600 may oscillate by the synchronization signal output from the synchronization and color demodulator 202 of the sub picture processing circuit 200 to provide a write clock to the frame memory 204 of the sub picture processing circuit 200. 700 is a main / sub switching unit, and selects and outputs the outputs of the main screen processing circuit 100 and the sub screen processing circuit 200 by a selection signal e, and 800 is a matrix. The luminance and chrominance signals output from the chrominance are converted into the original color signals R, G, and B and displayed on the CRT 900.

FIG. 2 is an operation timing diagram of each part of FIG. 1, and FIG. 2 (a) is a diagram illustrating the vertical synchronization signal output from the synchronous separation and color demodulator 102 of the main screen processing circuit 100 of FIG. FIG. 2 (b) shows an embodiment of the horizontal synchronization signal outputted from the synchronous separation and color demodulator 102 of the main screen processing circuit 100 of FIG. FIG. 2 (c) shows one embodiment of the read enable signal of the frame memory 104 of the main screen processing circuit 100 of FIG. 1, and FIG. 2 (d) shows the sub-screen processing of FIG. An example of the read enable signal of the frame memory 204 of the circuit 200 is illustrated, and FIG. 2E illustrates an example of the switching signal of the main / sub switch 700.

In this invention configured as described above, the high frequency induced by the antenna of the main screen processing circuit 100 is tuned by the tuner 101 and output to the synchronous separation and color demodulation unit 102 as a composite video signal. The vertical and horizontal synchronization signals a and b as shown in (b), the luminance signal Y, and the color difference signals RY and BY are separated. The luminance signal Y and the color difference signals R-Y and B-Y are converted into an 8-bit x 3 digital signal by the A / D converter 103 and input to the frame memory 104.

The vertical and horizontal synchronization signals a and b are provided to the deflection unit 300 to generate vertical and horizontal deflection currents and provide the vertical and horizontal deflection coils of the CRT 900. In addition, the vertical and horizontal synchronization signals a and b are provided to the PLL unit 400, and the PLL unit 400 oscillates a read / write clock locked to the vertical and horizontal synchronization signals.

At this time, the clock output from the i stage of the PLL unit 400 is a subcarrier frequency of 4Fsc and is provided to the write clock stage W of the frame memory 104. Where Fsc is the 3.58 MHz subcarrier frequency. Therefore, the frame memory 104 stores the output of the A / D converter 103 by the write clock.

On the other hand, the clock output from the j stage of the PLL unit 400 is 3/4 times 4Fsc, the clock output from the k stage is 8Fsc. The i, j, and k clocks are provided to the read clock R of the frame memories 104 and 204 through the switching unit 500. In this case, the frame memory 104 reads data provided from the frame memory 104 according to the read clock provided by the switching unit 500, outputs the data provided to the D / A converter 105, and converts the D / A. The unit 105 converts the output of the frame memory 104 into an analog signal and outputs the analog signal to the main / sub switching unit 700.

On the other hand, the PLL unit 600 oscillating by the synchronization signal output from the synchronous separation and color demodulation unit 202 of the sub picture processing circuit 200 provides a write clock of 4Fsc to the frame memory 1204 of the sub picture. The luminance (Y) and the color difference signals (RY, BY) output from the synchronous separation and color demodulator 202 are converted into 8-bit x 3 digital signals by the A / D converter 203, and then the frame memory 204 Is stored in the frame memory 204 in accordance with the write clock.

The output of the frame memory 204 is provided to the PIP / sub-switching unit 206 after PIP processing by the PIP processing unit 205. In this case, the PIP / sub-switching unit 206 selects the output of the PIP processing unit 205 when the read clock of the frame memory 204 provided by the switching unit 500 is 4 fsc, and 4 (4/3) Fsc. 8 Fsc, the output of the frame memory 204 is selected and output to the D / A converter 207. The D / A converter 207 converts the output of the PIP / sub-switcher 206 into an analog signal. After the output to the main / sub switching unit 700.

In addition, the output of the D / A converters 105 and 207 is selected and output to the matrix 800 by the switching signal e provided to the main / sub switching unit 700, and the original color signal in the matrix 800. Separated by (R, G, B) and output to the CRT (900).

At this time, when the write clock of the frame memories 104 and 204 is 4Fsc and the read clock is 4Fsc, the screen of the wide television is displayed as shown in FIG. 3A, and the remaining space is displayed on the PIP or POP screen.

The write clock is 4 Fsc and the read clock is 4 (4/3) Fsc. The read enable signal of the frame memory 104 is the same as in FIG. 2C, and the read enable signal of the frame memory 204 is zero. As shown in FIG. 2 (d), the switching signal of the main / sub switching unit 700 is shown in FIG. 2 (e), and the left and right upper and lower screens are cut (g portion of FIG. 2) as shown in FIG. do. If the read clock is 8 Fsc, the output of the frame memories 104 and 204 is time compressed and displayed as shown in FIG. In this case, the read enable signal of the frame memories 104 and 204 and the switching signal of the main / sub switching unit 700 are generated by a memory controller (not shown) by the main horizontal synchronization signal of the main screen processing circuit 100.

As described above, according to the two-screen simultaneous viewing circuit in the wide television according to the present invention, the write clock locked to the synchronization signal of the main and sub screens is used for the frame memory of the main screen and the sub screen, and the synchronization signal of the main screen is used. By using the clock locked on the main and sub screens as the read clock, the synchronization between the main and sub screens is synchronized, and the read signals are changed to cut or time-compress the video signal so that two 4: 3 screens can be 16: 9. There is an effect of enabling simultaneous viewing on a wide television having an aspect ratio of.

Claims (1)

A two-screen simultaneous viewing circuit in a wide television that simultaneously displays first and second video signals having an aspect ratio of 4: 3 on the left and right sides of a 16: 9 wide screen, wherein the first and second video signals are digitally converted. First and second analog-to-digital converters for outputting the control unit; First and second frame memories respectively storing first and second image signals digitally converted by the first and second analog-to-digital converters; The first and second image signals digitally converted by the first and second analog-to-digital converters are controlled to be recorded at a recording frequency when they are written to the first and second frame memories, respectively. A memory control unit for controlling reproduction at a frequency of at least 4/3 times and twice the recording frequency; First and second digital-to-analog converters for analog-converting and outputting first and second image signals read out from the first and second frame memories; And a main / sub switching unit which sequentially selects and outputs the outputs of the first and second digital-to-analog converters.