JPH07162702A - Left-right pincushion distortion correction circuit - Google Patents

Abstract

PURPOSE:To provide a left-right pincushion correction circuit unnecessitating an adjustment even when the size of the display screen of a television receiver, etc., is changed. CONSTITUTION:The first pulse synchronized with a horizontal synchronizing signal is generated in a frequency synthesizer 2, the video signal data corresponding to one horizontal scanning period is written in a video signal data memory 1 based on a first pulse, the data for first correction corresponding to the one horizontal scanning period is read from a data memory 3 for correction based on the first pulse, the data for second correction corresponding to left-right pincushion distortion for every scanning line is read from a correction data memory 6 based on the number of the scanning line in a field which is counted in a counter 5, the read first and second correction data is multiplied after the data is converted into analog signals, the pulse of the frequency based on the multiplication output is generated by a frequency synthesizer 15, the video signal data is read from the video signal memory 1 based on the pulse and a displayed image is generated by the video signal based on the read video signal data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a left and right pincushion distortion correction circuit used in a television receiver and a liquid crystal projector, and more specifically, a left and right pincushion distortion is corrected by expanding a video signal in accordance with the left and right pincushion distortion. Left and right pincushion distortion correction circuit.

[0002]

2. Description of the Related Art As shown in FIG. 9, a conventional bobbin distortion correction circuit has transistors Q11, Q12 and Q13, a diode modulator circuit 20 to which a midpoint voltage of a vertical deflection circuit is supplied, and a vertical synchronization signal. By generating a parabolic waveform voltage having the same period as the collector of the transistor Q13, modulating the collector output of the horizontal output transistor Q10 with the parabolic waveform voltage, and applying the modulated output to the horizontal deflection yoke Y. The horizontal deflection current flowing in is corrected to a parabola amplitude-modulated waveform within one cycle of the vertical synchronizing signal. In FIG. 9, D indicates a damper diode.

The midpoint voltage of the vertical deflection circuit supplied to the diode modulator circuit 20 has the waveform shown in FIG. 10 (a), and the parabolic waveform voltage output from the collector of the transistor Q13 has the waveform shown in FIG. 10 (b). The waveform of the voltage applied to the horizontal deflection yoke Y is the waveform shown in FIG. 10C, and the waveform of the horizontal deflection current flowing in the horizontal deflection yoke Y is the waveform shown in FIG. 10D. The horizontal direction of the image expands in the center portion of the screen, and the left and right pincushion distortion is corrected.

[0004]

The conventional correction of the left and right pincushion distortion is a method of superposing the correction current on the horizontal deflection current using a diode modulator circuit or the like, and the correction is made in the deflection circuit system. However, when the above-mentioned conventional left and right pincushion distortion correction circuit is used, each fixed constant such as the resistance value of the resistor in the diode modulator circuit or the electrostatic capacitance of the capacitor is based on the size of the display screen of the television receiver or the like. There was a problem that it had to be reviewed, changed, and adjusted.

It is an object of the present invention to provide a left and right pincushion distortion correction circuit that does not need to be adjusted even when the size of the display screen of a television receiver or the like is changed.

[0006]

The left and right pincushion distortion correction circuit of the present invention comprises a first pulse generating means for generating a first pulse synchronized with a horizontal synchronizing signal separated from a video signal, and one horizontal scanning period. Video signal data memory in which minute video signal data is sequentially written based on the first pulse,
A second pulse generating means for generating a second pulse whose cycle is sequentially expanded and contracted for each scanning line corresponding to the left and right pincushion distortion, and is stored in the video signal data memory based on the second pulse. It is characterized in that the video signal data is read.

In the left and right pincushion distortion correction circuit of the present invention, the second pulse generating means stores the first correction data for one horizontal scanning period consisting of the same correction data, and the data is the first correction data. A first correction data memory that is sequentially read based on one pulse, and a first D / A converter that converts the first correction data read from the first correction data memory into an analog signal A counter for counting the number of scanning lines in one field, and second correction data corresponding to the left and right pincushion distortion for each scanning line are stored and addressed by the count value of the counter. Second correction data memory from which the second correction data is read, and a second D / A converter for converting the second correction data read from the second correction data memory into an analog signal , A multiplier for multiplying the outputs of the first and second D / A converters, and pulse generating means for generating a pulse having a frequency based on the output of the multiplier as a second pulse. .

In the left and right pincushion distortion correction circuit of the present invention, the read pulse generating means uses the added output obtained by adding the output of the loop filter and the output of the multiplier as the oscillation frequency control voltage of the voltage controlled oscillator and synchronizes with the horizontal synchronizing signal. It is characterized by comprising a frequency synthesizer for generating the pulse.

[0009]

The left and right pincushion distortion correction circuit of the present invention sequentially writes the video signal data for one horizontal scanning period in the video signal data memory based on the first pulse synchronized with the horizontal synchronizing signal separated from the video signal. Be done. On the other hand, the second pulse generating means generates a second pulse whose cycle is sequentially expanded and contracted for each scanning line corresponding to the left and right pincushion distortion, and is stored in the video signal data memory based on the second pulse. The video signal data is read. In this case,
Since the cycle of the read pulse from the video signal data memory is expanded or contracted for each scanning line based on the left and right pincushion distortion, the video signal based on the video signal data read from the video signal data memory is based on the left and right pincushion distortion. Since the left and right pincushion distortion is corrected, the display image becomes an image without the left and right pincushion distortion.

[0010]

EXAMPLES The present invention will be described below with reference to examples. Figure 1
FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention.

In this embodiment, the horizontal synchronizing signal separated from the video signal is supplied to the PLL frequency synthesizer 2, and a clock having a frequency of 4 fsc (fsc is the frequency of the color subcarrier) synchronized with the horizontal synchronizing signal by the PLL frequency synthesizer 2. Generate a pulse. The clock pulse output from the PLL frequency synthesizer 2 is supplied to the video signal data memory 1 as a write address clock (WCK), and the video signal data converted into a digital signal is set to 1 based on the write address clock (WCK).
The video signal data for the horizontal scanning period is sequentially written in the video signal data memory 1.

Therefore, the video signal data is written in the video signal data memory 1 at a constant speed. Here, the video signal data memory 1 has a storage capacity for storing video signal data for one horizontal scanning period.

On the other hand, reference numeral 3 is a correction data memory in which correction data for one horizontal scanning period for expanding the image in the horizontal direction of the screen is stored. The clock pulse of the frequency 4fsc generated by the PLL frequency synthesizer 2 is supplied to the correction data memory 3 as a read address clock, and the correction data stored in the correction data memory 3 is read based on the read address clock. The correction data read from the correction data memory 3 is supplied to the D / A converter 4 and converted into an analog signal. The correction data memory 3 is read according to the waveform read from the correction data memory 3 and converted into an analog signal.
The correction data stored in FIG.
As shown in (a), it is linear.

Therefore, the correction data is read from the correction data memory 3 at a constant speed based on the frequency of 4 fsc, converted into an analog signal of a constant level, and output from the D / A converter 4. It 2 (b) is shown in FIG.
A part of the video signal for showing the timing with (a) is schematically shown. The correction data memory 3 is shown as ROM A in FIG.

Reference numeral 6 is a correction data memory in which correction data for one field period for determining the vertical position on the screen for expanding the image is stored. If the correction data stored in the correction data memory 6 is schematically shown by the waveform read from the correction data memory 6 and converted into an analog signal, it is as shown by the solid line in FIG. The shape corresponds to the left and right pincushion distortion in order to correct the short portion of the raster near the center in the vertical direction. The correction data memory 6 is shown as ROM B in FIG.

The horizontal synchronizing signal separated from the video signal is supplied to the scanning line counter 5 which is reset by the vertical synchronizing signal, and the scanning line counter 5 counts the number of scanning lines in one field period. The count value of the scanning line counter 5 is supplied to the correction memory 6 as a read address, and the correction data stored in the correction memory 6 is read based on the read address clock.

The data read from the correction memory 6 is supplied to the D / A converter 7 and converted into an analog signal. D
The analog signal output from the / A converter 7 is supplied to the phase shifter 8 to match the phase with the output from the D / A converter 4.

The phase shifter 8 is, for example, as shown in FIG. 4, a first phase shifter for delaying a phase (90 ° ± 30 °) consisting of a transistor Q1, a resistor R1 including a variable resistor, and a capacitor C1. A phase circuit, a second phase shift circuit for (90 °) phase advance composed of a transistor Q2, a resistor R2, and a capacitor C2 for shifting the output from the first phase shift circuit; And an emitter follower composed of a transistor Q3 for receiving the output from the phase shift circuit. The phase of the output of the D / A converter 7 is adjusted to ± 30 by adjusting the resistance value of the resistor R1.
The phase of the output from the phase shifter 8 is D /
The phase of the output from the A converter 4 is matched.

The output from the D / A converter 4 and the output from the D / A converter 7 whose phase has been adjusted by the phase shifter 8 are supplied to a multiplier 9 for multiplication. The multiplier 9 is, for example, as shown in FIG.
As shown in (a), the output of the D / A converter 4 and the phase shifter 8
Field-effect transistor Q4 that multiplies the output of the field effect transistor Q4 and an inverting amplifier P that amplifies the product output of the field-effect transistor Q4.
It consists of and. The multiplication output from the multiplier 9 is shown in FIG.
The waveform has an envelope as shown in (b). This envelope is similar to the parabolic waveform in the 1V period of the waveform shown in FIG. The multiplication output from the multiplier 9 is applied to the variable resistor 10 to divide the voltage.

On the other hand, the horizontal synchronizing signal separated from the video signal is supplied to the PLL frequency synthesizer 15, and the PLL frequency synthesizer 15 generates a clock pulse having a frequency of 4 fsc synchronized with the horizontal synchronizing signal. PLL
The frequency synthesizer 15 includes a phase comparison circuit 11, a loop filter 12 that smoothes a phase comparison output from the phase comparator 11, an output of the loop filter 12, and a variable resistor 1.
An adder 13 for adding the divided output by 0, and an adder 1
Voltage controlled oscillator 14 whose output is frequency controlled voltage 14
And a frequency divider (not shown) that divides the output frequency of the voltage controlled oscillator 14 and supplies the frequency-divided output to the phase comparison circuit 11, so that the output of the frequency divider and the horizontal synchronization signal are phase-compared. Configured. Here, the voltage controlled oscillator 14 is 4f
It oscillates at the free-running oscillation frequency of sc, and the oscillation frequency decreases as the frequency control voltage decreases.

Therefore, the oscillation frequency from the voltage controlled oscillator 14 is a frequency frequency-modulated by the divided voltage output from the variable resistor 10. The output from the voltage controlled oscillator 14 is supplied to the video signal data memory 1 as a read address clock for reading the video signal data,
The video signal data written in the video signal data memory 1 is sequentially read as corrected video signal data from the video signal data memory 1 based on the oscillation frequency of the voltage controlled oscillator 14.

As described above, the frequency of the signal output from the PLL frequency synthesizer 15, that is, the oscillation frequency of the voltage controlled oscillator 14 is frequency-modulated by the output from the variable resistor 10, and is displayed from the top of the display screen. The reading speed of the video signal data from the video signal data memory 1 up to almost the central portion of the screen in the vertical direction is gradually decreased for each horizontal scanning line, and the reading speed from the central portion of the display screen to the maximum of the display screen is increased. The reading speed of the video signal data from the video signal data memory 1 to the lower portion is sequentially increased for each horizontal scanning line.
The analog video signal obtained by converting the video signal data read from the device by an A / D converter (not shown) is corrected so as to have the most swollen image at the portions corresponding to the 131 and 132 scanning lines.

Therefore, in the case where there is no pincushion distortion, the display image becomes a barrel-like shape which bulges almost at the center in the vertical direction in one field as shown in FIG. 6 (a). As a result, when an image based on the video signal data read from the video signal data memory 1 is displayed by a television receiver including a picture tube having left and right pincushion distortion shown in FIG. As shown in (c), the image has a corrected left and right pincushion distortion. Therefore, regardless of the size of the picture tube of the television receiver, the left and right pincushion distortion can be corrected without correction. If the output level of the adder 9 is adjusted by the variable resistor 10,
The correction amount of the left and right pincushion distortion is adjusted.

In the above-mentioned embodiment, the correction data stored in the correction data memory 6 becomes the maximum level in the center line instead of the correction data schematically shown by the solid line in FIG. Is reduced to be the minimum on the first line and the 262 or 263th line, the correction data is schematically shown by a two-dot chain line in FIG. 3, and the oscillation frequency of the voltage controlled oscillator 14 is increased by the frequency control voltage. In the case where the oscillation frequency is reduced in accordance with the above, the same operation is performed. In this case, unlike the case of FIG. 5B, the multiplication output shown in FIG. It can be easily understood that the waveform has a bulged envelope, the read clock is delayed in the center line portion as in the case of the above-described embodiment, and the left and right pincushion distortion is corrected.

Next, another embodiment of the present invention will be described. FIG. 7 shows a liquid crystal projector of a full-face projection type to which another embodiment of the present invention is applied.

When an image is projected on the screen 18 in a state where the liquid crystal projector 17 of the full-face projection type is tilted,
In the screen 18 of FIG. 7, trapezoidal left and right pincushion distortions as shown by the diagonal lines occur. In the case of correcting the left and right pincushion distortion by applying the present invention in such a case, if the data stored in the correction data memory 6 is schematically shown by a waveform converted into an analog signal, as shown in FIG.
As shown in (a). Reference numeral e in FIG.
Corresponds to the upper part of the screen, and the symbol f corresponds to the lower part of the screen.

The data schematically shown in FIG. 8A is read out, converted into an analog signal, the phase is adjusted by the phase shifter 8, and the data in the correction data memory 3 converted into the analog signal is multiplied. The multiplication output in the device 9 is shown in FIG.
, And its envelope corresponds to the left and right distortion on the screen 18. Reference numeral g in FIG.
Corresponds to the upper part of the screen, and the symbol h corresponds to the lower part of the screen.

Therefore, in this case, the read address clock for reading the video signal data from the video signal data memory 1 is gradually delayed from the first scanning line on the screen to the last scanning line on the screen,
The image spreads in the horizontal direction as it goes to the bottom of the screen with respect to the top of the screen, and the displayed image becomes rectangular and the left and right pincushion distortion is corrected.

[0029]

As described above, according to the left and right pincushion distortion correction circuit of the present invention. Based on the first pulse synchronized with the horizontal synchronizing signal separated from the video signal, the video signal data for one horizontal scanning period is sequentially written in the video signal data memory, and the second pulse generating means copes with the left and right pincushion distortion. The second cycle in which the cycle is expanded and contracted for each scanning line
Pulse is generated and the video signal data stored in the video signal data memory is read based on the second pulse. Therefore, the video signal read from the video signal data memory and based on the video signal data causes left and right pincushion distortion. On the basis of the expansion and contraction for each scanning line, the display image has an effect of correcting left and right pincushion distortion.

Further, according to the left and right pincushion distortion correction circuit of the present invention, the video signal is expanded and contracted for each scanning line based on the left and right pincushion distortion, and when the size of the display screen of the television receiver or the like is changed. However, since the left and right pincushion distortion has already been corrected in the video signal, there is an effect that no special adjustment is necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a left and right pincushion distortion correction circuit according to the present invention.

FIG. 2 is a waveform diagram schematically showing stored contents of a correction data memory (ROM A) in one embodiment of the present invention.

FIG. 3 is a waveform diagram schematically showing stored contents of a correction data memory (ROM B) in one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a phase shifter according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a multiplier in one embodiment of the present invention and a waveform diagram of an output of the multiplier.

FIG. 6 is a schematic diagram for explaining the operation of one embodiment of the present invention.

FIG. 7 is an external view showing a full-face projection type liquid crystal projector to which another embodiment of the left and right pincushion distortion correction circuit according to the present invention is applied.

FIG. 8 is a waveform diagram and a multiplication output waveform diagram schematically showing the stored contents of a correction data memory according to another embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional left and right pincushion distortion correction circuit.

10 is a waveform diagram for explaining the operation of the conventional left and right pincushion distortion correction circuit shown in FIG.

[Explanation of symbols]

 1 Video signal data memory 2 and 15 PLL frequency synthesizer 3 and 6 Correction data memory 4 and 7 D / A converter 5 Scan line counter 8 Phase shifter 9 Multiplier 11 Phase comparator 12 Loop filter 13 Adder 14 Voltage control Oscillator

Claims (3)

[Claims] 1. A first pulse generating means for generating a first pulse synchronized with a horizontal synchronizing signal separated from a video signal, and video signal data for one horizontal scanning period are sequentially based on the first pulse. Video signal data memory to be written,
A second pulse generating means for generating a second pulse whose cycle is sequentially expanded and contracted for each scanning line corresponding to the left and right pincushion distortion, and is stored in the video signal data memory based on the second pulse. A left and right pincushion distortion correction circuit characterized by reading out image signal data. 2. The left and right pincushion distortion correction circuit according to claim 1, wherein the second pulse generation means stores the first correction data for one horizontal scanning period, which is composed of the same correction data. A first correction data memory in which the data is sequentially read out based on a first pulse, and a first D for converting the first correction data read out from the first correction data memory into an analog signal. A / A converter, a counter for counting the number of scanning lines in one field, second correction data corresponding to left and right pincushion distortion for each scanning line, and addressing by the count value of the counter. A second correction data memory from which the second correction data is read out, and a second D / A for converting the second correction data read from the second correction data memory into an analog signal A converter, a multiplier that multiplies the outputs of the first and second D / A converters, and a read pulse generation unit that generates a pulse having a frequency based on the output of the multiplier as the second pulse. Left and right pincushion distortion correction circuit. 3. The left and right pincushion distortion correction circuit according to claim 2, wherein the read pulse generation means uses the addition output obtained by adding the output of the loop filter and the output of the multiplier as the oscillation frequency control voltage of the voltage controlled oscillator. A left and right pincushion distortion correction circuit comprising a frequency synthesizer that generates a pulse synchronized with a synchronization signal.