JP2822469B2 - TV receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a television receiver.

[Summary of the Invention]

According to the present invention, in a television receiver, an image with excellent image quality is obtained by controlling the time axis of a video signal using a line memory.

[Conventional technology]

The display screen of a color television receiver (including a CRT display device without a tuner circuit) generally has a screen shown in FIG.
As shown in Fig. B, the horizontal deflection current Ih is amplitude-modulated by a parabolic wave having a vertical period (shown by a broken line) to correct the display screen to have a correct rectangular shape, as shown in Fig. B. You are.

In such a method of amplitude-modulating the horizontal deflection current Ih in a parabolic manner, the power supply voltage of the horizontal deflection circuit is changed in a parabolic manner.

A saturable reactor is connected in series to the horizontal deflection coil, and its inductance is changed in a parabolic manner.

A method called a diode modulator. and so on.

[Problems to be solved by the invention]

However, in any of the above methods, electric power is handled. When the size of the television receiver is large, the power of the deflection circuit itself is increased.

Therefore, in a large television receiver,
If the method (1) is adopted, the power consumption increases, and the scale, cost, reliability, and the like of the circuit and components are burdened.

In the television receiver, various horizontal deflection distortions occur in addition to the left and right pincushion distortions.

The present invention seeks to solve these problems.

[Means for solving the problem]

According to the present invention, the line signal of the video signal is alternately written, and the increment and decrement of the address of the write and read address signals supplied to each are set so that the direction of the time axis is non-inverted and inverted, respectively. First and second line memories from which line signals are alternately read, a clock generator for generating a clock synchronized with a synchronization signal related to a video signal, and a first memory based on a horizontal synchronization signal related to a video signal. And the second
A deflection circuit for forming a substantially sinusoidal horizontal deflection signal having a phase corresponding to the time axis direction of a line signal alternately read from the line memories, and write addresses supplied to the first and second line memories, respectively. One of the address signal and the read address signal is formed based on a clock from a clock generator, and the other address signal is modulated according to the horizontal deflection distortion of the horizontal deflection signal from the deflection circuit. An address signal forming circuit formed based on the modulated signal obtained as described above, and a video signal composed of line signals alternately read from the first and second line memories are supplied, and the horizontal signal from the deflection circuit is supplied. And a picture tube provided with deflection means for performing horizontal deflection by a deflection signal.

[Action]

According to the present invention, the first and second line memories include:
While the line signals of the video signal are written alternately,
By setting the increment and decrement of the address of the write and read address signals supplied to each of them, line signals whose time axis directions are non-inverted and inverted are alternately read. A clock generator generates a clock synchronized with a synchronization signal related to the video signal. The deflection circuit is configured to output a substantially sinusoidal horizontal deflection signal having a phase corresponding to the time axis direction of the line signal alternately read from the first and second line memories based on a horizontal synchronization signal related to the video signal. To form An address signal forming circuit forms one of a write address signal and a read address signal to be supplied to the first and second line memories based on a clock from a clock generator, and forms the other address signal. Is formed based on the modulated signal obtained by modulating the clock in accordance with the horizontal deflection distortion of the horizontal deflection signal from the deflection circuit. A video signal comprising a line signal alternately read from the first and second line memories is supplied to the picture tube, and the picture tube is provided with a deflection means for performing horizontal deflection by a horizontal deflection signal from a deflection circuit. It has.

〔Example〕

In FIG. 1, (1) shows a tuner circuit including a high-frequency amplifier to a video detection circuit, and a video signal (luminance signal) Sy is extracted from the tuner circuit (1). Then, the signal Sy is supplied to an A / D converter (2) and converted into a digital signal Sy.
D / through a signal line of a switch circuit (3) to be described later → line memory (4A) or (4B) → switch circuit (5)
The signal is supplied to an A converter (6) and converted into an analog signal Sy, and this signal Sy is supplied to a picture tube (8) through a video amplifier (7).

Further, a signal Sy from the tuner circuit (1) is supplied to a synchronization separation circuit (11) to extract a vertical synchronization pulse Pv and a horizontal synchronization pulse Ph, and these pulses Pv and Ph are supplied to a formation circuit (12). As shown in FIG. 2A, in an odd-numbered horizontal period Ta of one frame period, it becomes “1”,
In the even-numbered horizontal period Tb, a signal Ss that becomes “0” is formed, and this signal Ss is supplied to the switch circuits (3) and (5) as their control signals, and the switch circuits (3) and (5)
In (5), as shown in the figure, the polarities are switched to each other every one horizontal period.

Further, the pulse Ph is supplied to the PLL (13) to form a clock CK synchronized with the pulse Ph at a predetermined frequency, and this clock CK and the signal Ss are sent to the write signal forming circuit (14) having a counter. Supplied with this forming circuit (14)
In FIG. 2, as shown in FIG. 2B, every horizontal scanning period, starting from “0” at the start time, the clock CK
Each time, a write address signal Sw that is incremented by “1” is formed, and a write clock WRCK is formed. And these signals Sw and WRCK are
As shown in FIG. E, the data is supplied to the memory (4A) every period Ta, and as shown in FIG. F, it is supplied to the memory (4B) every period Tb.

In FIGS. E to H, the right-pointing arrow indicates the increment of the address, and the left-pointing arrow indicates the decrement of the address.

Further, a clock CK is supplied to a read signal forming circuit (16) through a PPM modulation circuit (15), which will be described later, and a signal Ss is supplied to a forming circuit (16). As shown in C, at each horizontal scanning period, starting from “0” at the start time,
A first read address signal Sa that is incremented by "1" every CK is formed, and a read clock RDCK is formed. These signals Sa and RDCK are generated during a period Tb as shown in FIG. Is supplied to the memory (4A).

Furthermore, in the forming circuit (14), as shown in FIG. D, the second starting from the “maximum value” at the start of each horizontal scanning period and decrementing by “1” every clock CK. The read address signal Sb is formed, and a read clock RDCK is formed. These signals Sb and RDCK are supplied to the memory (4B) during a period Ta as shown in FIG. Note that the values indicated by these signals Sa and Sb change linearly when no conversion is performed.

Further, pulses Pv and Ph are supplied to the deflection circuit (21),
A horizontal deflection signal (current) Sh as shown in FIG. 9G, that is, a horizontal deflection having a substantially sinusoidal waveform and a half frequency of the horizontal frequency, and a phase that changes from a minimum value to a maximum value during a period Tb. A signal Sh is formed, and this signal Sh is supplied to the horizontal deflection coil (22) of the picture tube (8).

In the deflection circuit (21), a vertical deflection signal Sv is formed, and this signal Sv is supplied to the vertical deflection coil (23). Note that this signal Sv changes in a sawtooth shape in the vertical cycle as a whole, but in the vertical scanning period, the level changes in a staircase waveform every horizontal period.

Further, a correction signal Sc having a waveform corresponding to the left and right pincushion distortion and various horizontal deflection distortions is taken out from the deflection circuit (21) in a horizontal cycle, and this signal Sc is sent to a modulation circuit (15) as a modulation signal. Supplied and formed circuits (16)
Is modulated according to the signal Sc, that is, according to the horizontal deflection position.

According to such a configuration, the signal Sy for accessing the memory (4A) is written to the memory (4A) in the period Ta in the increment direction of the address during the period Ta, as shown in FIG. Since the memory (4A) is read out from the memory (4A) in the increment direction of the address at Tb, that is, since the memory (4A) operates as a FIFO memory, the read signal Sy is, as shown in FIG. It is supplied to the converter (6) without changing the direction of the time axis.

However, as shown in FIG. 2F, the signal Sy for accessing the memory (4B) is written in the memory (4B) in the direction of increment of the address in the period Tb, and then the signal is read in the next period Ta.
Is read from the memory (4B) in the decrement direction of the address, that is, the memory (4B)
Since it operates as a memory, the read signal Sy is supplied to the converter (6) with its time axis direction inverted as shown in FIG. 2H.

Then, such signals Sy, Sy are applied to the circuits (6) and (7).
The horizontal deflection signal Sh supplied to the picture tube (8) at this time and supplied to the deflection coil (22) at this time.
Changes in the decreasing direction during the period Ta and changes in the increasing direction during the period Tb, as shown in FIG. 2G.
On the screen, an image is displayed with pixels arranged in a correct direction in any horizontal scanning line.

In this case, the read address signals Sa and Sb supplied to the memories (4A) and (4B) are PPM-modulated by the correction signals Sc corresponding to the left and right pincushion distortions and various horizontal deflection distortions. The time axis of the signal Sy read from the memories (4A) and (4B) is complementary to the right and left pincushion distortions and various horizontal deflection distortions. On the screen (8), an image in which left and right pincushion distortions and various horizontal deflection distortions are corrected is displayed.

Thus, according to the present invention, the time axis of the video signal Sy supplied to the picture tube (8) is changed in accordance with the left and right pincushion distortion and various horizontal deflection distortions. Can display no images.

In addition, since the left and right pincushion distortion and various horizontal deflection distortions are corrected by changing the time axis of the video signal Sy, highly accurate correction can be performed, and a large amount of electric power is required as in the above methods (1) to (4). No need to handle,
There is no burden on the scale, cost, reliability, etc. of circuits and components.

Furthermore, since the horizontal deflection is performed by the substantially sinusoidal signal Sh, various types of horizontal deflection distortion in the displayed image are basically reduced, and therefore the correction is simplified.

As shown in FIG. 2, when the horizontal deflection signal Sh is sinusoidal, the time axis of the video signal Sy needs to be inverted every other horizontal period. Since the memories (4A) and (4B) for correcting the horizontal deflection distortion are simultaneously performed, the memories (4A) and (4B) and their peripheral circuits can be simplified and the cost can be reduced.

Note that when the left and right pincushion distortions or horizontal deflection distortions are asymmetric on the left and right sides of the screen, the clocks CK may be separately PPM-modulated to obtain the signals Sa and Sb.

Also, the write address signals for the memories (4A) and (4B)
The clock CK serving as Sw may be PPM-modulated, and the clock CK serving as the read signals Sa and Sb may be non-modulated. Alternatively, the write address signal Sw of the memory (4A) or (4B) may be changed in the decrement direction, and the read address signal Sa may be changed in the increment direction.

〔The invention's effect〕

According to the television receiver of the present invention, the line signal of the video signal is alternately written, and the increment and decrement of the address of the supplied write and read address signals are set, so that the directions of the time axes are respectively set. First and second line memories from which non-inverted and inverted line signals are alternately read, a clock generator for generating a clock synchronized with a synchronization signal related to a video signal, and a horizontal synchronization signal related to a video signal. A deflection circuit that forms a substantially sinusoidal horizontal deflection signal having a phase corresponding to the time axis direction of the line signal alternately read from the first and second line memories based on the first and second line memories;
And one of the write address signal and the read address signal supplied to the second line memory is formed based on the clock from the clock generator, and the other address signal is generated by the clock from the deflection circuit. A video comprising an address signal forming circuit formed based on a modulated signal obtained by modulating the horizontal deflection signal according to the horizontal deflection distortion, and a line signal alternately read from the first and second line memories. Since there is provided a picture tube provided with a deflecting means for supplying a signal and performing horizontal deflection by a horizontal deflection signal from a deflection circuit, the following effects are obtained.

The first and second line memories and one of the write address signal and the read address signal supplied to the first and second line memories, respectively, are formed based on a clock from a clock generator, and the other is formed. Video signal supplied to a picture tube by an address signal forming circuit for forming an address signal based on a modulated signal obtained by modulating a clock according to a horizontal deflection distortion of a horizontal deflection signal from a deflection circuit. Is changed in accordance with the horizontal deflection distortion, so that an image without horizontal deflection distortion can be displayed on the picture tube, and highly accurate horizontal deflection distortion correction is possible. It is not necessary to handle a large amount of power as in the case of the method (1), and no burden is imposed on the scale, cost, reliability, etc. of the circuit and components.

Further, since the horizontal deflection is performed using a substantially sinusoidal horizontal deflection signal, various horizontal deflection distortions in the displayed image are basically reduced, and therefore, the correction is simplified.

Further, in order to perform horizontal deflection using a substantially sinusoidal horizontal deflection signal, first and second line memories and addresses as means for inverting the direction of the time axis of each line signal of the video signal every other line. Since the signal forming circuit is also used as a means for correcting horizontal deflection distortion, the configuration of the television receiver is simplified, and the number of parts is reduced.

[Brief description of the drawings]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explanation thereof. (4A) and (4B) are line memories, (8) is a picture tube, (1
4) and (15) are address signal forming circuits, (15) is a PPM modulation circuit, and (21) is a deflection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 3/30 H04N 3/23

Claims (1)

(57) [Claims] A line signal of a video signal is alternately written, and increments and decrements of addresses of write and read address signals supplied thereto are set separately, so that a direction of a time axis is non-inverted and inverted, respectively. 1 and 2 in which the read line signals are alternately read out.
A line generator, a clock generator for generating a clock synchronized with a synchronizing signal related to the video signal, and a horizontal synchronizing signal related to the video signal, alternately from the first and second line memories. A deflection circuit for forming a substantially sinusoidal horizontal deflection signal having a phase corresponding to the time axis direction of the read line signal; the write address signal supplied to the first and second line memories; One of the address signals is formed based on a clock from the clock generator, and the other address signal is modulated according to the horizontal deflection distortion of the horizontal deflection signal from the deflection circuit. An address signal forming circuit formed based on the modulated signal obtained from the first and second line memories. A video signal composed of mutually read line signals is supplied,
And a picture tube provided with a deflecting means for performing horizontal deflection by a horizontal deflection signal from the deflection circuit.