JPH0832056A - Field-effect transistor - Google Patents

Field-effect transistor

Info

Publication number
JPH0832056A
JPH0832056A JP16680394A JP16680394A JPH0832056A JP H0832056 A JPH0832056 A JP H0832056A JP 16680394 A JP16680394 A JP 16680394A JP 16680394 A JP16680394 A JP 16680394A JP H0832056 A JPH0832056 A JP H0832056A
Authority
JP
Japan
Prior art keywords
gate electrode
insulating film
gate
protective insulating
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16680394A
Other languages
Japanese (ja)
Inventor
Toshiya Shimura
俊哉 志村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16680394A priority Critical patent/JPH0832056A/en
Publication of JPH0832056A publication Critical patent/JPH0832056A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To provide a field-effect transistor having a reduced total gate capacitance. CONSTITUTION:A protective insulating film 5 comprising fluorine resin (FEP) is formed as if covering a gate electrode 3 on a silicon substrate 1 whereon the gate electrode 3 is formed. The specific conductivity of a gate insulating film 2 comprising silicon oxide is 3.8-3.9 but that of the fluororesin comprising the protective insulating film 5 is 1.9-2.2 that is lower than the former.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、MOSFETなどの
MOS構造を有する電界効果型の半導体装置に関し、特
に、微細化,高速動作のためにゲート総容量を低減した
電界効果型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device having a MOS structure such as MOSFET, and more particularly to a field effect semiconductor device having a reduced total gate capacitance for miniaturization and high speed operation.

【0002】[0002]

【従来の技術】MOSFETに代表される電界効果型半
導体装置では、例えばシリコン基板上に酸化膜を介して
ゲート電極を形成した構造を有している。このような電
界効果型半導体装置においては、ゲート電極上にはこれ
を覆うように保護絶縁膜が形成され、ゲート電極とその
上に形成する電極との絶縁のためや、ゲート電極の保護
のために用いられる。
2. Description of the Related Art A field effect semiconductor device represented by a MOSFET has a structure in which a gate electrode is formed on a silicon substrate with an oxide film interposed therebetween. In such a field effect type semiconductor device, a protective insulating film is formed on the gate electrode so as to cover the gate electrode, for insulation between the gate electrode and an electrode formed thereon and for protection of the gate electrode. Used for.

【0003】図2は、このようなMOS構造を有する電
界効果トランジスタの構成を示す断面図である。同図に
おいて、1はシリコン基板、2はシリコン基板1表面を
酸化することで形成されたゲート絶縁膜、3はゲート絶
縁膜2上に形成されたゲート電極、4はゲート電極3を
マスクにすることなどによりゲート電極3両わきのシリ
コン基板1表面に不純物を導入することで自己整合的に
形成されたソース・ドレイン領域、5aはゲート電極3
を覆うように基板1上に形成されたシリコン酸化膜、6
はゲート電極3による配線段差を低減させるための平坦
化膜である。
FIG. 2 is a sectional view showing the structure of a field effect transistor having such a MOS structure. In FIG. 1, 1 is a silicon substrate, 2 is a gate insulating film formed by oxidizing the surface of the silicon substrate 1, 3 is a gate electrode formed on the gate insulating film 2, and 4 is a gate electrode 3 as a mask. The source / drain regions 5a formed in a self-aligned manner by introducing impurities into the surface of the silicon substrate 1 on both sides of the gate electrode 3 are gate electrodes 3
A silicon oxide film formed on the substrate 1 so as to cover the
Is a flattening film for reducing the wiring step due to the gate electrode 3.

【0004】ところで、現在、上述したような電界効果
トランジスタの微細化が進められている。電界効果トラ
ンジスタが用いられる集積回路の集積度を上げようとす
ると、上述したゲート電極3の幅(ゲート長)を小さく
していかなくてはならない。そして、この短チャネル化
にともないゲート長を小さくしたことによって、その抵
抗を下げるためにゲート電極3の膜厚を厚く形成する必
要がある。現在では、ゲート長wが0.2〜1.0μ
m、ゲート厚hが0.3〜0.7μm、そしてゲート絶
縁膜2の厚さtが9〜30nm程度となっている(図
2)。
By the way, miniaturization of the above-mentioned field effect transistor is currently underway. In order to increase the degree of integration of the integrated circuit in which the field effect transistor is used, it is necessary to reduce the width (gate length) of the gate electrode 3 described above. By reducing the gate length in accordance with the shortening of the channel, it is necessary to increase the film thickness of the gate electrode 3 in order to reduce the resistance thereof. Currently, the gate length w is 0.2 to 1.0 μ
m, the gate thickness h is 0.3 to 0.7 μm, and the thickness t of the gate insulating film 2 is about 9 to 30 nm (FIG. 2).

【0005】[0005]

【発明が解決しようとする課題】従来は、以上のように
構成されていたので、短チャネル化にともないゲート電
極3が厚くなることで、ゲート電極3側面とソース・ド
レイン領域4との結合容量がますます増大し、ゲート総
容量を増大させているという問題があった。一定電位で
帯電したゲート電極3に関して、ゲート電極3−ゲート
絶縁膜2−シリコン基板1(半導体基板)で構成される
寄生容量とともに、ゲート電極3側面−シリコン酸化膜
5a(保護絶縁膜)−ソース・ドレイン領域4で構成さ
れる寄生容量が存在する。
Conventionally, since the gate electrode 3 is configured as described above, the thickness of the gate electrode 3 becomes thicker as the channel becomes shorter, so that the coupling capacitance between the side surface of the gate electrode 3 and the source / drain region 4 is increased. However, there is a problem that the total gate capacitance is increasing more and more. Regarding the gate electrode 3 charged at a constant potential, the gate electrode 3 side surface-the silicon oxide film 5a (protective insulating film) -source together with the parasitic capacitance formed by the gate electrode 3-gate insulating film 2-silicon substrate 1 (semiconductor substrate) -There is a parasitic capacitance composed of the drain region 4.

【0006】そして、ゲート電極3側面とシリコン酸化
膜5aとの接合面や、シリコン酸化膜5aとソース・ド
レイン領域4との接合面においても、それぞれ静電誘導
による電荷が生じる。これらは接合面積の増大、すなわ
ちゲート電極3が厚くなることにともない増加してい
く。前述したように、ゲート電極3の厚さとゲート絶縁
膜2の厚さの比は、約30:1となり、ゲート電極3側
面からソース・ドレイン領域4方向に生じる電界は無視
できない。
Electric charges are also generated by electrostatic induction at the joint surface between the side surface of the gate electrode 3 and the silicon oxide film 5a and the joint surface between the silicon oxide film 5a and the source / drain region 4. These increase as the junction area increases, that is, as the gate electrode 3 becomes thicker. As described above, the ratio of the thickness of the gate electrode 3 to the thickness of the gate insulating film 2 is about 30: 1, and the electric field generated from the side surface of the gate electrode 3 toward the source / drain region 4 cannot be ignored.

【0007】この発明は、以上のような問題点を解消す
るためになされたものであり、電界効果型半導体装置に
おけるゲート電極のゲート総容量を低減することを目的
とする。
The present invention has been made to solve the above problems, and an object thereof is to reduce the total gate capacitance of the gate electrode in a field effect semiconductor device.

【0008】[0008]

【課題を解決するための手段】この発明の電界効果型半
導体装置は、ゲート電極の少なくとも側面を覆うように
形成された保護絶縁膜を有し、その保護絶縁膜が誘電率
の低い材料から構成されていることを特徴とする。ま
た、その保護絶縁膜がゲート電極を覆うように形成され
ていることを特徴とする。また、低い誘電率を得るため
に、保護絶縁膜がフッ素またはその化合物を含む材料か
ら構成されていることを特徴とする。そして、その化合
物がフッ素樹脂から構成されていることを特徴とする。
A field effect semiconductor device according to the present invention has a protective insulating film formed so as to cover at least a side surface of a gate electrode, and the protective insulating film is made of a material having a low dielectric constant. It is characterized by being. The protective insulating film is formed so as to cover the gate electrode. Further, in order to obtain a low dielectric constant, the protective insulating film is characterized by being made of a material containing fluorine or its compound. The compound is characterized by being composed of a fluororesin.

【0009】[0009]

【作用】ゲート電極側面と保護絶縁膜との間の結合容量
が小さくなる。
Function The coupling capacitance between the side surface of the gate electrode and the protective insulating film is reduced.

【0010】[0010]

【実施例】以下この発明の1実施例を図を参照して説明
する。図1は、この発明における1実施例であるMOS
型トランジスタの構成を示す断面図である。同図におい
て、5はゲート電極3が形成されたシリコン基板1上に
ゲート電極3を覆うように形成されたフッ素樹脂(FE
P)からなる保護絶縁膜であり、他は図2と同様であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOS according to an embodiment of the present invention.
It is sectional drawing which shows the structure of a type transistor. In the figure, 5 is a fluororesin (FE) formed so as to cover the gate electrode 3 on the silicon substrate 1 on which the gate electrode 3 is formed.
P) is a protective insulating film and is otherwise similar to FIG.

【0011】酸化シリコンから構成されるゲート絶縁膜
2の比誘電率は3.8〜3.9であるが、保護絶縁膜5
を構成するフッ素樹脂は比誘電率が1.9〜2.2と低
い。このため、この実施例によれば、保護絶縁膜にシリ
コン酸化膜を用いた場合に比較して、ゲート電極3と保
護絶縁膜5との間の結合容量を小さくできるので、ゲー
ト総容量を低減することができる。
The relative dielectric constant of the gate insulating film 2 made of silicon oxide is 3.8 to 3.9, but the protective insulating film 5
The fluororesin constituting the above has a low relative dielectric constant of 1.9 to 2.2. Therefore, according to this embodiment, the coupling capacitance between the gate electrode 3 and the protective insulating film 5 can be reduced as compared with the case where the silicon oxide film is used as the protective insulating film, and thus the total gate capacitance is reduced. can do.

【0012】なお、上記実施例では、ゲート絶縁膜2を
酸化シリコンで構成するようにしたが、これに限るもの
ではなく、たとえば窒化シリコンであっても良い。ま
た、上記実施例では、シリコン基板上に形成されたMO
S型トランジスタについて説明したが、これに限るもの
ではない。たとえば、接合型の電界効果トランジスタや
ショットキー接合を用いた電界効果トランジスタであっ
ても良く、同様の効果を奏する。
Although the gate insulating film 2 is made of silicon oxide in the above embodiment, the present invention is not limited to this, and may be silicon nitride, for example. Further, in the above embodiment, the MO formed on the silicon substrate
Although the S-type transistor has been described, the present invention is not limited to this. For example, a junction field effect transistor or a field effect transistor using a Schottky junction may be used, and the same effect can be obtained.

【0013】[0013]

【発明の効果】以上説明したように、この発明によれ
ば、フッ素樹脂を用いることなどにより、保護絶縁膜の
誘電率をゲート絶縁膜などに用いるシリコン酸化膜より
小さくした。このため、ゲート電極側面からの電界によ
るソース・ドレイン領域それぞれとの結合容量の増加に
よるゲート容量を抑制し、ゲート総容量を抑制できると
いう効果があり、電界効果型半導体装置の高速動作を可
能とする。
As described above, according to the present invention, the dielectric constant of the protective insulating film is made smaller than that of the silicon oxide film used for the gate insulating film or the like by using the fluororesin. Therefore, there is an effect that the gate capacitance due to the increase of the coupling capacitance with each of the source / drain regions due to the electric field from the side surface of the gate electrode can be suppressed, and the total gate capacitance can be suppressed. To do.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明における1実施例であるMOS型ト
ランジスタの構成を示す断面図である。
FIG. 1 is a cross-sectional view showing the structure of a MOS transistor which is an embodiment of the present invention.

【図2】 MOS構造を有する電界効果トランジスタの
構成を示す断面図である。
FIG. 2 is a cross-sectional view showing a configuration of a field effect transistor having a MOS structure.

【符号の説明】[Explanation of symbols]

1…シリコン基板、2…ゲート絶縁膜、3…ゲート電
極、4…ソース・ドレイン領域、5…保護絶縁膜、6…
平坦化膜。
1 ... Silicon substrate, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... Source / drain region, 5 ... Protective insulating film, 6 ...
Planarization film.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ゲート電極を備えた電界効果型の半導体
装置において、 前記ゲート電極の少なくとも側面を覆うように形成され
た保護絶縁膜を有し、 前記保護絶縁膜が誘電率の低い材料から構成されている
ことを特徴とする電界効果型半導体装置。
1. A field effect semiconductor device having a gate electrode, comprising a protective insulating film formed so as to cover at least a side surface of the gate electrode, the protective insulating film being made of a material having a low dielectric constant. A field-effect semiconductor device characterized by being provided.
【請求項2】 請求項1記載の電界効果型半導体装置に
おいて、 前記保護絶縁膜が前記ゲート電極を覆うように形成され
ていることを特徴とする電界効果型半導体装置。
2. The field effect semiconductor device according to claim 1, wherein the protective insulating film is formed so as to cover the gate electrode.
【請求項3】 請求項1または2記載の電界効果型半導
体装置において、 前記材料がフッ素またはその化合物を含むことを特徴と
する電界効果型半導体装置。
3. The field effect semiconductor device according to claim 1, wherein the material contains fluorine or a compound thereof.
【請求項4】 請求項3記載の電界効果型半導体装置に
おいて、 前記化合物がフッ素樹脂から構成されていることを特徴
とする電界効果型半導体装置。
4. The field effect semiconductor device according to claim 3, wherein the compound is composed of a fluororesin.
JP16680394A 1994-07-19 1994-07-19 Field-effect transistor Pending JPH0832056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16680394A JPH0832056A (en) 1994-07-19 1994-07-19 Field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16680394A JPH0832056A (en) 1994-07-19 1994-07-19 Field-effect transistor

Publications (1)

Publication Number Publication Date
JPH0832056A true JPH0832056A (en) 1996-02-02

Family

ID=15837977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16680394A Pending JPH0832056A (en) 1994-07-19 1994-07-19 Field-effect transistor

Country Status (1)

Country Link
JP (1) JPH0832056A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670711B2 (en) 2001-11-15 2003-12-30 Renesas Technology Corp. Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677209A (en) * 1992-08-28 1994-03-18 Fujitsu Ltd Manufacture of fluororesin
JPH0794642A (en) * 1993-07-27 1995-04-07 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677209A (en) * 1992-08-28 1994-03-18 Fujitsu Ltd Manufacture of fluororesin
JPH0794642A (en) * 1993-07-27 1995-04-07 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670711B2 (en) 2001-11-15 2003-12-30 Renesas Technology Corp. Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode

Similar Documents

Publication Publication Date Title
US10418480B2 (en) Semiconductor device capable of high-voltage operation
US5894156A (en) Semiconductor device having a high breakdown voltage isolation region
US10396166B2 (en) Semiconductor device capable of high-voltage operation
US10879389B2 (en) Semiconductor device capable of high-voltage operation
JP2003152178A (en) Lateral power mosfet for high switching speed
US5895246A (en) Method of making semiconductor device with air gap between the gate electrode and substrate during processing
GB2292480A (en) Protection MOSFET
US6972463B2 (en) Multi-finger transistor
US5293512A (en) Semiconductor device having a groove type isolation region
JP2676888B2 (en) Semiconductor device
JPH0832056A (en) Field-effect transistor
JP3402043B2 (en) Field effect transistor
US5181094A (en) Complementary semiconductor device having improved device isolating region
JPS6262069B2 (en)
JPH0222868A (en) Insulated-gate field-effect transistor
JP3217484B2 (en) High voltage semiconductor device
JP3074064B2 (en) Lateral MOS field effect transistor
US20060255374A1 (en) Manufacturing process and structure of power junction field effect transistor
JPH0456469B2 (en)
JPH11220124A (en) Semiconductor device
JP3280699B2 (en) Field effect transistor and method of manufacturing the same
JP3361382B2 (en) Transistor
JPH0252469A (en) Semiconductor device and its manufacture
JPH0846138A (en) Semiconductor integrated circuit device
JPH0388338A (en) Semiconductor device