JPH0846138A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device in which the heat dissipation effect is enhanced. CONSTITUTION:A thin film SOI layer 3 is provided through a silicon oxide 2 deposited on a single crystal silicon substrare 1 thus forming a semiconductor integrated circuit 7 including a MOSFET 6 made of the thin film SOI layer 3. A thin film SOI layer 10 is then provided, as a protective resistor, through the silicon oxide 2 deposited on the single crystal substrate 1. The thin film SOIL layer 10 is connected, at one end thereof, with a bonding pad 9 and, at the other end thereof, with the semiconductor integrated circuit 7. A low resistance polysilicon layer 12 is provided through a silicon oxide 11 made of same material as the gate oxide of the MOSFET 6 with same thick therewith for the thin film SOI layer 10 and a metal layer 13 is provided on the surface side of the single crystal silicon substrate 1 while being coupled thermally with the low resistance polysilicon layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to SOI (Silicon On Insul).
attor or Semiconductor On
The present invention relates to a semiconductor integrated circuit device that employs an insulator structure and that includes a protective resistor that protects the semiconductor integrated circuit from static electricity and the like.

[0002]

2. Description of the Related Art In the past, as semiconductor devices have been speeded up and highly integrated, a single crystal silicon layer (SOI) on an insulator has been developed.
Research on MOSFETs formed in layers) is being conducted. In particular, when the thickness of the SOI layer is smaller than the maximum depletion layer width of the channel region of the MOSFET and the SOI layer is completely depleted when the channel is formed, the short channel effect compared to the MOSFET formed on the bulk silicon substrate. Can be suppressed or the vertical electric field in the channel can be relaxed so that the effective mobility can be improved.
It is known that since a PN junction formed in a thin SOI layer having a thickness of μm or less exists only in the horizontal cross section of the SOI layer, it has excellent characteristics such as high-speed operation with low floating capacitance.

By the way, in a semiconductor integrated circuit device, an element (particularly a MOS, in particular, which constitutes the semiconductor integrated circuit is usually subjected to a high voltage (excess current) such as static electricity or surge voltage.
In order to prevent the gate oxide film of the FET) from being destroyed, an electrostatic breakdown resistant element is required in the input pad section, and a protective resistor is generally used for this type of element to adjust the excess current amount. Has been.

When this protective resistor is a polysilicon layer on an insulating film or is formed on a thin film SOI layer, the periphery of the protective resistor is covered with an insulator having poor heat conduction, so that the heat radiation is poor. There is a problem that the allowable power loss decreases.

To solve this problem, Japanese Patent Laid-Open No. 63-
There is a method disclosed in Japanese Patent No. 90846. this is,
As shown in FIGS. 16 and 17, a metal layer 33 is provided on the upper layer of the polysilicon resistor 31 with the insulating layer 32 sandwiched therebetween to improve heat dissipation.

[0006]

However, the insulating layer 32
The film thickness of the insulating layer 32 cannot be reduced due to the process restriction that is an interlayer insulating film between the wiring and the element portion (normally 50
There is a problem that a very large heat dissipation effect cannot be obtained.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of improving the heat radiation effect.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit including a MOSFET formed in a semiconductor layer via an insulating layer on a semiconductor substrate, an external connection terminal and the semiconductor integrated circuit. In a semiconductor integrated circuit device, which is provided between the protection resistor and a protection resistor provided via an insulating layer on the semiconductor substrate, and the protection resistor is made of the same material as the gate oxide film of the MOSFET. A semiconductor integrated circuit device in which a conductor layer is arranged through an insulator having the same thickness and a metal layer which is thermally connected to the conductor layer is arranged on the surface side of the semiconductor substrate. .

According to a second aspect of the present invention, the protective resistor according to the first aspect of the present invention comprises a semiconductor layer on the semiconductor substrate via an insulating layer, and the conductive layer is the gate of the MOSFET. The gist of the semiconductor integrated circuit device is the same material as the electrodes, and a conductor layer is arranged on the protective resistor via the insulator.

According to a third aspect of the present invention, the protective resistor in the first aspect of the invention is made of the same material as the gate electrode of the MOSFET, and the conductor layer is an insulator layer on the semiconductor substrate. The gist of the invention is a semiconductor integrated circuit device which is formed of a semiconductor layer with a conductive layer interposed under the protective resistor with the insulator interposed therebetween.

A fourth aspect of the invention is based on a semiconductor integrated circuit device in which the conductor layer in the first aspect of the invention is in the same potential as the protective resistor or in a floating state.

[0012]

According to the first, second and third aspects of the present invention, when a high voltage is applied to the external connection terminal, the protective resistor converts the electric power into heat energy. The heat is transmitted to the conductor layer through the thin insulator, is further transmitted to the metal layer through the conductor layer having high thermal conductivity, and is dissipated in this metal layer. In this way, since the insulator is thin, the heat dissipation effect is improved.

According to the invention of claim 4, claim 1
In addition to the function of the invention described in (1), since the conductor layer is at the same potential as the protective resistor or in a floating state, it is difficult to apply a high voltage to the thin insulator in contact with the protective resistor. Even if the body is destroyed, the protective function of the protective resistor can be maintained.

[0014]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of the present semiconductor integrated circuit device, and FIG. 1B is a sectional view taken along the line AA of FIG. 1A. A buried silicon oxide film 2 as an insulator layer is formed on a single crystal silicon substrate 1 as a semiconductor substrate. On the embedded silicon oxide film 2,
Thin single crystal silicon layer as a semiconductor layer (hereinafter, thin film S
The OI layer 3) is arranged. A polysilicon gate electrode 5 is formed on the thin film SOI layer 3 via a silicon oxide film 4 as a gate oxide film to form a MOSFET 6. This MOSFET 6 is a semiconductor integrated circuit 7
Is part of.

An interlayer insulating film 8 made of a BPSG film is formed in a predetermined region on the buried silicon oxide film 2, and a bonding pad 9 as an external connection terminal is formed on the interlayer insulating film 8. ing. The bonding pad 9 is made of Al (aluminum).

On the buried silicon oxide film 2,
A thin single crystal silicon layer (hereinafter referred to as a thin film SOI layer) 10 as a semiconductor resistor and a protective resistor doped with N-type or P-type impurities is arranged. This thin film S
The OI layer 10 has a strip shape and extends in a meandering manner. One end of the thin film SOI layer 10 has the semiconductor integrated circuit 7
And the other end is connected to the bonding pad 9. A low resistance polysilicon layer 12 as a conductor layer is arranged on the thin film SOI layer 10 with a thin silicon oxide film 11 of about 10 nm as an insulator interposed therebetween.

Here, the silicon oxide film 11 is formed by the above-mentioned MO.
It has the same material and the same film thickness as the silicon oxide film 4 as the gate oxide film of the SFET 6. The low resistance polysilicon layer 12 is made of the same material as the polysilicon gate electrode 5 of the MOSFET 6.

The low resistance polysilicon layer 12 has a rectangular shape. Further, on the low resistance polysilicon layer 12, A
A metal layer 13 made of l (aluminum) is arranged, and the metal layer 13 has a rectangular shape and has a low resistance polysilicon layer 12.
It has almost the same size as. Thus, the metal layer 13 is arranged on the front surface side of the single crystal silicon substrate 1 in a state of being thermally connected to the low resistance polysilicon layer 12. The low resistance polysilicon layer 12 is in a floating state.

Next, a method of manufacturing the present semiconductor integrated circuit device will be described with reference to FIGS. First, as shown in FIG. 2, a buried silicon oxide film 2 is formed on a single crystal silicon substrate 1, and a thin single crystal silicon layer (thin film SOI layer) is formed thereon, and, for example, a LOCOS method or the like is used. Then, the thin film SOI layers 3 and 10 are arranged in the protective resistor forming region Z1 and the MOSFET forming region Z2 by element isolation. Then, silicon oxide films 4 and 11 having a film thickness of about 10 nm are simultaneously formed on the thin SOI layers 3 and 10.

Then, as shown in FIG.
After masking the formation region Z2 with the resist 14, for example,
Phosphorus (P ⁺ ), arsenic (As ⁺ ), boron (B ⁺ ) ions, etc. are ion-implanted to form the thin film SO in the protective resistor forming region Z1.
The resistance of the I layer 10 is reduced.

Further, as shown in FIG. 4, a polysilicon layer is deposited by the LPCVD method, and the resistance of the polysilicon layer is lowered by, for example, phosphorus deposition, and then the polysilicon layer is patterned in a desired region. as a result,
Polysilicon gate electrode 5 and low resistance polysilicon layer 12
Is arranged.

Continuing, as shown in FIG.
After masking the formation region Z1 with the resist 15, the MOSF is formed.
When the N-channel type is used as ET6, for example, phosphorus
(P ⁺), Arsenic (As⁺) As P as MOSFET 6
When the channel type is used, for example, boron (B⁺), B
F₂ ⁺Is self-aligned with the polysilicon gate electrode 5.
Source / drain regions 16 are formed by ion implantation with in
To do.

Further, as shown in FIG. 6, an interlayer insulating film 8 made of a BPSG film is deposited by the plasma CVD method. Then, as shown in FIG. 1B, the contact hole 17 and the protective resistor opening 1 are formed in the interlayer insulating film 8.
8 is formed by etching. After that, a metal film made of aluminum is deposited, and the metal film is patterned into a predetermined region to form the bonding pad 9, the metal layer 13, and the wiring 19.

Next, the operation of the semiconductor integrated circuit device thus constructed will be described. When a high voltage is applied to the bonding pad 9 due to static electricity or surge voltage, the thin film SOI layer 10 as a protective resistor converts electric power into heat energy to protect the semiconductor integrated circuit 7. At this time, the thin film SO
The heat generated in the I layer 10 is transferred to the low resistance polysilicon layer 12 side through the silicon oxide film 11. At this time,
When the insulating layer 32 (silicon oxide film) which is the interlayer insulating film shown in Nos. 6 and 17 is used, the film thickness of the silicon oxide film is 500 nm.
In this apparatus, the film thickness of the silicon oxide film 11 is about 10 nm, which is as thin as 1/10 or less, so that the heat dissipation effect is improved. Further, the thin film SOI layer 10
The heat generated in 1 is transmitted to the metal layer 13 through the low resistance polysilicon layer 12 having a good thermal conductivity through the silicon oxide film 11, and is dissipated in the metal layer 13.

As described above, the heat generated in the thin SOI layer 10 is applied to the silicon oxide film 11 and the low resistance polysilicon layer 1.
It is transmitted to the metal layer 13 through 2 and can be efficiently transmitted to the metal layer 13. Therefore, the thin film SOI layer 10
The temperature rise can be suppressed, and thermal destruction can be suppressed.

Therefore, the allowable power loss is improved and a high electrostatic breakdown voltage can be achieved without increasing the area of the protective resistor. As described above, in this embodiment, the MOS formed on the thin film SOI layer 3 (semiconductor layer) via the silicon oxide film 2 (insulator layer) on the single crystal silicon substrate 1 (semiconductor substrate).
The semiconductor integrated circuit 7 including the FET 6, the thin film SOI layer 10 provided between the bonding pad 9 (external connection terminal) and the semiconductor integrated circuit 7 and arranged via the silicon oxide film 2 on the single crystal silicon substrate 1. In a semiconductor integrated circuit device including a (protective resistor), a low resistance poly-silicon film is formed on the thin film SOI layer 10 via a silicon oxide film 11 (insulator) made of the same material and the same film thickness as the gate oxide film of the MOSFET 6. A silicon layer 12 (conductor layer) is arranged, and a metal layer 13 which is thermally connected to the low resistance polysilicon layer 12 is arranged on the front surface side of the single crystal silicon substrate 1. More specifically, the protective resistor is composed of the thin film SOI layer 10 with the silicon oxide film 2 on the single crystal silicon substrate 1, and the low resistance polysilicon layer 12 (conductor layer) is composed of the same material as the gate electrode of the MOSFET 6. A low resistance polysilicon layer 12 was arranged on the thin film SOI layer 10 (protective resistor) with a silicon oxide film 11 (insulator) interposed therebetween.

Therefore, when a high voltage is applied to the bonding pad 9, the thin film SOI layer 10 generates heat, and the heat is transferred through the thin silicon oxide film 11 to the low resistance polysilicon layer 1.
2 is further transmitted to the metal layer 13 through the low resistance polysilicon layer 12 having a high thermal conductivity, and is diffused in the metal layer 13. In this way, the silicon oxide film 11
Since the film thickness is thin, the heat dissipation effect is improved.

Further, in this embodiment, the thin film SOI layer 10 (protective resistor) is thermally connected to the metal layer 13 via the low resistance polysilicon layer 12 thereabove, so that, for example, for wiring. Even in the portion where the metal layer 13 cannot be arranged,
The heat dissipation can be improved by extending the low-resistance polysilicon layer 12 to the place where the metal layer 13 can be arranged.

Further, since the low resistance polysilicon layer 12 (conductor layer) is in a floating state, a high voltage is applied to the thin silicon oxide film 11 (insulator) which is in contact with the thin SOI layer 10 (protective resistor). Is difficult to be applied, and even if this thin silicon oxide film 11 is broken, the thin film S
The protection function of the OI layer 10 can be maintained.

As another mode of this embodiment, the following may be carried out. In the above embodiment, the low resistance polysilicon layer 12
Although (and the metal layer 13) is in a floating state, as shown in FIGS. 7A and 7B, by connecting the metal layer 13 to the bonding pad 9, the low resistance polysilicon layer 12 is thinned. The potential may be the same as that of the SOI layer 10 (protective resistor). By doing so, it is difficult to apply a high voltage to the thin silicon oxide film 11 that is in contact with the thin SOI layer 10.
The protective function of the thin film SOI layer 10 can be maintained even when the thin film is broken. Further, since the heat generated in the thin film SOI layer 10 can be transferred to the bonding pad 9 and diffused, the allowable power capacity can be further improved.

Further, in FIGS. 1A and 1B, the thin film SOI is
Although the layers 3 and 10 are embedded in the silicon oxide film 2, as shown in FIGS. 8A and 8B, the thin film S is formed.
The OI layers 3 and 10 may be separated by mesa and formed on the silicon oxide film 2.

Further, as shown in FIGS. 9A and 9B, the low resistance polysilicon layer 12 and the metal layer 13 on the protective resistor (thin film SOI layer 10) may be divided into small areas. . That is, as shown in FIG. 9A, the low-resistance polysilicon layer 12 and the metal layer 13 are formed by, for example, 12a and 13a.
"11" is divided into 12k and 13k. Figure 1 (a),
In the structure shown in (b), the protective resistor (thin film SOI
When the potential difference between the protective resistor (thin film SOI layer 10) and the low resistance polysilicon layer 12 at both ends of the layer 10) becomes larger than the withstand voltage of the silicon oxide film 11, the silicon oxide film 11 is destroyed and the current is reduced to the low resistance polysilicon layer. It may flow to the silicon layer 12 and the original resistance value may not be secured. On the other hand, in the structure shown in FIGS. 9A and 9B, since the low resistance polysilicon layer 12 is divided into small areas, the low resistance polysilicon layer 12 is formed at both ends of one island. A large potential difference is less likely to occur between 12 and the protective resistor (thin film SOI layer 10), and the original resistance is easily secured.

Further, instead of the low resistance polysilicon layer 12, for example, a material whose resistance is reduced by silicide such as W (tungsten), Ti (titanium), or W is used.
A single element such as (tungsten) or Ti (titanium) may be used. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.

FIG. 10A is a plan view of this semiconductor integrated circuit device, and FIG. 10B is a sectional view taken along line EE of FIG. 10A. A buried silicon oxide film 2 is formed on the single crystal silicon substrate 1, and a thin film SOI layer 3 is arranged on the buried silicon oxide film 2. Thin film S
A polysilicon gate electrode 5 is formed on the OI layer 3 as a gate oxide film via a silicon oxide film 4 to form a MOSFE.
T6 is formed, and this MOSFET 6 forms a part of the semiconductor integrated circuit 7. Also, the embedded silicon oxide film 2
The interlayer insulating film 8 made of BPSG film
Is formed, and a bonding pad 9 made of Al (aluminum) is formed on the interlayer insulating film 8.

On the buried silicon oxide film 2,
A thin conductive single crystal silicon layer (hereinafter referred to as a low resistance thin film SOI layer) 20 serving as a semiconductor layer and a conductor layer having a low resistance doped with N-type or P-type impurities is arranged. The low resistance thin film SOI layer 20 is formed in a rectangular shape. Further, on the low resistance thin film SOI layer 20,
Thin silicon oxide film 21 of about 10 nm as an insulator
A polysilicon layer 22 serving as a protective resistor is arranged via. The polysilicon layer 22 has a strip shape, and
It is meandering and extended. One end of the polysilicon layer 22 is connected to the semiconductor integrated circuit 7 and the other end is connected to the bonding pad 9.

Here, the silicon oxide film 21 is formed by the above-mentioned MO.
It has the same material and the same film thickness as the silicon oxide film 4 as the gate oxide film of the SFET 6. The polysilicon layer 22 is made of the same material as the polysilicon gate electrode 5 of the MOSFET 6.

A metal layer 23 made of aluminum is formed on the polysilicon layer 22 with the interlayer insulating film 8 interposed therebetween. The metal layer 23 has a rectangular shape and has a low resistance thin film S.
It has substantially the same size as the OI layer 20. Also, the metal layer 23
Is connected to the low resistance thin film SOI layer 20 through a contact hole 24 formed in the interlayer insulating film 8. Thus, the metal layer 23 is arranged on the front surface side of the single crystal silicon substrate 1 in a state of being thermally connected to the low resistance thin film SOI layer 20. The low resistance thin film SOI layer 20 is in a floating state.

Next, a method of manufacturing the present semiconductor integrated circuit device will be described with reference to FIGS. First, as shown in FIG. 11, a buried silicon oxide film 2 is formed on a single crystal silicon substrate 1, and a thin single crystal silicon layer (thin film SOI layer) is formed thereon, and, for example, LOCO.
Using the S method or the like, the protective resistor forming region Z1 and the MOSFE are formed.
The thin film SOI layers 3 and 20 are arranged in the T formation region Z2 by element isolation. Then, 10n is formed on the thin film SOI layers 3 and 20.
The silicon oxide films 4 and 21 having a film thickness of about m are simultaneously formed.

Then, as shown in FIG.
After masking the T formation region Z2 with the resist 25, for example, phosphorus (P ⁺ ), arsenic (As ⁺ ), boron (B ⁺ ) ions, etc. are ion-implanted to lower the thin film SOI layer in the protective resistor formation region Z1. The resistance is changed (the low resistance thin film SOI layer 20 is formed).

Further, as shown in FIG. 13, a polysilicon layer is deposited by the LPCVD method, the resistance of the polysilicon layer is lowered by, for example, phosphorus deposition, and then the polysilicon layer is patterned in a desired region. as a result,
A polysilicon gate electrode 5 and a polysilicon layer 22 are arranged.

Subsequently, as shown in FIG. 14, after masking the protective resistor forming region Z1 with the resist 26, the MOS is formed.
When making the FET 6 an N-channel type, for example, phosphorus (P ⁺ ) and arsenic (As ⁺ ) are made when making the MOSFET 6 a P-channel type, for example, boron (B ⁺ ),
BF ₂ ⁺ is ion-implanted into the polysilicon gate electrode 5 by self-alignment to form the source / drain regions 16.

Further, as shown in FIG. 15, an interlayer insulating film 8 made of a BPSG film is deposited by the plasma CVD method. Then, as shown in FIG. 10B, contact holes 17 and 24 are formed in the interlayer insulating film 8 by etching. After that, a metal film made of aluminum is deposited, and the metal film is patterned into a predetermined region to form the bonding pad 9, the metal layer 23, and the wiring 19.

Next, the operation of the semiconductor integrated circuit device thus constructed will be described. When a high voltage is applied to the bonding pad 9 due to static electricity or surge voltage, the polysilicon layer 22 as a protective resistor converts electric power into heat energy to protect the semiconductor integrated circuit 7. At this time, the heat generated in the polysilicon layer 22 is transferred to the low resistance thin film SOI layer 20 side through the silicon oxide film 21. At this time, if the insulating layer 32 (silicon oxide film) which is the interlayer insulating film shown in FIGS. 16 and 17 is used, the film thickness of the silicon oxide film is 500 n.
Although it is about m, in this device, the film thickness of the silicon oxide film 21 is about 10 nm, and the film thickness is reduced to 1/10 or less, so that the heat dissipation effect is improved. Further, the heat generated in the polysilicon layer 22 is transferred to the metal layer 23 through the silicon oxide film 21 and the low resistance thin film SOI layer 20 having good thermal conductivity, and is dissipated in the metal layer 23.

As described above, the heat generated in the polysilicon layer 22 is applied to the silicon oxide film 21 and the low resistance thin film SOI layer 2
It is transmitted to the metal layer 23 through 0, and can be efficiently transmitted to the metal layer 23. Therefore, the polysilicon layer 2
The temperature rise of 2 can be suppressed, and thermal destruction can be suppressed.

Therefore, the allowable power loss is improved without increasing the area of the protective resistor. As described above, in the present embodiment, the semiconductor integrated circuit 7 including the MOSFET 6 formed in the thin film SOI layer 3 (semiconductor layer) via the silicon oxide film 2 (insulator layer) on the single crystal silicon substrate 1 (semiconductor substrate). And a polysilicon layer 22 (protective resistor) provided between the bonding pad 9 (external connection terminal) and the semiconductor integrated circuit 7 and arranged via the silicon oxide film 2 on the single crystal silicon substrate 1. In the provided semiconductor integrated circuit device, the low resistance thin film SOI layer 20 (conductor layer) is provided to the polysilicon layer 22 via the silicon oxide film 21 (insulator) made of the same material and the same film thickness as the gate oxide film of the MOSFET 6. ) Is arranged, and the metal layer 23 thermally connected to the low resistance thin film SOI layer 20 is arranged on the front surface side of the single crystal silicon substrate 1. More specifically, the polysilicon layer 22 (protective resistor) is made of the same material as the gate electrode of the MOSFET 6, and the conductor layer is the low resistance thin film SOI layer 20 (with the silicon oxide film 2 on the single crystal silicon substrate 1 interposed therebetween). Semiconductor layer), and a silicon oxide film 21 is formed under the polysilicon layer 22.
The low resistance thin film SOI layer 20 was arranged via the above.

Therefore, when a high voltage is applied to the bonding pad 9, the polysilicon layer 22 generates heat, and the heat is transferred through the thin silicon oxide film 21 to the low resistance thin film SOI layer 2.
Low resistance thin film SO that has high thermal conductivity.
This metal layer 2 is transmitted to the metal layer 23 through the I layer 20.
Dispersed at 3. Thus, since the silicon oxide film 21 is thin, the heat dissipation effect is improved.

Further, in this embodiment, the polysilicon layer 22 (protective resistor) is thermally connected to the metal layer 23 via the low resistance thin film SOI layer 20 therebelow, so that, for example, for wiring. Even in a portion where the metal layer 23 cannot be arranged,
Low resistance thin film SOI layer 2 up to where metal layer 23 can be arranged
By extending 0, heat dissipation can be improved.

As another mode of this embodiment, the following may be carried out. Similar to the first embodiment, the metal layer 23 is connected to the bonding pad 9 to bring the low resistance thin film SOI layer 20 to the same potential as the polysilicon layer 22 (protective resistor) and to transfer heat energy to the bonding pad 9. You may make it diverge. Further, the low resistance thin film SOI layer 20 may be divided into small areas so that the thin silicon oxide film 21 is not easily broken.

[0050]

As described in detail above, according to the inventions of claims 1, 2 and 3, the excellent effect of improving the heat radiation effect is exhibited.

According to the invention of claim 4, claim 1
In addition to the effects of the invention described in (1), it is difficult to apply a high voltage to the insulator, and the protective function of the protective resistor can be maintained even if the insulator is destroyed.

[Brief description of drawings]

FIG. 1 shows a semiconductor integrated circuit device according to a first embodiment,
(A) is a plan view, (b) is A-A in (a)
It is sectional drawing.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor integrated circuit device of the first embodiment.

FIG. 3 is a cross-sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment.

FIG. 4 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment.

FIG. 5 is a cross-sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment.

FIG. 6 is a cross-sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment.

FIG. 7 shows a semiconductor integrated circuit device of an application example of the first embodiment, (a) is a plan view, and (b) is B in (a).
It is a -B sectional view.

FIG. 8 shows a semiconductor integrated circuit device of an application example of the first embodiment, (a) is a plan view, and (b) is a C in (a).
FIG.

FIG. 9 shows a semiconductor integrated circuit device of an application example of the first embodiment, (a) is a plan view, and (b) is a D in (a).
It is a -D sectional view.

FIG. 10 shows a semiconductor integrated circuit device of a second embodiment,
(A) is a plan view, (b) is EE in (a)
It is sectional drawing.

FIG. 11 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the second embodiment.

FIG. 12 is a cross-sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the second embodiment.

FIG. 13 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the second embodiment.

FIG. 14 is a sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the second embodiment.

FIG. 15 is a cross-sectional view for explaining the manufacturing process for the semiconductor integrated circuit device according to the first embodiment.

FIG. 16 is a plan view of a conventional device.

17 is a cross-sectional view taken along the line FF of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon substrate as a semiconductor substrate, 2 ... Silicon oxide film as an insulator layer, 3 ... Thin film SOI layer as a semiconductor layer, 4 ... Silicon oxide film as a gate oxide film, 5 ... Polysilicon gate electrode, 6 ... MOSFET,
7 ... Semiconductor integrated circuit, 9 ... Bonding pad as external connection terminal, 10 ... Thin SOI layer as protective resistor and semiconductor layer, 11 ... Silicon oxide film as insulator, 12 ... Low resistance poly as conductor layer Silicon layer, 1
3 ... Metal layer, 20 ... Low resistance thin film SOI layer as conductor layer and semiconductor layer, 21 ... Silicon oxide film as insulator, 22 ... Polysilicon layer as protection resistor, 23 ...
Metal layer

Claims (4)

[Claims] 1. A semiconductor integrated circuit including a MOSFET formed on a semiconductor layer with an insulator layer on a semiconductor substrate, and provided between an external connection terminal and the semiconductor integrated circuit.
A semiconductor integrated circuit device comprising a protective resistor arranged via an insulating layer on the semiconductor substrate, wherein the protective resistor is made of the same material and has the same film thickness as the gate oxide film of the MOSFET. A semiconductor integrated circuit device, wherein a conductor layer is arranged via a body, and a metal layer thermally connected to the conductor layer is arranged on a front surface side of the semiconductor substrate. 2. The protective resistor is made of a semiconductor layer with an insulating layer on the semiconductor substrate, and the conductive layer is made of the same material as the gate electrode of the MOSFET, and the insulating layer is formed on the protective resistor. 2. The semiconductor integrated circuit device according to claim 1, wherein a conductor layer is arranged via the body. 3. The protection resistor is made of the same material as the gate electrode of the MOSFET, the conductor layer is made of a semiconductor layer via an insulator layer on the semiconductor substrate, and the protection layer is formed under the protection resistor. 2. The semiconductor integrated circuit device according to claim 1, wherein the conductor layer is arranged via an insulator. 4. The semiconductor integrated circuit device according to claim 1, wherein the conductor layer has the same potential as the protective resistor or is in a floating state.