JPH0388338A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to avoid the decrease in operating speed due to the increase in parasitic capacitance between an LDD region and a gate electrode by the characteristic of a constitution wherein a conductor layer which is formed on a low-concentration drain region through an insulating layer whose thickness in terms of capacitance is larger than that of a gate insulating film and connected to a gate electrode is provided. CONSTITUTION:An overlapped part 12 between a gate electrode 1 and an LDD region 3 is formed of a conductor layer other than the gate electrode 1. For example, in an element isolating region which is demarcated by an isolating and insulating layer 20, an extending part 21 of the gate electrode 1 is connected to an extending part 22 of the overlapped part 12. A thickness t1 of an insulating film 14 at the overlapped part 12 can be selected independently from a thickness (t2) of a gate insulating film 10. For example, t1=500Angstrom for is set t2=140Angstrom . Thus, the parasitic capacitance at the overlapped part 12 can be decreased to 30% or less the convensional value, and the operating speed can be improved by three times or more.

Description

[Detailed Description of the Invention] [Summary] In order to prevent characteristic deterioration caused by hot electrons being trapped in the insulating layer in the LDD region, the LDDS
This invention relates to a semiconductor device having a structure in which gate electrodes overlap in the L region.

The purpose is to avoid a decrease in operating speed due to an increase in parasitic capacitance between the LDD 81 area and the gate electrode.

A semiconductor substrate and a channel region and a drain region defined in the semiconductor substrate in close proximity to each other.

A gate electrode formed on the channel region via a gate insulating film, a low concentration drain region formed in the semiconductor substrate so as to be interposed between the channel region and the drain region, and and a conductive layer formed on the low concentration drain region and connected to the gate electrode via an insulating layer having a large thickness in terms of capacitance.

[Industrial application field]

The present invention relates to a semiconductor device having a structure in which a gate electrode overlaps a too61 region in order to prevent characteristic deterioration caused by hot electrons being trapped in an insulating layer in a lightly doped drain (LDD) fil region.

[Conventional technology]

When the channel length decreases as transistors become smaller (MOS), hot electrons are injected into the gate insulating film near the drain region, increasing the threshold voltage (vth) and increasing the drive capability (gm). ) decreases. As a method to prevent these phenomena, a lightly doped drain (LDD) is provided between the channel region and the drain region.

However, as miniaturization progresses further and the channel length becomes less than 1 μm, and the electric field in the channel and n-81 region increases, hot electrons generated by this high electric field will be injected into the insulating layer above the LDDjl region. It is known that the injected hot electrons cause the parasitic resistance (Rd) of the drain region to increase over time.

Such an increase in Rd causes a decrease in driving capacity (gm) and operating speed, which is unfavorable in terms of reliability.

On the other hand, if the power supply voltage is lowered to avoid the hot electron injection described above, the drive capability must be sacrificed.

As a means for eliminating the influence of hot electrons injected into the insulating layer in the LDD region, a structure has been proposed in which the gate electrode overlaps the LDD jil region, as shown in FIG.

That is, the gate electrode 1 is formed to have an overlapping portion 11 overlapping the LDDjl region 3. In FIG.
When implanting high-concentration impurities into the source/drain region 4, an electric field caused by a voltage applied to this overlap portion 11, which is a sidewall (or spacer) for masking the LDD region 3, causes t, oo
Since the influence of the hot electrons injected into the insulating film on the 61 region 3 is canceled by the gate electric field, the above-mentioned Rd does not increase over time. Therefore, L
By lowering the power supply voltage in order to avoid injection of hot electrons in the DDjl region, it is possible to solve the trade-off problem between a reduction in driving ability and reliability.

[Problem to be solved by the invention]

However, in the structure of FIG. 3, the parasitic capacitance of the gate increases by the capacitance (C) between the overlap portion 11 and the LDD 8N region 3. Overlap part 1
The same insulating film as the gate insulating film lO between the gate electrode 1 and the substrate 5 was formed between the gate electrode 1 and the LDD region 3.

On the other hand, it is necessary to reduce the thickness of the gate insulating film according to the scaling law, but this also increases the extra capacitance (CI) in the overlap portion 11. 2. For example, 1-4 megabit class ultra LS
As in I, the gate insulating film is 200λ (Sin,
When the film is made as thin as (converted).

There is a problem in that an increase in the delay time per gate due to the increase in the extra capacitance (C,''), that is, a decrease in the operating speed cannot be ignored.

An object of the present invention is to avoid a decrease in operating speed caused by the capacitance of the overlapped portion of the gate electrode and the LDo 8N region.

[Means to solve the problem]

The above object includes a semiconductor substrate, a channel region and a drain region defined in the semiconductor substrate in close proximity to each other, a gate electrode formed on the channel region with a gate insulating film interposed therebetween, and the channel region and the drain region. a low concentration drain region formed on the semiconductor substrate so as to be interposed therebetween; and a low concentration drain region formed on the low concentration drain region via an insulating layer having a larger thickness in terms of capacitance than the gate insulating film; This is achieved by the semiconductor device according to the present invention, which is characterized by comprising a conductive layer connected to the gate electrode.

[For production]

FIG. 1 is a sectional view of a main part for explaining the present invention in detail. As shown in FIG. 5A, a structure is provided in which the thickness (t,) of the insulating film 14 at the overlap portion 12 between the gate electrode 1 and the LDD region 3 is larger than the thickness (tz) of the gate insulating film 1G. . In order to easily realize such a structure, for example, the overlap portion 12 is formed of a conductive layer different from that of the gate electrode 1.

As shown in FIG. 2B, a method is adopted in which the extended portion 21 of the gate electrode 1 and the extended portion 22 of the overlap portion 12 are connected in the element isolation region defined by the isolation insulating layer 20.

In the structure of FIG. 1, the thickness (tl) of the insulating film 14 in the overlap portion 12 can be selected independently of the thickness (h) of the gate insulating film 10, for example.

For tx = 140 people, Lt is 500 people.

This reduces the parasitic capacitance in the overlap portion 12.

This can be reduced to 30% or less of the conventional value as shown in FIG.

In other words, it is possible to improve the operating speed by more than three times. On the other hand, when viewed from the gate insulating film 10.

Its reduced thickness prevents the seat channel effect.
(at, c, t, actual thickness; ε, dielectric constant) are made larger than those of the gate insulating film IO.

〔Example〕

An embodiment of the manufacturing process of a semiconductor device according to the present invention will be described below with reference to FIG. In the drawing below.

The same parts as in the previously published drawings are designated by the same reference numerals.

Referring to FIG. 2(a), after forming a gate insulating film 10 with a thickness of approximately 140 mm on the surface of the semiconductor substrate 30 exposed in the element formation region defined by the isolation insulating layer 20, for example, Forming the gate electrode 1 consisting of a polysilicon layer (6) Similar to a conventional MOS transistor, the gate electrode 1 has an extension 21 that reaches onto the separating insulating layer 20 . Note that the extended portion 21 in the figure may be regarded as an extended portion of the gate electrode 1 formed in an adjacent element formation region (not shown).

Then 9, for example, using the gate electrode 1 as a mask.

After ion-implanting n-type impurities at a concentration of about +lXl0I3/cm'' into the element forming region to form a low concentration n-type region 31 as shown in FIG. The thickness of the body is about 50, for example, from stow.
Deposit an insulating layer 32 of zero. The low concentration n-type region 31 is.

This constitutes an LDD area 3, which will be described later.

Next, as shown in FIG. 2C, a resist mask layer 34 having an opening exposing the extended portion 21 on the isolation insulating layer 20 is formed, and a well-known resist mask layer 34 is formed in a direction perpendicular to the surface of the semiconductor substrate 30. Anisotropic etching is performed to remove the insulating layer 32 on the stretched portion 21. The insulating layer 32 remains on the side surface of the extended portion 21. This anisotropic etching
The end point is determined by detecting that the upper surface of No. 1 is exposed.

Next, after removing the resist mask layer 34.

As shown in FIG. 2(d), on the surface of the semiconductor substrate 30.

For example, a conductive layer 35 made of polysilicon with a thickness of about 1,000 thick and an insulating layer 36 made of Sing with a thickness of about 2,000 to 10,000 thick are sequentially deposited. and one isolation insulating layer 20
A resist mask layer 38 is formed to mask the upper extended portion 21, and anisotropic etching is performed in a direction perpendicular to the surface of the semiconductor substrate 30, so that the insulating layer 36. is exposed from the resist mask layer 38. Conductive layer 35. Then, the insulating layer 32 is sequentially and selectively removed.

In the above anisotropic etching, the removal of the insulating layer 36 made of Sing is terminated when the exposure of the conductive layer 35 is detected. In addition, the conductive layer 35 made of polysilicon
The removal ends when it is detected that the conductive layer 35 no longer exists. Therefore, the resist mask layer 38 in FIG. 2(d) needs to be formed so as to completely cover the stretched portion 21 exposed in FIG. 2(C). Further, the insulating layer 32 may be removed in the same manner as the insulating layer 36, and the end point may be determined by detecting that the gate electrode 1 is exposed.

As a result of the above anisotropic etching, the upper surface of the gate electrode 1 is exposed as shown in FIG. 2(e).

On the side surface of the gate electrode 1, a side wall 40 formed by stacking an insulating layer 32, a conductive layer 35, and an insulating layer 36 remains. - way 1
Extended portion 21 of gate electrode 1 on isolation insulating layer 20
is covered with a conductive layer 35 and an insulating layer 36.

Next, using the sidewall 40 as a mask, in the element formation region,
5. N-type impurity ions at a concentration of about 5XIO"/cm" are implanted to form highly doped n-type regions, that is, source/drain regions 4. Directly below the side wall 40.

A portion of the low concentration n-type region 31 remains, and LDD ji
Configure area 3. The conductive layer 35 constituting the side wall 40 is
The overlap portion 12 (first
(see figure). In this way, the electrode layer overlapping the LDD region 3 is formed in a self-aligned manner.

The conductive layer 35 constituting this overlap portion 12 is 9
The extending portion 2 of the gate electrode l extends on the isolation insulating layer 20.
I am in contact with 1. That is, in the structure of the present invention, the electrode layer overlapping the LDDel region 3 is formed of a conductive layer different from that of the gate electrode l, but is connected to the gate electrode l at its extended portion 22, It is set to the same potential as the gate electrode l. however,
The parasitic capacitance between the overlap portion 12 and the LDD fJ region 3 can be controlled independently of the gate insulating film 10 by changing the thickness of the insulating layer 32. Therefore, by setting the thickness of the insulating layer 32 to 500 Å as described above, the parasitic capacitance can be reduced to about 1/3.5 compared to the case where, for example, 140 insulating layers, which are the same as the conventional gate insulating film IO, are used. can be reduced to As the insulating layer 32, a gate insulating film lO
By using a material with a lower dielectric constant, it is possible to further reduce the parasitic capacitance.

After the above, an insulating layer between the eyebrows is formed on the surface of the semiconductor substrate 30, and contact holes reaching the source/drain region 4 and the extended portion 21 of the gate electrode 1 are provided in this interlayer insulating layer, and each contact hole is formed through these contact holes. A wiring layer connected to the region is formed to complete the semiconductor device of the present invention.

Note that in the above, the gate insulating film IO is made of Si or N.

It may be formed using a high dielectric material such as. The advantage of using a high dielectric constant material for the gate insulating film is that the thickness of the insulating film can be selected to be relatively large within the range of allowable variations in device characteristics, making it easy to control the film thickness. .

〔Effect of the invention〕

According to the present invention, this becomes a problem in a MOS transistor having an LDD structure. The deterioration of the characteristics over time due to the injection of hot electrons into the insulating layer on the Loo61 region is
This can be prevented without sacrificing operating speed and drive capability, and has the effect of making it possible to provide a high performance MOS transistor with high drive capability.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is an explanatory diagram of the manufacturing process of the semiconductor device of the present invention. FIG. 3 is an explanatory diagram of the problems of the conventional method. In fig. 1 is the gate electrode, 2 is the side wall. 3 is the LDD region, and 4 is the source/drain region. lO is a gate insulating film. 11 and 12 are overlapping parts. 14 is an insulating film, and 20 is an isolation insulating layer. 21 is an extended portion of the gate electrode l. 22 is an extended portion of the overlap portion 12; 30 is a semiconductor substrate, and 31 is a low concentration n-type region. 32 and 36 are insulating layers, and 34 and 38 are resist mask layers. 35 is a conductive layer, and 40 is a side wall.

Claims (1)

[Scope of Claims] A semiconductor substrate; a channel region and a drain region defined close to each other on the semiconductor substrate; a gate electrode formed on the channel region with a gate insulating film interposed therebetween; and the channel region. a low concentration drain region formed on the semiconductor substrate so as to be interposed between the gate insulation film and the drain region; 1. A semiconductor device comprising: a conductive layer formed thereon and connected to the gate electrode.