JPH08293502A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE: To improve reliability of passivation in a mesa side wall of a bipolar transistor with a mesa structure and in a side surface of a contact hole by preventing stress in the former and voids in the latter. CONSTITUTION: A side wall 9 as a passivation film consisting of silicon nitride is formed in both side surfaces of a semiconductor layer of emitters 5, 6 formed to a mesa type. A film 12 consisting of silicon nitride is formed in a side surface of a hole 11 for contact. When a mesa and a contact hole are etched, a silicon nitride film is produced by carrying out dry etching by plasma including nitrogen and silicon tetrachloride (SiCl4 ) and it is formed as a side wall and an inner wall as each of the passivation films 9, 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly to a mesa type bipolar transistor using gallium arsenide (GaAs) as a material and a method for manufacturing the same.

[0002]

2. Description of the Related Art Bipolar transistors are superior to field effect transistors in terms of power density and breakdown voltage. Therefore, a heterojunction bipolar transistor using not only silicon but also a compound semiconductor (hereinafter abbreviated as HBT)
Research and development are actively carried out. 3 and 4 are cross-sectional views in the order of manufacturing steps for explaining a conventional HBT and its manufacturing method. First, as shown in FIG.
An n-type GaAs collector contact layer 2 and an n-type GaA are formed on the semi-insulating substrate 1 made of s by an epitaxial growth method.
s collector layer 3, p-type GaAs base layer 4, n-type AlG
An aAs emitter layer 5 and an emitter cap layer 6 are sequentially grown, and a portion other than the element region is made to have a high resistance by proton ion implantation to form an insulating region 7 for element isolation. Then, a refractory metal such as W is formed on the entire surface of the substrate.
A Si film is formed by a sputtering method, and the WSi film is patterned by reactive ion etching (RIE) using SF ₆ gas using a photoresist (not shown) as a mask to form an emitter electrode 8.

Next, as shown in FIG. 3B, the photoresist and the emitter electrode 8 are used as a mask to perform reactive ion beam etching with chlorine plasma to form the emitter cap layer 6 and the emitter layer 5 into p-type GaAs. Etching is performed until the surface of the base layer 4 is reached to form an emitter mesa. The photoresist is then removed with an organic solvent.

Next, as shown in FIG. 3C, after forming a silicon oxide film (SiO ₂ film) on the entire surface of the wafer, anisotropic etching is performed by reactive ion etching using CF ₄ gas. The emitter cap layer 6 and the emitter layer 5
Side walls 16 made of SiO ₂ are formed on both surfaces of the.

After that, as shown in FIG. 4A, an Au-based alloy, for example, AuMn, is formed on the entire surface of the wafer by a vacuum deposition method, and is patterned by an ion milling method using a photoresist as a mask. To form. Then, as shown in FIG. 4 (b), after cleaning with an organic solvent to remove the photoresist film, a photoresist having a predetermined pattern is newly used as a mask to remove the phosphoric acid, hydrogen peroxide solution, and a mixed solution of water. The base layer 4 and the collector layer 3 are sequentially etched to form a collector contact hole 11. In this contact hole 11, n
After exposing the surface of the type GaAs collector contact layer 2, a collector electrode 13 of AuGeNi is formed by a lift-off method.

Finally, as shown in FIG. 4C, after forming a passivation film 14 made of SiO _{2 on the} entire surface of the wafer, through holes are formed at the positions of the electrodes by reactive ion etching using CF ₄ gas. Then, a predetermined wiring 15 is formed in the region including the through hole, and the bipolar transistor is completed.

[0007]

In this conventional HBT, the side wall 16 made of SiO ₂ functions not only as a separator between the emitter and the base but also as a passivation film on the side surface of the emitter mesa. However, in general, SiO ₂ and GaA
A strong stress is generated at the interface between the s and AlGaAs semiconductors, and this stress causes cracks and the like on the side walls, impairing the passivation function and reducing the reliability of the bipolar transistor.

Further, in this conventional HBT manufacturing method,
The passivation film 14 made of SiO ₂ is formed on the entire surface of the wafer after the collector electrode is formed. However, due to the low adhesion between the passivation film and the electrode, the passivation film and the inner surface of the contact hole 11 may be separated from each other. There is also a problem in that voids 17 are generated and a portion of the inner surface of the contact hole 11 that is not passivated is generated, resulting in deterioration of reliability.

[0009]

It is an object of the present invention to suppress the stress on the side wall formed on the side surface of the mesa and to prevent voids on the inner surface of the contact hole, thereby improving the reliability of passivation in each and a bipolar transistor. It is to provide a manufacturing method.

[0010]

A bipolar transistor of the present invention is characterized in that side walls made of silicon nitride are formed on both side surfaces of a third semiconductor layer formed in a mesa type.

Further, the bipolar transistor of the present invention is characterized in that an inner wall made of silicon nitride is formed on the inner surface of the hole of the first semiconductor layer in which the contact hole is formed.

Further, according to the manufacturing method of the present invention, a plasma containing nitrogen and silicon tetrachloride (SiCl ₄ ) is used when the mesa is formed by etching the third semiconductor layer in the manufacturing process of the mesa type bipolar transistor. It is characterized by performing dry etching by.

Further, according to the manufacturing method of the present invention, in forming the contact hole by etching the first semiconductor layer in the manufacturing process of the mesa type bipolar transistor,
It is characterized in that the dry etching is performed by a plasma containing nitrogen and silicon tetrachloride.

[0014]

In the present invention, since the mixed gas containing nitrogen and silicon tetrachloride is used as the etching gas during the dry etching, during the progress of the etching due to the chlorine plasma dissociated from the silicon tetrachloride, the silicon tetrachloride is also dissociated. The silicon nitride formed by combining the formed silicon and nitrogen adheres to the side surface of the etching as a side wall. The silicon nitride side wall functions as a passivation film as a mesa side wall.

Further, since the silicon nitride film is deposited on the inner surface of the contact hole at the same time as the opening of the contact hole to function as a passivation film, the occurrence of voids, which would occur when depositing an insulating film after the electrode formation, is prevented. .

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views of a main part for explaining a bipolar transistor according to an embodiment of the present invention in accordance with its manufacturing process. First, as shown in FIG. 1A, an n-type GaAs collector contact layer 2, an n-type GaAs collector layer 3, a p-type GaAs base layer 4, and an n-type AlGaAs are epitaxially grown on a semi-insulating substrate 1 made of GaAs. The emitter layer 5 and the emitter cap layer 6 are sequentially grown, and the portion other than the element region is made to have a high resistance by proton ion implantation to form an insulating region 7 for element isolation. Next, a refractory metal is formed on the entire surface of the substrate,
For example, a WSi film is formed by a sputtering method, and using the photoresist (not shown) as a mask, the WSi film is patterned by reactive ion etching (RIE) using SF ₆ gas to form the emitter electrode 8.

Next, as shown in FIG. 1B, the emitter cap layer 6 and the emitter layer 5 are filled with nitrogen and silicon tetrachloride (S) using the photoresist and the emitter electrode 8.
Etching is performed by reactive ion beam etching using a plasma containing iCl ₄ ) until the surface of the p-type GaAs base layer 4 is reached to form an emitter mesa. This time,
An emitter mesa side surface passivation film 9 made of silicon nitride is simultaneously formed on the side surface of the emitter mesa.

Next, as shown in FIG. 2A, an Au-based alloy, for example, AuMn, is formed on the entire surface of the wafer by a vacuum deposition method, and is patterned by an ion milling method using a photoresist as a mask. To form. Subsequently, as shown in FIG. 2B, after cleaning with an organic solvent to remove the photoresist, the base layer 4 and the collector layer 3 are newly cleaned with nitrogen and silicon tetrachloride using the photoresist having a predetermined pattern as a mask. Sequential etching is performed by reactive ion beam etching using contained plasma to form a collector contact hole 11 exposing the surface of the n-type GaAs collector contact layer 2.

The collector contact hole 11
At the time of forming, the passivation film 12 made of SiN is simultaneously formed on the inner surface of the contact hole. The thickness of the passivation film 12 is at most about 10 nm, and the reduction of the collector electrode area due to the deposition of the passivation film can be ignored. After that, the collector electrode 13 made of AuGeNi is formed by the lift-off method.

After that, as shown in FIG. 2C, a passivation film 14 is formed on the entire surface, a through hole is formed in the passivation film 14, and then a wiring 15 is formed to form each electrode 7, 8, 1.
A bipolar transistor is completed by making an electrical connection to 3.

In the bipolar transistor of the present embodiment thus formed, the side wall 9 made of silicon nitride is formed on the side surface of the emitter cap layer 6 and the emitter layer 5 formed in the mesa type. Silicon suppresses the generation of stress at the interface with GaAs or AlGaAs. Therefore, the reliability of the side wall 9 functioning as a passivation film is secured, and the reliability of the bipolar transistor is secured.

When forming this mesa,
Since a mixed gas containing nitrogen and silicon tetrachloride is used as the dry etching gas, silicon nitride formed by combining silicon and nitrogen which are also dissociated from silicon tetrachloride while the etching is progressed by chlorine plasma dissociated from silicon tetrachloride. Adhere to the etched side surface as a side wall. Therefore,
It is not necessary to separately provide a process for forming the side wall, and the process can be simplified.

Further, as a method for producing such silicon nitride (SiN) or silicon nitride oxide (SiON), a plasma CVD method using monosilane (SiH ₄ ) as a raw material gas has been generally used in the past. It has been reported that hydrogen plasma generated during film formation causes a problem of inactivating carbon as a base dopant (N. M. Johnson et al.
al. ), Physical Review Bee (Physi
cal Review B), vol. 33, 1102-1.
105, January 1986). In this respect, in the manufacturing method of the above-mentioned embodiment, since the hydrogen gas or hydrogen plasma is not used when forming the silicon nitride passivation film, the deactivation of carbon as the base dopant does not occur.

Further, since the silicon nitride film is formed as the passivation film 12 formed on the inner surface of the collector contact hole 11, the generation of stress can be suppressed as in the case of the sidewall 9 described above. Further, since the passivation film 12 is formed at the same time when the contact hole 11 is opened, the manufacturing process can be simplified and a void is generated as in the conventional technique of depositing an insulating film after the electrode is formed. Never do
Its reliability is enhanced.

Although the present embodiment shows an example in which the base layer is made of GaAs, the present invention is not limited to this. For example, a p-type AlGaAs composition gradient layer or a p-type InGaAs composition gradient is formed in the base layer. Using a layer, n in the emitter layer
The same effect can be applied to any of bipolar transistors having various material systems such as a type using InGaP. Although the emitter top type bipolar transistor has been described in the embodiment, the same effect can be obtained in the collector top type bipolar transistor, and a silicon nitride passivation film can be formed on the side surface of the collector mesa and the inner surface of the emitter contact hole. it can.

[0026]

As described above, according to the present invention, since the silicon nitride film is formed as the side wall as the passivation film formed on both sides of the mesa of the bipolar transistor, the occurrence of stress in the mesa is suppressed, The reliability of passivation is improved by the occurrence of cracks.

Further, since the silicon nitride film is formed as the passivation film formed on the inner surface of the contact hole, generation of voids can be prevented and the reliability of passivation can be improved.

Further, in the manufacturing method of the present invention, the mixed gas containing nitrogen and silicon tetrachloride is used as the dry etching gas for forming the mesas such as the emitter and the collector. Since it is attached as a side wall to the side surface of the substrate, the passivation film can be manufactured without using an independent process, the process can be simplified, and the presence of carbon as a base dopant in forming the silicon nitride passivation film can be reduced. No activation occurs.

Further, according to the manufacturing method of the present invention, since the passivation film is formed on the inner surface of the contact hole at the same time when the contact hole is opened, the manufacturing fixation is simplified, and voids are not generated and the passivation is highly reliable. A film can be formed.

[Brief description of drawings]

FIG. 1 is a first sectional view showing a method for manufacturing a bipolar transistor of the present invention in the order of steps.

FIG. 2 is a second sectional view showing the method of manufacturing the bipolar transistor of the present invention in order of steps.

FIG. 3 is a first sectional view showing a method of manufacturing a conventional bipolar transistor in the order of steps.

FIG. 4 is a second cross-sectional view showing the method of manufacturing the conventional bipolar transistor in the order of steps.

[Explanation of symbols]

 1 GaAs semi-insulating substrate 2 n-type GaAs collector contact layer 3 n-type GaAs collector layer 4 p-type GaAs base layer 5 n-type AlGaAs emitter layer 6 emitter cap layer 7 insulating region 8 emitter electrode 9 passivation film 10 base electrode 11 collector contact Hole 12 passivation film 13 collector electrode

Claims (5)

[Claims] 1. A first semiconductor layer of a first conductivity type on a substrate,
In a mesa-type bipolar transistor having a second semiconductor layer of a second conductivity type and a third semiconductor layer of a first conductivity type, the third semiconductor layer is formed in a mesa type and nitrided on both side surfaces thereof. A bipolar transistor having a sidewall formed of silicon. 2. A first semiconductor layer of a first conductivity type on a substrate,
In a mesa bipolar transistor having a second semiconductor layer of a second conductivity type and a third semiconductor layer of a first conductivity type and having a contact hole reaching the first semiconductor layer, an inner surface of the hole is formed. Is a bipolar transistor having an inner wall made of silicon nitride. 3. The bipolar transistor according to claim 1, wherein the mesa layer is an emitter layer or a collector layer, and the first semiconductor layer is a collector layer or an emitter layer. 4. A first semiconductor layer of a first conductivity type on a substrate,
A method for manufacturing a mesa bipolar transistor having a second semiconductor layer of a second conductivity type and a third semiconductor layer of a first conductivity type, wherein the third semiconductor layer is made of nitrogen and silicon tetrachloride (SiCl). ₄ ) A method for manufacturing a bipolar transistor, which includes a step of forming a mesa layer by dry etching with plasma containing. 5. A first semiconductor layer of a first conductivity type on a substrate,
A method for manufacturing a mesa bipolar transistor having a second semiconductor layer of a second conductivity type and a third semiconductor layer of a first conductivity type, wherein the first semiconductor layer is made of nitrogen and silicon tetrachloride (SiCl). ₄ ) A method for manufacturing a bipolar transistor, characterized by including the step of performing dry etching with a plasma containing (1) to etch a contact hole for the first semiconductor layer.