JPH08288658A - Printed wiring board for bga package mount - Google Patents

Printed wiring board for bga package mount

Info

Publication number
JPH08288658A
JPH08288658A JP7092752A JP9275295A JPH08288658A JP H08288658 A JPH08288658 A JP H08288658A JP 7092752 A JP7092752 A JP 7092752A JP 9275295 A JP9275295 A JP 9275295A JP H08288658 A JPH08288658 A JP H08288658A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
electrode pad
bga package
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7092752A
Other languages
Japanese (ja)
Inventor
Akira Izumi
公 和泉
Yoshinori Ishibashi
淑憲 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7092752A priority Critical patent/JPH08288658A/en
Publication of JPH08288658A publication Critical patent/JPH08288658A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a printed wiring board for BGA package which prevents short-circuit between electrode pads due to superfluous bonding agent and imperfect bonding due to insufficient bonding agent, and surely enables visual inspection of defect, and improve packaging density by effectively arranging electrode pads and through hole lands. CONSTITUTION: In a printed wiring board 1 for BGA package, through hole lands 3L are arranged. The through hole land is formed in the vicinity of periphery of an electrode pad 2 connected with a spherical outer electrode of a BGA package, and constituted as as unified body with the electrode pad 2. The electrode pad 2 and the through hole land 3L are formed in a plane where the width is gradually decreased. The fluidity of superfluous bonding agent is accelerated, and made to flow smoothly into through holes positioned in the central parts of the through hole lands 3L. The through hole lands 3L are arranged in the oblique direction, while the electrode pads 2 are set as the centers.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はBGA(ボールグリッド
アレイ)パッケージが搭載される印刷配線基板に関す
る。特に本発明は、BGAパッケージの球状外部電極が
接続される電極パッドを有する印刷配線基板に関する。
本発明においては、BGAパッケージの球状外部電極と
印刷配線基板の電極パッドとの間の電気的かつ機械的な
接合(例えば、半田接合)が良好に行える印刷配線基板
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board on which a BGA (ball grid array) package is mounted. Particularly, the present invention relates to a printed wiring board having an electrode pad to which a spherical external electrode of a BGA package is connected.
The present invention relates to a printed wiring board capable of excellent electrical and mechanical bonding (for example, solder bonding) between a spherical external electrode of a BGA package and an electrode pad of the printed wiring board.

【0002】[0002]

【従来の技術】BGAパッケージにおいては、パッケー
ジ下面に球状外部端子が配列され、パッケージの外側面
の周囲に接続用外部端子が突出しないので、印刷配線基
板の実装面上に高密度実装ができる。さらに、BGAパ
ッケージは表面実装部品であり、印刷配線基板の表面及
び裏面の両面の実装面上に各々BGAパッケージが実装
できるので、印刷配線基板の実装面上に高密度実装がで
きる。
2. Description of the Related Art In a BGA package, spherical external terminals are arranged on the lower surface of the package, and the connecting external terminals do not project around the outer surface of the package, so that high density mounting can be performed on the mounting surface of a printed wiring board. Furthermore, since the BGA package is a surface mount component and the BGA package can be mounted on each of the mounting surfaces of the front surface and the back surface of the printed wiring board, high density mounting can be performed on the mounting surface of the printed wiring board.

【0003】図4は従来技術に係るBGAパッケージ搭
載用印刷配線基板の平面図であり、図5はBGAパッケ
ージが実装された状態において前記図4に示す切断線F
5−F5で切った印刷配線基板の縦断面図である。図5
に示すように、印刷配線基板1の実装面上にはBGAパ
ッケージ6が実装される。図4及び図5に示すように、
印刷配線基板1の実装面上には、BGAパッケージのパ
ッケージ下面に配列された球状外部電極8の配列位置及
び配列個数に対応し、実装面において行方向、列方向の
いずれにも規則的に配列された複数の電極パッド2が設
けられる。BGAパッケージ6の球状外部電極8と印刷
配線基板1の電極パッド2との間の接続は接合剤7で行
われ、接合剤7には半田が使用される。複数の電極パッ
ド2には各々スルーホールランド3Lが電気的に接続さ
れ、電極パッド2とスルーホールランド3Lとの間の接
続は接続用配線23で行われる。スルーホールランド3
Lは印刷配線基板1に形成されたスルーホールに埋め込
まれたスルーホール配線3Tに電気的に接続され、この
スルーホール配線3Tには印刷配線基板1の内部に配設
された内層配線(図示しない)に電気的に接続される。
FIG. 4 is a plan view of a printed wiring board for mounting a BGA package according to the prior art, and FIG. 5 is a cutting line F shown in FIG. 4 in a state where the BGA package is mounted.
It is a longitudinal cross-sectional view of the printed wiring board cut along 5-F5. Figure 5
As shown in, the BGA package 6 is mounted on the mounting surface of the printed wiring board 1. As shown in FIGS. 4 and 5,
On the mounting surface of the printed wiring board 1, the spherical external electrodes 8 arranged on the lower surface of the package of the BGA package correspond to the arrangement position and the number of arrangements, and are regularly arranged in both the row direction and the column direction on the mounting surface. A plurality of formed electrode pads 2 are provided. The bonding between the spherical external electrode 8 of the BGA package 6 and the electrode pad 2 of the printed wiring board 1 is performed by the bonding agent 7, and solder is used as the bonding agent 7. A through hole land 3L is electrically connected to each of the plurality of electrode pads 2, and a connection wiring 23 is used to connect the electrode pad 2 and the through hole land 3L. Through hole land 3
L is electrically connected to a through-hole wiring 3T embedded in a through-hole formed in the printed wiring board 1 and an inner layer wiring (not shown) arranged inside the printed wiring board 1 is provided in the through-hole wiring 3T. ) Is electrically connected to.

【0004】前記印刷配線基板1の実装面上にBGAパ
ッケージ6及び他の実装部品を実装する実装方法は以下
の手順で行われる。
A mounting method for mounting the BGA package 6 and other mounting components on the mounting surface of the printed wiring board 1 is performed in the following procedure.

【0005】まず、印刷配線基板製造時にBGAパッケ
ージ6の電極パッド2(他の実装部品が接続される電極
パッドを含む)及びスルーホールランド3Lを除き、印
刷配線基板1の実装面上にソルダレジストが塗布され
る。実装第1工程においては、BGAパッケージ6の電
極パッド2上にクリーム半田が塗布される。クリーム半
田は接合剤7として使用され、このクリーム半田は例え
ば印刷技術で塗布される。第2工程においては、印刷配
線基板1の実装面上にBGAパッケージ6が搭載され、
印刷配線基板1の電極パッド2上にクリーム半田を介し
てBGAパッケージ6の球状外部電極8が当接される。
BGAパッケージ6は装着装置等で搭載される。第3工
程においては、前記印刷配線基板1がリフロー炉に搬送
され、リフロー炉においてクリーム半田が加熱溶融さ
れ、半田リフローが行われる。この半田リフローによ
り、電極パッド2と球状外部電極8との間が接合剤7で
接合され、印刷配線基板1の実装面上にBGAパッケー
ジ6が実装される。
First, at the time of manufacturing the printed wiring board, the solder resist is provided on the mounting surface of the printed wiring board 1 except for the electrode pads 2 (including the electrode pads to which other mounting components are connected) of the BGA package 6 and the through hole lands 3L. Is applied. In the first mounting step, cream solder is applied onto the electrode pads 2 of the BGA package 6. The cream solder is used as the bonding agent 7, and this cream solder is applied by a printing technique, for example. In the second step, the BGA package 6 is mounted on the mounting surface of the printed wiring board 1,
The spherical external electrodes 8 of the BGA package 6 are brought into contact with the electrode pads 2 of the printed wiring board 1 via cream solder.
The BGA package 6 is mounted by a mounting device or the like. In the third step, the printed wiring board 1 is conveyed to a reflow oven, the cream solder is heated and melted in the reflow oven, and solder reflow is performed. By this solder reflow, the electrode pad 2 and the spherical external electrode 8 are bonded with the bonding agent 7, and the BGA package 6 is mounted on the mounting surface of the printed wiring board 1.

【0006】しかしながら、前記印刷配線基板1の実装
面上にBGAパッケージ6が実装されてしまうと電極パ
ッド2と球状外部電極8との間の接合部分が隠れてしま
い、接合部分の(接合剤7の状態を検査する)外観不良
検査が事実上行えない。従って、この種のBGAパッケ
ージ6を実装する印刷配線基板1においては如何に接合
部分の信頼性を確保するかが重要な課題として存在す
る。
However, when the BGA package 6 is mounted on the mounting surface of the printed wiring board 1, the bonding portion between the electrode pad 2 and the spherical external electrode 8 is hidden, and the bonding agent (bonding agent 7 The state of () is not inspected. Therefore, in the printed wiring board 1 on which this type of BGA package 6 is mounted, how to secure the reliability of the joint portion is an important issue.

【0007】さらに、半田リフローにおいては印刷配線
基板1に熱が加えられ、印刷配線基板1に反り、歪み等
の変形が発生しやすい。印刷配線基板1に変形が発生し
た場合には電極パッド2と球状外部電極8との間に隙間
が生じ、接合剤7の不足に起因する接合不良が発生す
る。また、接合剤7の不足を予測し予め接合剤7(クリ
ーム半田)を多めに塗布しておくと、逆に電極パッド2
と球状外部電極8との間に隙間が生じない箇所において
は接合剤7が過剰に存在する。このため、図5に示すよ
うに隣接する電極パッド2間(球状外部電極8間)にお
いて余剰の接合剤7が互いに連結する短絡部7Sが生成
され、電極パッド2間に短絡が発生する。
Further, in the solder reflow, heat is applied to the printed wiring board 1 and the printed wiring board 1 is likely to be deformed such as warped or distorted. When the printed wiring board 1 is deformed, a gap is created between the electrode pad 2 and the spherical external electrode 8, and a bonding failure due to the lack of the bonding agent 7 occurs. Further, when the shortage of the bonding agent 7 is predicted and a large amount of the bonding agent 7 (cream solder) is applied in advance, on the contrary, the electrode pad 2
Excessive amount of the bonding agent 7 is present at a location where no gap is formed between the spherical external electrode 8 and the spherical external electrode 8. Therefore, as shown in FIG. 5, a short-circuit portion 7S is formed between the adjacent electrode pads 2 (between the spherical external electrodes 8) so that the excess bonding agent 7 is connected to each other, and a short circuit occurs between the electrode pads 2.

【0008】特開平l−258454号公報には前述の
外観不良検査が困難な点を改善できる技術が開示されて
いる。この公報に開示された技術においてはパッケージ
下面の電極部にパッケージ上面まで達するスルーホール
が形成される。パッケージを半田付けで実装基板に実装
する際に前記スルーホール内を這い上がる半田の存在が
確認され、この半田の這上がりがあるか否かで外観不良
検査において良否が判定される。
Japanese Unexamined Patent Publication (Kokai) No. 1-258454 discloses a technique capable of improving the difficulty of the above-described appearance defect inspection. In the technique disclosed in this publication, a through hole reaching the upper surface of the package is formed in the electrode portion on the lower surface of the package. When the package is mounted on the mounting board by soldering, the presence of the solder crawling in the through hole is confirmed, and whether the solder has crawled up or not is judged by the appearance defect inspection.

【0009】さらに、実開平4−87682号公報には
前述の余剰の接合剤7に起因する電極パッド2間の短絡
が防止できる技術が開示されている。この公報に開示さ
れた技術においては半田パッド(前述の電極パッド2に
相当する)の中央部にスルーホールが形成される。この
スルーホールには余剰な半田が流し込まれるので、余剰
な半田に起因する半田パッド間の短絡が防止できる。
Further, Japanese Utility Model Laid-Open No. 4-87682 discloses a technique capable of preventing a short circuit between the electrode pads 2 due to the excess bonding agent 7. In the technique disclosed in this publication, a through hole is formed in the center of the solder pad (corresponding to the electrode pad 2 described above). Since excess solder is poured into the through holes, it is possible to prevent a short circuit between solder pads due to the excess solder.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、従来技
術においては以下の点の配慮がなされていない。 (1)前述の図4及び図5に示す印刷配線基板1におい
ては、電極パッド2から接続用配線23及びスルーホー
ルランド3Lを通してスルーホールに繋がる余剰な接合
剤7Lを逃がす経路が形成される。ところが、接続用配
線23は電極パッド2、スルーホールランド3Lの各々
の外形寸法に比べて小さい幅寸法でしかも均一な幅寸法
で形成される。さらに、接続用配線23は電極パッド
2、スルーホールランド3Lの各々と別の層でかつ別の
材料で形成される。このため、余剰な接合剤7Lを逃が
す経路においては、電極パッド2から接続用配線23に
至る部分で急激に経路幅が減少され、余剰な接合剤7L
は逃げにくく、実際には余剰な接合剤7Lを逃がす経路
としては機能しない。従って、前述のように余剰の接合
剤7Lに起因する電極パッド2間の短絡が発生する。
However, the following points have not been taken into consideration in the prior art. (1) In the printed wiring board 1 shown in FIGS. 4 and 5 described above, there is formed a path through which the excess bonding agent 7L connected to the through hole is released from the electrode pad 2 through the connection wiring 23 and the through hole land 3L. However, the connecting wiring 23 is formed with a width dimension smaller than the outer dimensions of the electrode pad 2 and the through-hole land 3L and a uniform width dimension. Further, the connection wiring 23 is formed in a layer different from that of each of the electrode pad 2 and the through hole land 3L and made of a different material. Therefore, in the route through which the excess bonding agent 7L is released, the route width is rapidly reduced in the portion from the electrode pad 2 to the connection wiring 23, and the excess bonding agent 7L is removed.
Is hard to escape, and actually does not function as a route for escaping the excess bonding agent 7L. Therefore, as described above, a short circuit occurs between the electrode pads 2 due to the excess bonding agent 7L.

【0011】(2)前述の図4及び図5に示す印刷配線
基板1においては、隣接する4つの電極パッド2で周囲
が囲まれた領域の中央にスルーホールランド3Lが配置
される。このため、電極パッド2とスルーホールランド
3Lとの間には、図4中、上下方向、左右方向に延在す
る外層配線が実質的に通せないので、外層配線は電極パ
ッド2の配列領域及びスルーホールランド3Lの配列領
域を迂回し引き回される。従って、印刷配線基板1の実
装面上には引き回し配線の余分な配置領域が必要になる
ので、印刷配線基板1において実装効率が減少する。
(2) In the printed wiring board 1 shown in FIGS. 4 and 5, the through hole land 3L is arranged at the center of the area surrounded by the four adjacent electrode pads 2. For this reason, the outer layer wiring extending vertically and horizontally in FIG. 4 cannot be substantially passed between the electrode pad 2 and the through-hole land 3L, and therefore the outer layer wiring is arranged in the arrangement region of the electrode pads 2 and It is routed around the array area of the through hole land 3L. Therefore, since an extra layout wiring area is required on the mounting surface of the printed wiring board 1, the mounting efficiency of the printed wiring board 1 is reduced.

【0012】(3)前述の特開平l−258454号公
報に開示された技術においては、確かに目視による外観
不良検査が行えるが、パッケージ側にスルーホールが形
成されるので、パッケージ内の素子及び配線を避けてス
ルーホールが形成される。この結果、スルーホールが形
成される分、パッケージの寸法が大きくなるので、実装
基板の実装面上において実装効率が低くなる。
(3) According to the technique disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-258454, it is possible to visually inspect for visual defects, but since the through holes are formed on the package side, the elements in the package and Through holes are formed while avoiding wiring. As a result, the size of the package is increased due to the formation of the through hole, so that the mounting efficiency is lowered on the mounting surface of the mounting substrate.

【0013】(4)前述の実開平4−87682号公報
に開示された技術においては、半田リフローで印刷配線
基板1に変形が発生し、半田パッド上に隙間が生じる箇
所においても半田がスルーホール内に流れ込んでしま
う。このため、隙間が生じる箇所においては半田の不足
による接合不良が発生する。
(4) In the technique disclosed in the above-mentioned Japanese Utility Model Laid-Open No. 4-87682, the solder reflow causes deformation of the printed wiring board 1, resulting in a through hole of solder even at a place where a gap is formed on the solder pad. It flows inside. For this reason, a joint failure occurs due to lack of solder at the place where the gap is generated.

【0014】本発明は前述の課題を解決するためになさ
れたものであり、本発明の目的は下記の通りである。
The present invention has been made to solve the above problems, and the objects of the present invention are as follows.

【0015】(1)本発明は、余剰な接合剤に起因する
電極パッド間の短絡を防止し、接合剤の不足に起因する
接合不良を防止するとともに、外観不良検査が確実に行
える、BGAパッケージが搭載される印刷配線基板の提
供を目的とする。
(1) The present invention prevents a short circuit between electrode pads due to an excess bonding agent, prevents a bonding failure due to a shortage of the bonding agent, and can reliably perform a visual defect inspection. An object of the present invention is to provide a printed wiring board on which is mounted.

【0016】(2)本発明は、電極パッド及びスルーホ
ールランドを効率良く配列し、実装密度が向上できる、
BGAパッケージが搭載される印刷配線基板の提供を目
的とする。
(2) According to the present invention, the electrode pads and the through hole lands can be efficiently arranged to improve the packaging density.
An object is to provide a printed wiring board on which a BGA package is mounted.

【0017】[0017]

【課題を解決するための手段及び作用】上記課題を解決
するため、請求項1に係る発明は、BGAパッケージが
搭載される印刷配線基板において、前記BGAパッケー
ジの球状外部電極に電気的かつ機械的に接続され、前記
球状外部電極の配列位置及び配列個数に応じて実装面上
に配置される電極パッドと、前記電極パッドの周囲の近
接した位置において前記実装面上に配置され、前記電極
パッドと同一層及び同一材料で一体に形成され、基板内
部に配設された内層配線に電気的に接続されたスルーホ
ールランドと、を備えたことを特徴とする。
In order to solve the above problems, the present invention according to claim 1 provides a printed wiring board on which a BGA package is mounted, which is electrically and mechanically connected to a spherical external electrode of the BGA package. And electrode pads arranged on the mounting surface according to the arrangement position and the number of arrangement of the spherical external electrodes, and arranged on the mounting surface at positions close to the periphery of the electrode pad, and the electrode pads. Through hole lands that are integrally formed of the same layer and the same material and that are electrically connected to the inner layer wiring provided inside the substrate.

【0018】請求項1に係る発明においては、熱処理
(例えば、半田リフロー)に起因し発生する印刷配線基
板とBGAパッケージとの間の隙間を吸収するためにB
GAパッケージの球状外部電極と印刷配線基板の電極パ
ッドとの間に過剰の接合剤(例えば、半田)が使用され
る場合に、余剰の接合剤がスルーホールランド内(スル
ーホール内)に流し込める。前記電極パッドとスルーホ
ールランドとは一体に形成され、余剰の接合剤が流動す
る経路である電極パッドの表面及びスルーホールランド
の表面が段差を減少した滑らかな表面で形成されるの
で、余剰の接合剤においては流動性が促進される。従っ
て、隣接する電極パッド間が余剰の接合剤で繋がる短絡
の発生が減少できる。さらに、余剰の接合剤はスルーホ
ール内に流しこまれるので、この余剰の接合剤に基づき
外観不良検査が行える。
According to the first aspect of the present invention, in order to absorb the gap between the printed wiring board and the BGA package, which is caused by heat treatment (for example, solder reflow), B is absorbed.
When an excessive bonding agent (for example, solder) is used between the spherical external electrode of the GA package and the electrode pad of the printed wiring board, the excess bonding agent can be poured into the through hole land (through hole). . Since the electrode pad and the through-hole land are integrally formed, and the surface of the electrode pad and the surface of the through-hole land, which is a path for the excess bonding agent to flow, are formed of smooth surfaces with reduced steps, the excess Fluidity is promoted in the cement. Therefore, it is possible to reduce the occurrence of a short circuit in which adjacent electrode pads are connected by an excessive bonding agent. Furthermore, since the surplus bonding agent is poured into the through holes, the appearance defect inspection can be performed based on the surplus bonding agent.

【0019】請求項2に係る発明は、前記請求項1に記
載される印刷配線基板において、前記一体に形成された
電極パッド及びスルーホールランドが電極パッド側から
前記スルーホールランド側に向かって幅が暫減される平
面形状で形成されることを特徴とする。
According to a second aspect of the present invention, in the printed wiring board according to the first aspect, the electrode pad and the through hole land which are integrally formed have a width from the electrode pad side toward the through hole land side. Is formed in a planar shape that is temporarily reduced.

【0020】請求項2に係る発明においては、電極パッ
ド上に形成された接合剤のうち余剰の接合剤が電極パッ
ドからスルーホールランドに徐々にしかもスムーズに流
し込める。
According to the second aspect of the invention, the surplus of the bonding agent formed on the electrode pad can be gradually and smoothly poured from the electrode pad to the through hole land.

【0021】請求項3に係る発明は、前記請求項1又は
請求項2に記載される印刷配線基板において、前記電極
パッドは行方向、列方向のいずれにも複数配列され、前
記スルーホールランドはこのスルーホールランドに一体
に形成された電極パッドを中心に電極パッドが配列され
る行方向、列方向のいずれに対しても傾斜角度を有する
斜め方向に配置されることを特徴とする。
According to a third aspect of the present invention, in the printed wiring board according to the first or second aspect, a plurality of the electrode pads are arranged in each of a row direction and a column direction, and the through hole lands are formed. It is characterized in that the electrode pads integrally formed on the through hole land are arranged in an oblique direction having an inclination angle with respect to both the row direction and the column direction in which the electrode pads are arranged.

【0022】請求項3に係る発明においては、前記スル
ーホールランドが配置された位置を前記電極パッドが配
列される行方向上、列方向上に各々投影すると、電極パ
ッドとこの電極パッドに一体に形成されたスルーホール
ランドとの間の距離が見掛上短縮できる。つまり、電極
パッドが配列される行方向、列方向において、電極パッ
ドに接続されたスルーホールランドと隣接する他の電極
パッドとの間のスペースが確保できるので、電極パッド
の配列間隔が縮小でき、実装面上に電極パッドが高密度
で配列できる。さらに、前記電極パッドに接続されたス
ルーホールランドと隣接する他の電極パッドとの間のス
ペースが確保できるので、このスペースに配線が配置で
きる。電極パッド間に配線が配置できると電極パッドを
迂回する引回し配線が減少できるので、実装面上に配線
が高密度で配置できる。
In the invention according to claim 3, when the positions where the through-hole lands are arranged are projected in the row direction and the column direction where the electrode pads are arranged, the electrode pads and the electrode pads are integrally formed. The distance between the formed through hole land can be apparently shortened. That is, in the row direction and the column direction in which the electrode pads are arranged, a space can be secured between the through hole land connected to the electrode pad and another adjacent electrode pad, so that the arrangement interval of the electrode pads can be reduced, Electrode pads can be arranged at high density on the mounting surface. Furthermore, since a space can be secured between the through hole land connected to the electrode pad and another adjacent electrode pad, wiring can be arranged in this space. If wirings can be arranged between the electrode pads, the number of wirings that bypass the electrode pads can be reduced, so that the wirings can be arranged at a high density on the mounting surface.

【0023】請求項4に係る発明は、前記請求項3に記
載される印刷配線基板において、前記電極パッドとこの
電極パッドに接続されるスルーホールランドとの間の距
離が前記スルーホールランドとこのスルーホールランド
が配置される斜め方向に隣接する他の電極パッドとの間
の距離に比べて小さく設定されることを特徴とする。
According to a fourth aspect of the present invention, in the printed wiring board according to the third aspect, a distance between the electrode pad and a through hole land connected to the electrode pad is equal to that of the through hole land. It is characterized in that it is set smaller than the distance between the through hole land and another electrode pad adjacent in the diagonal direction.

【0024】請求項4に係る発明においては、スルーホ
ールランドと隣接する他の電極パッドとの間にスペース
が確保できるので、このスペースに配線が配置できる。
従って、引回し配線が減少でき、実装面上に配線が高密
度で配置できる。
In the invention according to claim 4, since a space can be secured between the through hole land and another electrode pad adjacent to the through hole land, wiring can be arranged in this space.
Therefore, the number of wirings can be reduced, and the wirings can be arranged at a high density on the mounting surface.

【0025】請求項5に係る発明は、前記請求項1又は
請求項2に記載される印刷配線基板において、前記電極
パッド及びこの電極パッドに接続されたスルーホールラ
ンドが電極パッドを配列する行方向上又は列方向上に配
置されることを特徴とする。
According to a fifth aspect of the present invention, in the printed wiring board according to the first or second aspect, the electrode pad and the through-hole land connected to the electrode pad are arranged in the row direction on the row direction. Alternatively, they are arranged in the column direction.

【0026】請求項5に係る発明においては、電極パッ
ドが配列される列方向又は行方向にはスルーホールラン
ドが配置されないので、この方向において電極パッド間
にスペースが確保でき、このスペースに配線が配置でき
る。従って、引回し配線が減少でき、実装面上に配線が
高密度で配置できる。
In the invention according to claim 5, since the through hole lands are not arranged in the column direction or the row direction in which the electrode pads are arranged, a space can be secured between the electrode pads in this direction, and wiring can be provided in this space. Can be placed. Therefore, the number of wirings can be reduced, and the wirings can be arranged at a high density on the mounting surface.

【0027】[0027]

【実施例】【Example】

実施例1 図1は本発明の実施例1に係るBGAパッケージ用印刷
配線基板の一部を示す平面図、図2はBGAパッケージ
を実装した状態において前記図1に示す切断線F2−F
2で切った縦断面図である。
Embodiment 1 FIG. 1 is a plan view showing a part of a printed wiring board for a BGA package according to Embodiment 1 of the present invention, and FIG. 2 is a cutting line F2-F shown in FIG. 1 in a state where a BGA package is mounted.
It is a longitudinal cross-sectional view cut in 2.

【0028】図2に示すように、印刷配線基板1の実装
面上にはBGAパッケージ6が実装される。図1及び図
2に示すように、印刷配線基板1の実装面上には、BG
Aパッケージのパッケージ下面に配列された球状外部電
極8の配列位置及び配列個数に対応し、実装面において
行方向、列方向のいずれにも規則的に配列された複数の
電極パッド2が設けられる。実装面上において電極パッ
ド2の周囲の近接した位置にはスルーホールランド3L
が配置される。
As shown in FIG. 2, the BGA package 6 is mounted on the mounting surface of the printed wiring board 1. As shown in FIGS. 1 and 2, BG is mounted on the mounting surface of the printed wiring board 1.
A plurality of electrode pads 2 are provided which are arranged regularly in both the row direction and the column direction on the mounting surface, corresponding to the arrangement position and the number of the spherical external electrodes 8 arranged on the lower surface of the package of the A package. A through hole land 3L is provided at a position close to the periphery of the electrode pad 2 on the mounting surface.
Is arranged.

【0029】前記電極パッド2は球状外部電極8に接続
するのに必要な寸法及び形状で形成され、電極パッド2
は少なくとも球状外部電極8を実装面上に投影した円形
と同一又は類似した形状で形成される。スルーホールラ
ンド3Lは前記電極パッド2と同一層及び同一材料で一
体に形成され、スルーホールランド3Lと前記電極パッ
ド2とは電気的に接続される。前記電極パッド2とスル
ーホールランド3Lとが一体に形成されると、電極パッ
ド2の表面及びスルーホールランド3Lの表面の段差が
減少され滑らかな表面が形成される。電極パッド2から
スルーホールランド3Lまでは余剰の接合剤7Lが流動
する経路に相当し、余剰の接合剤7Lの流動性が促進さ
れる。
The electrode pad 2 is formed to have a size and shape necessary for connecting to the spherical external electrode 8.
Is formed in a shape that is the same as or similar to the circular shape in which at least the spherical external electrode 8 is projected on the mounting surface. The through hole land 3L is integrally formed of the same layer and the same material as the electrode pad 2, and the through hole land 3L and the electrode pad 2 are electrically connected. When the electrode pad 2 and the through hole land 3L are integrally formed, the step difference between the surface of the electrode pad 2 and the surface of the through hole land 3L is reduced to form a smooth surface. The excess bonding agent 7L flows from the electrode pad 2 to the through hole land 3L, and the fluidity of the excess bonding agent 7L is promoted.

【0030】本実施例においては1つの電極パッド2に
1つのスルーホールランド3Lが接続されるが、本発明
においては1つの電極パッド2に複数のスルーホールラ
ンド3Lを又は複数の電極パッド2に1つのスルーホー
ルランド3Lを接続する場合が含まれる。
In the present embodiment, one through hole land 3L is connected to one electrode pad 2, but in the present invention, one electrode pad 2 is provided with a plurality of through hole lands 3L or a plurality of electrode pads 2. The case where one through-hole land 3L is connected is included.

【0031】前記電極パッド2の外形サイズに比べてス
ルーホールランド3Lの外形サイズは小さく設定され、
一体に形成された電極パッド2及びスルーホールランド
3Lは電極パッド2側から前記スルーホールランド3L
側に向かって幅が暫減される平面形状で形成される。電
極パッド2上に接合剤7が塗布されるとこの塗布された
接合剤7のうち余剰の接合剤7Lは電極パッド2からス
ルーホールランド3Lの中央部に位置するスルーホール
内に徐々にしかもスムーズに流し込める。電極パッド2
と球状外部電極8との間の接合に必要な最小限の接合剤
7は電極パッド2の表面上に濡れ性により確保される。
The outer size of the through hole land 3L is set smaller than the outer size of the electrode pad 2.
The electrode pad 2 and the through hole land 3L formed integrally are the through hole land 3L from the electrode pad 2 side.
It is formed in a planar shape whose width is gradually reduced toward the side. When the bonding agent 7 is applied on the electrode pad 2, the excess bonding agent 7L of the applied bonding agent 7 gradually and smoothly moves from the electrode pad 2 into the through hole located in the central portion of the through hole land 3L. Can be poured into. Electrode pad 2
The minimum amount of the bonding agent 7 required for bonding between the spherical external electrode 8 and the spherical external electrode 8 is secured on the surface of the electrode pad 2 by wettability.

【0032】スルーホールランド3Lは印刷配線基板1
に形成されたスルーホールに埋め込まれたスルーホール
配線3Tに電気的に接続される。スルーホール配線3T
には印刷配線基板1の内部に配設された内層配線5が電
気的に接続される。スルーホール内に流し込まれる余剰
の接合剤7Lは印刷配線基板1の裏面から観測でき、こ
の余剰の接合剤7Lに基づき外観不良検査が行える。
The through hole land 3L is the printed wiring board 1
Is electrically connected to the through-hole wiring 3T embedded in the through-hole formed in. Through hole wiring 3T
The inner layer wiring 5 disposed inside the printed wiring board 1 is electrically connected to the. The surplus bonding agent 7L poured into the through holes can be observed from the back surface of the printed wiring board 1, and the appearance defect inspection can be performed based on the surplus bonding agent 7L.

【0033】前記電極パッド2の行方向及び列方向の配
列に対して、スルーホールランド3Lはこのスルーホー
ルランド3Lに一体に形成された電極パッド2を中心に
電極パッド2が配列される行方向、列方向のいずれに対
しても傾斜角度を有する斜め方向に配置される。すなわ
ち、図1に示すように、行方向に隣接する2つの電極パ
ッド2及び列方向に隣接する2つの電極パッド2の合計
4つの電極パッド2の各中心点を結んで便宜的に破線で
図示した四角形の対角線上に沿ってスルーホールランド
3Lが形成される。スルーホールランド3Lが配置され
た位置を前記電極パッド2が配列される行方向上、列方
向上に各々投影すると、電極パッド2とこの電極パッド
2に一体に形成されたスルーホールランド3Lとの間の
距離La、Lbが各々見掛上短縮できる。つまり、電極
パッド2が配列される行方向、列方向において、電極パ
ッド2に接続されたスルーホールランド3Lと隣接する
他の電極パッド2との間のスペースが確保できるので、
電極パッド2の配列間隔LA、LBが各々縮小できる。
表現を代えれば、電極パッド2に接続されたスルーホー
ルランド3Lと隣接する他の電極パッド2との間のスペ
ースが確保できるので、このスペースに同図1に示すよ
うに外層配線4が配置できる。
With respect to the arrangement of the electrode pads 2 in the row direction and the column direction, the through hole land 3L is arranged in the row direction in which the electrode pads 2 are arranged around the electrode pad 2 formed integrally with the through hole land 3L. , Are arranged in an oblique direction having an inclination angle with respect to any of the column directions. That is, as shown in FIG. 1, two electrode pads 2 adjacent to each other in the row direction and two electrode pads 2 adjacent to each other in the column direction are connected by connecting the respective center points of a total of four electrode pads 2 and are illustrated by broken lines for convenience. Through-hole lands 3L are formed along the diagonal line of the square. When the positions where the through-hole lands 3L are arranged are projected in the row direction and the column direction in which the electrode pads 2 are arranged, respectively, between the electrode pads 2 and the through-hole lands 3L formed integrally with the electrode pads 2. The distances La and Lb can be apparently shortened. That is, in the row direction and the column direction in which the electrode pads 2 are arranged, it is possible to secure a space between the through-hole land 3L connected to the electrode pad 2 and another electrode pad 2 adjacent thereto,
The arrangement intervals LA and LB of the electrode pads 2 can be reduced respectively.
In other words, a space can be secured between the through-hole land 3L connected to the electrode pad 2 and another adjacent electrode pad 2, so that the outer layer wiring 4 can be arranged in this space as shown in FIG. .

【0034】さらに、前記電極パッド2とこの電極パッ
ド2に接続されるスルーホールランド3Lとの間の距離
Lcが前記スルーホールランド3Lとこのスルーホール
ランド3Lが配置される斜め方向に隣接する他の電極パ
ッド2との間の距離LCに比べて小さく設定される。す
なわち、前述の便宜的に図示した四角形の中心点Pに達
しない寸法において前記電極パッド2とスルーホールラ
ンド3Lとが一体に形成される。従って、スルーホール
ランド3Lと隣接する他の電極パッド2との間にはスペ
ースが確保できる。確保されたスペースには外層配線4
が配置できる。
Further, the distance Lc between the electrode pad 2 and the through-hole land 3L connected to the electrode pad 2 is adjacent to the through-hole land 3L in the diagonal direction in which the through-hole land 3L is arranged. Is set smaller than the distance LC between the electrode pad 2 and the electrode pad 2. That is, the electrode pad 2 and the through hole land 3L are integrally formed in a size that does not reach the center point P of the quadrangle illustrated for convenience. Therefore, a space can be secured between the through-hole land 3L and another adjacent electrode pad 2. Outer layer wiring 4 in the secured space
Can be placed.

【0035】前記BGAパッケージ6の球状外部電極8
と印刷配線基板1の電極パッド2との間の接続は接合剤
7で行われ、接合剤7には例えば半田が使用される。
The spherical external electrode 8 of the BGA package 6
The connection between the printed wiring board 1 and the electrode pad 2 of the printed wiring board 1 is performed by a bonding agent 7, and for the bonding agent 7, for example, solder is used.

【0036】次に、前述の印刷配線基板1の実装面上に
BGAパッケージ6(及び他の実装部品)を実装する実
装方法について説明する。
Next, a mounting method for mounting the BGA package 6 (and other mounting components) on the mounting surface of the printed wiring board 1 will be described.

【0037】まず、印刷配線基板製造時にBGAパッケ
ージ6の電極パッド2(他の実装部品が接続される電極
パッドを含む)及びスルーホールランド3Lを除き、印
刷配線基板1の実装面上にソルダレジストが塗布され
る。実装第1工程においては、BGAパッケージ6の電
極パッド2上にクリーム半田が塗布される。クリーム半
田は接合剤7として使用され、このクリーム半田は例え
ば印刷技術で塗布される。第2工程においては、印刷配
線基板1の実装面上にBGAパッケージ6が搭載され、
印刷配線基板1の電極パッド2上にクリーム半田を介し
てBGAパッケージ6の球状外部電極8が当接される。
BGAパッケージ6は装着装置等で搭載される。第3工
程においては、前記印刷配線基板1がリフロー炉に搬送
され、リフロー炉においてクリーム半田が加熱溶融さ
れ、半田リフローが行われる。この半田リフローによ
り、電極パッド2と球状外部電極8との間が接合剤7で
接合され、印刷配線基板1の実装面上にBGAパッケー
ジ6が実装される。
First, at the time of manufacturing the printed wiring board, the solder resist is provided on the mounting surface of the printed wiring board 1 except for the electrode pads 2 (including the electrode pads to which other mounting components are connected) of the BGA package 6 and the through hole lands 3L. Is applied. In the first mounting step, cream solder is applied onto the electrode pads 2 of the BGA package 6. The cream solder is used as the bonding agent 7, and this cream solder is applied by a printing technique, for example. In the second step, the BGA package 6 is mounted on the mounting surface of the printed wiring board 1,
The spherical external electrodes 8 of the BGA package 6 are brought into contact with the electrode pads 2 of the printed wiring board 1 via cream solder.
The BGA package 6 is mounted by a mounting device or the like. In the third step, the printed wiring board 1 is conveyed to a reflow oven, the cream solder is heated and melted in the reflow oven, and solder reflow is performed. By this solder reflow, the electrode pad 2 and the spherical external electrode 8 are bonded with the bonding agent 7, and the BGA package 6 is mounted on the mounting surface of the printed wiring board 1.

【0038】このように構成される印刷配線基板1にお
いては以下の効果が得られる。
The printed wiring board 1 thus constructed has the following effects.

【0039】(1)実装時(半田リフロー時)に余剰な
接合剤7Lが電極パッド2からスルーホールランド3L
を通してスルーホール内に流れ込み、接合剤7の量が調
整されるので、余剰な接合剤7Lに起因する電極パッド
2間の短絡が防止できる。
(1) Excess bonding agent 7L from the electrode pad 2 to the through hole land 3L during mounting (during solder reflow)
Since the amount of the bonding agent 7 flows through the through holes to adjust the amount of the bonding agent 7, it is possible to prevent a short circuit between the electrode pads 2 due to the excess bonding agent 7L.

【0040】(2)スルーホールに流れ込む接合剤7L
は余剰のものに限られ、接合に必要な最小限の接合剤7
は電極パッド2の表面に濡れ性により確保できるので、
接合剤7の不足に起因する接合不良が防止できる。
(2) Bonding agent 7L flowing into the through hole
Is the surplus, and the minimum amount of bonding agent required for bonding 7
Can be secured on the surface of the electrode pad 2 by wettability,
It is possible to prevent defective bonding due to the shortage of the bonding agent 7.

【0041】(3)スルーホールに流れ込む接合剤7L
により外観不良検査が確実に行える。 (4)電極パッド2及びスルーホールランド3Lが効率
良く配列され、実装密度が向上できる。
(3) Bonding agent 7L flowing into the through hole
With this, the appearance defect inspection can be reliably performed. (4) The electrode pads 2 and the through hole lands 3L are efficiently arranged, and the mounting density can be improved.

【0042】実施例2.図3は本発明の実施例2に係る
BGAパッケージ用印刷配線基板の一部を示す平面図で
ある。
Example 2. FIG. 3 is a plan view showing a part of a printed wiring board for a BGA package according to the second embodiment of the present invention.

【0043】図3に示すように、本実施例に係る印刷配
線基板1においては電極パッド2及びこの電極パッド2
に接続されたスルーホールランド3Lが電極パッド2を
配列する行方向上(又は列方向上)に配置される。電極
パッド2が配列される列方向にはスルーホールランド3
Lが配置されないので、この方向において電極パッド2
間にスペースが確保できる。このスペースには外層配線
4が配置できるので、引回し配線が減少できる。
As shown in FIG. 3, in the printed wiring board 1 according to this embodiment, the electrode pad 2 and the electrode pad 2 are provided.
The through-hole land 3L connected to is arranged on the row direction (or on the column direction) where the electrode pads 2 are arranged. Through hole lands 3 are arranged in the column direction in which the electrode pads 2 are arranged.
Since L is not arranged, the electrode pad 2 in this direction
Space can be secured between them. Since the outer layer wiring 4 can be arranged in this space, the number of routing wirings can be reduced.

【0044】本実施例においては同図3に示すように電
極パッド2及びスルーホールランド3Lが一体化された
平面形状が長円形状で形成されるが、本発明においては
前記一体化された形状が矩形であってもよい。
In the present embodiment, as shown in FIG. 3, the planar shape in which the electrode pad 2 and the through-hole land 3L are integrated is formed into an oval shape. In the present invention, the integrated shape is the same. May be rectangular.

【0045】このように構成される印刷配線基板1にお
いては前述の実施例1に係る印刷配線基板1で得られる
効果と同様の効果が得られる。
In the printed wiring board 1 thus constructed, the same effects as those obtained by the printed wiring board 1 according to the first embodiment described above can be obtained.

【0046】[0046]

【発明の効果】本発明においては下記の効果が得られ
る。 (1)本発明は、余剰な接合剤に起因する電極パッド間
の短絡が防止でき、接合剤の不足に起因する接合不良が
防止できるとともに、外観不良検査が確実に行える、B
GAパッケージが搭載される印刷配線基板が提供でき
る。
The following effects are obtained in the present invention. (1) The present invention can prevent a short circuit between electrode pads due to an excess bonding agent, prevent a bonding failure due to a shortage of the bonding agent, and reliably perform a visual defect inspection.
A printed wiring board on which a GA package is mounted can be provided.

【0047】(2)本発明は、電極パッド及びスルーホ
ールランドが効率良く配列でき、実装密度が向上でき
る、BGAパッケージが搭載される印刷配線基板が提供
できる。
(2) The present invention can provide a printed wiring board on which a BGA package is mounted, in which electrode pads and through-hole lands can be efficiently arranged and packaging density can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1に係るBGAパッケージ用
印刷配線基板の一部を示す平面図である。
FIG. 1 is a plan view showing a part of a printed wiring board for a BGA package according to a first embodiment of the present invention.

【図2】 BGAパッケージを実装した状態において前
記図1に示す切断線F2−F2で切った縦断面図であ
る。
2 is a vertical cross-sectional view taken along the cutting line F2-F2 shown in FIG. 1 in a state in which a BGA package is mounted.

【図3】 本発明の実施例2に係るBGAパッケージ用
印刷配線基板の一部を示す平面図である。
FIG. 3 is a plan view showing a part of a printed wiring board for a BGA package according to a second embodiment of the present invention.

【図4】 従来技術に係るBGAパッケージ用印刷配線
基板の一部を示す平面図である。
FIG. 4 is a plan view showing a part of a printed wiring board for a BGA package according to a conventional technique.

【図5】 BGAパッケージを実装した状態において前
記図4に示す切断線F5−F5で切った縦断面図であ
る。
5 is a vertical cross-sectional view taken along the line F5-F5 shown in FIG. 4 in a state where a BGA package is mounted.

【符号の説明】[Explanation of symbols]

1 印刷配線基板、2 電極パッド、3L スルーホー
ルランド、3T スルーホール配線、4 外層配線、5
内層配線、6 BGAパッケージ、7,7L接合剤、
8 球状外部電極。
1 printed wiring board, 2 electrode pads, 3L through hole land, 3T through hole wiring, 4 outer layer wiring, 5
Inner layer wiring, 6 BGA package, 7,7L bonding agent,
8 Spherical external electrode.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/34 501 H01L 23/12 L ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H05K 3/34 501 H01L 23/12 L

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 BGAパッケージが搭載される印刷配線
基板において、 前記BGAパッケージの球状外部端子に電気的かつ機械
的に接続され、前記球状外部端子の配列位置及び配列個
数に応じて実装面上に配置される電極パッドと、 前記電極パッドの周囲の近接した位置において前記実装
面上に配置され、前記電極パッドと同一層及び同一材料
で一体に形成され、基板内部に配設された内層配線に電
気的に接続されたスルーホールランドと、 を備えたことを特徴とするBGAパッケージ搭載用印刷
配線基板。
1. A printed wiring board on which a BGA package is mounted is electrically and mechanically connected to spherical external terminals of the BGA package, and is mounted on a mounting surface according to the array position and the number of arrayed spherical external terminals. The electrode pad to be arranged is arranged on the mounting surface at a position close to the periphery of the electrode pad, and is formed integrally with the electrode pad in the same layer and the same material as the inner layer wiring arranged inside the substrate. A printed wiring board for mounting a BGA package, comprising: an electrically connected through hole land.
【請求項2】 前記請求項1に記載される印刷配線基板
において、 前記一体に形成された電極パッド及びスルーホールラン
ドは、電極パッド側から前記スルーホールランド側に向
かって幅が暫減される平面形状で形成されることを特徴
とするBGAパッケージ搭載用印刷配線基板。
2. The printed wiring board according to claim 1, wherein the width of the electrode pad and the through-hole land formed integrally is gradually reduced from the electrode pad side toward the through-hole land side. A printed wiring board for mounting a BGA package, which is formed in a planar shape.
【請求項3】 前記請求項1又は請求項2に記載される
印刷配線基板において、 前記電極パッドは行方向、列方向のいずれにも複数配列
され、 前記スルーホールランドはこのスルーホールランドに一
体に形成された電極パッドを中心に電極パッドが配列さ
れる行方向、列方向のいずれに対しても傾斜角度を有す
る斜め方向に配置されることを特徴とするBGAパッケ
ージ搭載用印刷配線基板。
3. The printed wiring board according to claim 1 or 2, wherein a plurality of the electrode pads are arranged in each of a row direction and a column direction, and the through hole land is integrated with the through hole land. A printed wiring board for mounting a BGA package, characterized in that the electrode pads are formed in a diagonal direction having an inclination angle with respect to both a row direction and a column direction.
【請求項4】 前記請求項3に記載される印刷配線基板
において、 前記電極パッドとこの電極パッドに接続されるスルーホ
ールランドとの間の距離は前記スルーホールランドとこ
のスルーホールランドが配置される斜め方向に隣接する
他の電極パッドとの間の距離に比べて小さく設定される
ことを特徴とするBGAパッケージ搭載用印刷配線基
板。
4. The printed wiring board according to claim 3, wherein a distance between the electrode pad and a through hole land connected to the electrode pad is such that the through hole land and the through hole land are arranged. A printed wiring board for mounting a BGA package, which is set to be smaller than a distance between other electrode pads adjacent to each other in an oblique direction.
【請求項5】 前記請求項1又は請求項2に記載される
印刷配線基板において、 前記電極パッド及びこの電極パッドに接続されたスルー
ホールランドは電極パッドが配列される行方向上又は列
方向上に配置されることを特徴とするBGAパッケージ
搭載用印刷配線基板。
5. The printed wiring board according to claim 1, wherein the electrode pad and the through-hole land connected to the electrode pad are arranged in a row direction or a column direction in which the electrode pads are arranged. A printed wiring board for mounting a BGA package, which is arranged.
JP7092752A 1995-04-18 1995-04-18 Printed wiring board for bga package mount Pending JPH08288658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7092752A JPH08288658A (en) 1995-04-18 1995-04-18 Printed wiring board for bga package mount

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7092752A JPH08288658A (en) 1995-04-18 1995-04-18 Printed wiring board for bga package mount

Publications (1)

Publication Number Publication Date
JPH08288658A true JPH08288658A (en) 1996-11-01

Family

ID=14063156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7092752A Pending JPH08288658A (en) 1995-04-18 1995-04-18 Printed wiring board for bga package mount

Country Status (1)

Country Link
JP (1) JPH08288658A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000022894A1 (en) * 1998-10-13 2000-04-20 Sun Microsystems, Inc. Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging
WO2002054838A1 (en) * 2000-12-29 2002-07-11 Intel Corporation (A Corporation Of Delaware) Via-in-pad with off-center geometry and methods of manufacture
JP2003283080A (en) * 2002-03-25 2003-10-03 Ricoh Co Ltd Auxiliary package for wiring and wiring layout structure of printed circuit wiring board
US7000312B2 (en) 2001-12-05 2006-02-21 Murata Manufacturing Co., Ltd. Circuit board device and mounting method therefor
JP2006114777A (en) * 2004-10-15 2006-04-27 Toshiba Corp Printed wiring substrate and information processing device mounting the same
WO2006059706A1 (en) * 2004-12-02 2006-06-08 Matsushita Electric Industrial Co., Ltd. Printed board and designing method therefor and ic package terminal designing method and connecting method therefor
JP2007180248A (en) * 2005-12-27 2007-07-12 Murata Mfg Co Ltd Electronic component mounting structure
JP2010123860A (en) * 2008-11-21 2010-06-03 Denso Wave Inc Substrate
JP2010161205A (en) * 2009-01-08 2010-07-22 Denso Wave Inc Substrate for bga mounting
JP2010171140A (en) * 2009-01-21 2010-08-05 Fujitsu Ltd Printed circuit board, and mounting structure and mounting method in printed circuit board
WO2017122674A1 (en) * 2016-01-15 2017-07-20 シャープ株式会社 Mounting substrate and method for manufacturing mounting substrate

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000022894A1 (en) * 1998-10-13 2000-04-20 Sun Microsystems, Inc. Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging
WO2002054838A1 (en) * 2000-12-29 2002-07-11 Intel Corporation (A Corporation Of Delaware) Via-in-pad with off-center geometry and methods of manufacture
US6833615B2 (en) 2000-12-29 2004-12-21 Intel Corporation Via-in-pad with off-center geometry
US7208348B2 (en) 2000-12-29 2007-04-24 Intel Corporation Methods of fabricating a via-in-pad with off-center geometry
US7000312B2 (en) 2001-12-05 2006-02-21 Murata Manufacturing Co., Ltd. Circuit board device and mounting method therefor
JP2003283080A (en) * 2002-03-25 2003-10-03 Ricoh Co Ltd Auxiliary package for wiring and wiring layout structure of printed circuit wiring board
US7525817B2 (en) 2002-03-25 2009-04-28 Ricoh Company, Ltd. Wiring layout of auxiliary wiring package and printed circuit wiring board
JP4625674B2 (en) * 2004-10-15 2011-02-02 株式会社東芝 Printed wiring board and information processing apparatus mounting this board
JP2006114777A (en) * 2004-10-15 2006-04-27 Toshiba Corp Printed wiring substrate and information processing device mounting the same
WO2006059706A1 (en) * 2004-12-02 2006-06-08 Matsushita Electric Industrial Co., Ltd. Printed board and designing method therefor and ic package terminal designing method and connecting method therefor
US8097815B2 (en) 2004-12-02 2012-01-17 Panasonic Corporation Printed circuit board and its designing method, and designing method of IC package terminal and its connecting method
JP2007180248A (en) * 2005-12-27 2007-07-12 Murata Mfg Co Ltd Electronic component mounting structure
JP2010123860A (en) * 2008-11-21 2010-06-03 Denso Wave Inc Substrate
JP2010161205A (en) * 2009-01-08 2010-07-22 Denso Wave Inc Substrate for bga mounting
JP2010171140A (en) * 2009-01-21 2010-08-05 Fujitsu Ltd Printed circuit board, and mounting structure and mounting method in printed circuit board
WO2017122674A1 (en) * 2016-01-15 2017-07-20 シャープ株式会社 Mounting substrate and method for manufacturing mounting substrate

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