JP2007180248A - Electronic component mounting structure - Google Patents

Electronic component mounting structure Download PDF

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Publication number
JP2007180248A
JP2007180248A JP2005376589A JP2005376589A JP2007180248A JP 2007180248 A JP2007180248 A JP 2007180248A JP 2005376589 A JP2005376589 A JP 2005376589A JP 2005376589 A JP2005376589 A JP 2005376589A JP 2007180248 A JP2007180248 A JP 2007180248A
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electronic component
insulating layer
multilayer substrate
bumps
mounting structure
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Tomoaki Shiraishi
智彰 白石
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component mounting structure that allows each terminal of an electronic component to be nearly uniformly bump-connected. <P>SOLUTION: A multilayered substrate 10 is provided with laminated insulating layers 11-14 and conductor patterns respectively arranged in each of insulating layers 11-14. At least one electronic component 50 is mounted onto the multilayered substrate 10 via bumps 54, 55 by flip chip bonding. When viewed transparently in a laminating direction of the insulating layers 11-14, all through-holes 11a, 11b formed in the first insulating layer 11 of the insulating films 11-14 closest to the bumps 54, 55 in the multilayered substrate 10 are apart from all the bumps 54, 55 for mounting the electronic component 50. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は電子部品実装構造に関し、詳しくは、電子部品をフリップチップボンディングにより多層基板に実装した電子部品実装構造に関する。   The present invention relates to an electronic component mounting structure, and more particularly to an electronic component mounting structure in which an electronic component is mounted on a multilayer substrate by flip chip bonding.

電気回路の高密度化、ユニット化等のために、多層基板に電子部品を実装した電子部品実装構造が利用されている。   An electronic component mounting structure in which electronic components are mounted on a multilayer substrate is used for increasing the density of electric circuits and unitization.

例えば図５に示す積層型セラミック電子部品１２１は、配線基板１３８上に形成された導体ランド１３９に、多層基板１２３の端子１２７が半田１４０により接続されている。多層基板１２３は、積層された複数のセラミック層１２２を含み、内部には、セラミック層１２２の間に配置された内部導体膜（導体パターン）１２８や、セラミック層１２２を貫通するビアホール導体１２９，１３０が形成されている。多層基板１２３の上面に形成された端子１２５には、ケース１３３や電子部品１３１，１３２が接続されている。電子部品１３１の端子電極１３４は、導電性接着剤１３５により接続されている。電子部品１３２は、金バンプ１３６により接続され、樹脂１３７によって封止されている（例えば、特許文献１参照）。   For example, in the multilayer ceramic electronic component 121 shown in FIG. 5, the terminal 127 of the multilayer substrate 123 is connected to the conductor land 139 formed on the wiring substrate 138 by the solder 140. The multilayer substrate 123 includes a plurality of laminated ceramic layers 122, and internally includes an internal conductor film (conductor pattern) 128 disposed between the ceramic layers 122 and via-hole conductors 129 and 130 penetrating the ceramic layer 122. Is formed. A case 133 and electronic components 131 and 132 are connected to a terminal 125 formed on the upper surface of the multilayer substrate 123. The terminal electrodes 134 of the electronic component 131 are connected by a conductive adhesive 135. The electronic component 132 is connected by a gold bump 136 and sealed with a resin 137 (see, for example, Patent Document 1).

一方、電子部品には、中空構造を有するものがある。例えば図６に示す加速度センサ１は、台座２に、中空構造を有するセンサチップ４が接着されている。センサチップ４には空間９が形成され、空間９中に、ビーム６によって主要部７が浮いた状態で支持されている。ビーム６には、矢印１ａで示した方向の主要部７の変位量を検出するため、ピエゾ抵抗８が形成されている。空間９の周囲に延在するセンサチップ４の外枠５は、接着剤３により台座２に接着されている。センサチップ４の外枠５に反りがあると、電気特性のばらつき等が生じる（例えば、非特許文献１参照）。
特開２００２−３６８４２６号公報 「姿を消す車載半導体」、日経エレクトロニクス３月１４日号、日経ＢＰ社、２００５年３月１４日、第８９５号、ｐ．１０８−１０９ On the other hand, some electronic components have a hollow structure. For example, in the acceleration sensor 1 shown in FIG. 6, a sensor chip 4 having a hollow structure is bonded to a pedestal 2. A space 9 is formed in the sensor chip 4, and the main portion 7 is supported in a state of being floated by the beam 6 in the space 9. A piezoresistor 8 is formed in the beam 6 in order to detect the amount of displacement of the main portion 7 in the direction indicated by the arrow 1a. An outer frame 5 of the sensor chip 4 extending around the space 9 is bonded to the base 2 with an adhesive 3. If the outer frame 5 of the sensor chip 4 is warped, variations in electrical characteristics occur (for example, see Non-Patent Document 1).
JP 2002-368426 A "Disappearing in-vehicle semiconductors", Nikkei Electronics March 14 issue, Nikkei BP, March 14, 2005, No. 895, p. 108-109

中空構造を有するセンサチップを接着する台座は、小型化、低背化を図るため薄くすることが望ましい。台座を薄くした中空構造を有する電子部品を多層基板に実装する場合、各端子の接続が不均一であると、外枠のひずみによる特性のばらつきや、実装の信頼性の低下を招く。   The pedestal to which the sensor chip having a hollow structure is bonded is preferably thin in order to reduce the size and height. When an electronic component having a hollow structure with a thin pedestal is mounted on a multi-layer substrate, uneven connection of terminals causes variation in characteristics due to distortion of the outer frame and a decrease in mounting reliability.

本発明は、かかる実情に鑑み、電子部品の各端子を略均一にバンプ接続することができる、電子部品実装構造を提供しようとするものである。   In view of such a situation, the present invention intends to provide an electronic component mounting structure capable of bump-connecting terminals of an electronic component substantially uniformly.

本発明は、上記課題を解決するために、以下のように構成した電子部品実装構造を提供する。   In order to solve the above-mentioned problems, the present invention provides an electronic component mounting structure configured as follows.

電子部品実装構造は、積層された絶縁層と、該絶縁層に配置された導体パターンとを備えた多層基板に、バンプを介して少なくとも一つの電子部品をフリップチップボンディングにより実装した電子部品実装構造である。前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層のうち前記バンプに最も近い第１の絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れている。   The electronic component mounting structure is an electronic component mounting structure in which at least one electronic component is mounted by flip chip bonding via a bump on a multilayer substrate having a laminated insulating layer and a conductor pattern disposed on the insulating layer. It is. When seen through in the stacking direction of the insulating layer, all the through holes formed in the first insulating layer closest to the bump among the insulating layers of the multilayer substrate are all the electronic components for mounting the electronic components. Away from the bump.

上記構成において、絶縁層の貫通孔には、例えば導体パターンに電気的に接続された層間接続導体等が配置される。第１の絶縁層において、貫通孔が形成された部分以外の部分は略平坦であり、貫通孔が形成された部分とそれ以外の部分との間には段差が生じる。これに対応して、電子部品を実装する面には凹凸が生じる。   In the above configuration, for example, an interlayer connection conductor electrically connected to a conductor pattern is disposed in the through hole of the insulating layer. In the first insulating layer, the portion other than the portion where the through hole is formed is substantially flat, and a step is generated between the portion where the through hole is formed and the other portion. Correspondingly, the surface on which the electronic component is mounted is uneven.

上記構成によれば、多層基板に電子部品を実装するための全てのバンプは、第１の絶縁層の貫通孔が形成された部分の直上部分以外の略平坦な部分に配置され、全てのバンプの高さが揃う。そのため、電子部品をフリップチップボンディングにより実装するとき、電子部品の各端子には略均一に力が作用するので、各端子を略均一にバンプ接続することができる。   According to the above configuration, all the bumps for mounting the electronic components on the multilayer substrate are arranged in a substantially flat portion other than the portion directly above the portion where the through hole of the first insulating layer is formed, and all the bumps All the heights are aligned. For this reason, when the electronic component is mounted by flip chip bonding, the force acts on each terminal of the electronic component substantially uniformly, so that each terminal can be bump-connected substantially uniformly.

したがって、実装された電子部品に不均一なストレスを与えることを防ぎ、実装時の不均一なひずみによる電子部品の特性のばらつき等を防ぐことができる。また、バンプごとの接続強度のばらつきが小さくなるので、信頼性の高い電子部品の実装が可能となる。   Accordingly, it is possible to prevent uneven stress from being applied to the mounted electronic component, and to prevent variations in the characteristics of the electronic component due to uneven distortion during mounting. In addition, since variation in connection strength for each bump is reduced, highly reliable electronic components can be mounted.

好ましくは、前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層のうち前記第１の絶縁層の前記電子部品とは反対側に隣接する第２の絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れている。   Preferably, when viewed in the stacking direction of the insulating layer, all of the insulating layers of the multilayer substrate formed on the second insulating layer adjacent to the opposite side of the first insulating layer from the electronic component. A through hole is separated from all the bumps for mounting the electronic component.

積層基板の電子部品を実装するための全てのバンプは、第２の絶縁層の貫通孔により凹凸が形成される可能性のある部分から離れて、配置される。したがって、電子部品の実装時の不均一なひずみによる、電子部品の特性のばらつき等を、より確実に防ぐことができ、一層、信頼性の高い電子部品の実装が可能となる。   All the bumps for mounting the electronic components of the multilayer substrate are arranged apart from the portion where the unevenness may be formed by the through hole of the second insulating layer. Therefore, variations in the characteristics of the electronic component due to non-uniform distortion during mounting of the electronic component can be more reliably prevented, and the electronic component can be mounted with higher reliability.

好ましくは、前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れている。   Preferably, when seen through in the stacking direction of the insulating layer, all the through holes formed in the insulating layer of the multilayer substrate are separated from all the bumps for mounting the electronic component.

積層基板の電子部品を実装するための全てのバンプは、積層基板の絶縁層の貫通孔により凹凸が形成される可能性のあるすべて部分から離れて、配置される。したがって、電子部品の実装時の不均一なひずみによる、電子部品の特性のばらつき等を、より一層、確実に防ぐことができ、さらに一層、信頼性の高い電子部品の実装が可能となる。   All the bumps for mounting the electronic components of the multilayer substrate are arranged apart from all the portions where the irregularities may be formed by the through holes of the insulating layer of the multilayer substrate. Therefore, variations in the characteristics of the electronic component due to non-uniform distortion during mounting of the electronic component can be prevented more reliably, and mounting of the electronic component with higher reliability can be achieved.

好ましくは、前記電子部品は、その内部に空間を有し、主要部が前記空間に浮いた状態で変位可能に支持されている。   Preferably, the electronic component has a space therein and is supported so as to be displaceable in a state in which a main part is floated in the space.

この場合、電子部品はバンプ接続の不均一に対して敏感であるので、前述した各構成は、特に好適である。   In this case, since the electronic component is sensitive to the unevenness of the bump connection, each configuration described above is particularly suitable.

本発明の電子部品実装構造は、電子部品の各端子を略均一にバンプ接続することができる。   The electronic component mounting structure of the present invention can bump-connect each terminal of the electronic component substantially uniformly.

以下、本発明の実施の形態について、図１〜図４を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to FIGS.

図１に模式的に示したように、多層基板１０は、複数の絶縁層１１〜１４と、複数の導電層２１〜２５とが交互に配置されている。なお、絶縁層と導電層の層数は、任意に選択することができる。   As schematically shown in FIG. 1, the multilayer substrate 10 has a plurality of insulating layers 11 to 14 and a plurality of conductive layers 21 to 25 arranged alternately. Note that the number of insulating layers and conductive layers can be arbitrarily selected.

各導電層２１〜２５には、導電材料を用いて所定の導体パターン（不図示）が形成されている。絶縁層１１〜１４の適宜位置には、貫通孔（ビアホール）１１ａ，１１ｂ；１２ａ，１２ｂ；１３ａが形成され、貫通孔１１ａ，１１ｂ；１２ａ，１２ｂ；１３ａの内部には、層間接続導体（ビアホール導体）３１〜３４が配置されている。ビアホール導体３１〜３４は、１又は２以上の絶縁層１１〜１４を貫通し、導電層２１〜２５の導体パターン（不図示）に電気的に接続されている。   Each conductive layer 21 to 25 is formed with a predetermined conductor pattern (not shown) using a conductive material. Through holes (via holes) 11a, 11b; 12a, 12b; 13a are formed at appropriate positions of the insulating layers 11 to 14, and interlayer connection conductors (via holes) are formed inside the through holes 11a, 11b; 12a, 12b; 13a. Conductors 31 to 34 are disposed. The via-hole conductors 31 to 34 penetrate one or more insulating layers 11 to 14 and are electrically connected to conductive patterns (not shown) of the conductive layers 21 to 25.

図２に示すように、多層基板１０の表面の凹凸状態を測定すると、符号４０を付して模式的に図示したように、絶縁層の１層目１１に形成されたビアホール導体３１による凸部４１、絶縁層の２層目１２に形成されたビアホール導体３２による凸部４２、絶縁層の１、２層目１１，１２に形成されたビアホール導体３４による凸部４３が、それぞれ形成されている。凸部４１〜４３以外の部分４４は、平坦である。   As shown in FIG. 2, when the unevenness state of the surface of the multilayer substrate 10 is measured, as shown schematically with reference numeral 40, a convex portion due to the via-hole conductor 31 formed in the first layer 11 of the insulating layer. 41, a convex portion 42 formed by the via-hole conductor 32 formed in the second layer 12 of the insulating layer, and a convex portion 43 formed by the via-hole conductor 34 formed in the first and second layers 11 and 12 of the insulating layer, respectively. . The portion 44 other than the convex portions 41 to 43 is flat.

そこで、図３に示すように、多層基板１０の表面に電子部品５０をフリップチップボンディングにより実装するための全てのバンプ５４，５５は、凸部４１〜４３から離れた平坦な部分４４に配置し、全てのバンプ５４，５５の直下部分に、絶縁層の１層目１１（すなわち、第１の絶縁層）に形成された貫通孔１１ａ，１１ｂと、絶縁層の２層目１２（すなわち、第２の絶縁層）に形成された貫通孔１１ａ，１１ｂが来ないようにする。換言すれば、絶縁層１１〜１４の積層方向（すなわち、図１〜図４において上下方向）に透視すると、絶縁層の１、２層目１１，１２に形成された全ての貫通孔１１ａ，１１ｂ；１２ａ，１２ｂが、電子部品５０を実装するための全てのバンプ５４，５５から離れるようにする。   Therefore, as shown in FIG. 3, all the bumps 54 and 55 for mounting the electronic component 50 on the surface of the multilayer substrate 10 by flip chip bonding are arranged in a flat portion 44 apart from the convex portions 41 to 43. The through holes 11a and 11b formed in the first layer 11 of the insulating layer (that is, the first insulating layer) and the second layer 12 of the insulating layer (that is, the first layer) are formed immediately below all the bumps 54 and 55. The through holes 11a and 11b formed in the second insulating layer are prevented from coming. In other words, when viewed in the stacking direction of the insulating layers 11 to 14 (that is, the vertical direction in FIGS. 1 to 4), all the through holes 11a and 11b formed in the first and second layers 11 and 12 of the insulating layer. And 12a and 12b are separated from all the bumps 54 and 55 for mounting the electronic component 50.

一般には、例えば図４に示すように、ビアホール導体３４の直上、すなわち凸部４３の上にバンプ５７を設けることが多い。しかし、端子５２の個数が多い電子部品５０の場合、すべてのバンプを凸部の上に設けるようとすると、絶縁層の１層目１１に多くの貫通孔を互いに接近して形成しなければならず、加工が困難になる。そのため、凸部４１〜４３がない平坦な部分４４にもバンプ５６を配置せざるを得ない。   In general, for example, as shown in FIG. 4, bumps 57 are often provided immediately above the via-hole conductor 34, that is, on the convex portion 43. However, in the case of the electronic component 50 having a large number of terminals 52, if all the bumps are provided on the convex portions, many through holes must be formed close to each other in the first layer 11 of the insulating layer. Therefore, processing becomes difficult. Therefore, the bumps 56 must be disposed on the flat portion 44 where the convex portions 41 to 43 are not present.

このように、平坦な部分４４と凸部４３とにバンプ５６，５７を設けた場合、バンプ５６，５７の高さには差δが生じる。そのため、熱と荷重と超音波振動を加えるフリップチップボンディングによって電子部品５０を多層基板１０に実装する際、電子部品５０の各端子５２に作用する力は不均一になる。電子部品５０が、中空構造を有する電子部品（すなわち、内部に空間を有し、主要部がその空間に浮いた状態で変位可能に支持されているセンサやスイッチ等の電子部品）である場合、電子部品５０の内部に生じた局所的なひずみによって、電子部品５０の特性にばらつきが生じる。また、電子部品５０と多層基板１０との接続強度がバンプ５６，５７ごとにばらつくため、実装の信頼性の低下を招く。   Thus, when the bumps 56 and 57 are provided on the flat portion 44 and the convex portion 43, a difference δ is generated in the height of the bumps 56 and 57. Therefore, when the electronic component 50 is mounted on the multilayer substrate 10 by flip chip bonding that applies heat, load, and ultrasonic vibration, the force acting on each terminal 52 of the electronic component 50 becomes non-uniform. When the electronic component 50 is an electronic component having a hollow structure (that is, an electronic component such as a sensor or a switch that has a space inside and is supported so as to be displaceable in a state in which the main part floats in the space), Variations in the characteristics of the electronic component 50 occur due to local strain generated inside the electronic component 50. In addition, since the connection strength between the electronic component 50 and the multilayer substrate 10 varies for each of the bumps 56 and 57, the mounting reliability is reduced.

一方、図３に示したように、凸部４１〜４３から離れた平坦な部分４４に、電子部品５０を実装するための全てのバンプ５４，５５を配置すると、バンプ５４，５５の高さが揃う。そのため、電子部品５０をフリップチップボンディングにより多層基板１０に実装するとき、電子部品５０の各端子５２には略均一に力が作用し、電子部品５０の各端子５２での接続状態が略均一になる。つまり、多層基板１０に、電子部品５０の各端子５２を略均一にバンプ接続することができる。   On the other hand, as shown in FIG. 3, when all the bumps 54 and 55 for mounting the electronic component 50 are arranged on the flat portion 44 apart from the convex portions 41 to 43, the height of the bumps 54 and 55 is increased. It's aligned. Therefore, when the electronic component 50 is mounted on the multilayer substrate 10 by flip chip bonding, a force is applied to each terminal 52 of the electronic component 50 substantially uniformly, and the connection state at each terminal 52 of the electronic component 50 is substantially uniform. Become. That is, each terminal 52 of the electronic component 50 can be bump-connected to the multilayer substrate 10 substantially uniformly.

その結果、電子部品５０の内部に不均一なストレスを与えることがなくなるので、電子部品５０が中空構造の電子部品であっても、特性にばらつきが生じることを防ぐことができる。また、バンプ５４，５５ごとの接続強度のばらつきが小さくなるので、信頼性の高い実装が可能となる。   As a result, non-uniform stress is not applied to the inside of the electronic component 50, so that even if the electronic component 50 is an electronic component having a hollow structure, it is possible to prevent variations in characteristics. Further, since the variation in connection strength between the bumps 54 and 55 is reduced, highly reliable mounting is possible.

例えば、厚さ約０．４ｍｍのガラス基板に、厚さ約５０〜６０μｍの中空構造を有するセンサチップが接合され、１６個の端子を有する角速度センサ（ＭＥＭＳジャイロセンサ）を、多層基板に実装する場合、バンプ高さのばらつきは、多層基板の反り程度まで小さくすることができるので、特性のばらつきを防ぐとともに、実装の信頼性を高めることができる。   For example, a sensor chip having a hollow structure with a thickness of about 50 to 60 μm is bonded to a glass substrate with a thickness of about 0.4 mm, and an angular velocity sensor (MEMS gyro sensor) having 16 terminals is mounted on the multilayer substrate. In this case, the variation in bump height can be reduced to the extent of warping of the multilayer substrate, so that the variation in characteristics can be prevented and the reliability of mounting can be improved.

多層基板によっては、絶縁層の２層目に形成された貫通孔（ビアホール）３２があっても、多層基板の実装面に凸部４２が実質的に形成されない（電子部品５０の実装に実質的に影響を与えない）ことがある。この場合には、電子部品５０をフリップチップボンディングするためのバンプ５４，５５の直下には、絶縁層の１層目１１に形成されたに貫通孔１１ａ，１１ｂのみが全くないようにするだけでよい。換言すれば、絶縁層１１〜１４の積層方向に透視すると、絶縁層の１層目に形成される全ての貫通孔が、電子部品５０を実装するための全てのバンプ５４，５５から離れるようにすればよい。   Depending on the multilayer substrate, even if there is a through hole (via hole) 32 formed in the second layer of the insulating layer, the convex portion 42 is not substantially formed on the mounting surface of the multilayer substrate (substantially for mounting the electronic component 50). May not be affected). In this case, only the through holes 11a and 11b are formed in the first layer 11 of the insulating layer just below the bumps 54 and 55 for flip chip bonding of the electronic component 50. Good. In other words, when viewed in the stacking direction of the insulating layers 11 to 14, all the through holes formed in the first layer of the insulating layer are separated from all the bumps 54 and 55 for mounting the electronic component 50. do it.

逆に、絶縁層の１、２層目より内側に形成された貫通孔（ビアホール）の影響で、多層基板の実装面に凸部が形成されることがある。この場合には、電子部品をフリップチップボンディングするためのバンプの直下には、貫通孔が全くないようにすることが好ましい。換言すれば、絶縁層１１〜１４の積層方向に透視すると、絶縁層１１〜１４に形成される全ての貫通孔１１ａ，１１ｂ；１２ａ，１２ｂ；１３ａが、電子部品５０を実装するための全てのバンプ５４，５５から離れていることが、好ましい。   Conversely, convex portions may be formed on the mounting surface of the multilayer substrate due to the influence of through holes (via holes) formed inside the first and second layers of the insulating layer. In this case, it is preferable that there are no through holes immediately below the bumps for flip chip bonding of the electronic component. In other words, when viewed in the stacking direction of the insulating layers 11 to 14, all the through holes 11a, 11b; 12a, 12b; 13a formed in the insulating layers 11 to 14 are all mounted to mount the electronic component 50. It is preferable to be away from the bumps 54 and 55.

多層基板の実装面に絶縁層の貫通孔によって凹部が形成される場合も、多層基板の実装面に絶縁層の貫通孔によって凸部が形成される場合と同様に、実装面から適宜層数分の絶縁層の貫通孔が、バンプの直下にないようにすればよい。すなわち、絶縁層の積層方向に透視すると、実装面から適宜層数分の絶縁層に形成される貫通孔が、電子部品を実装するための全てのバンプから離れているようにすればよい。   When the concave portion is formed by the through hole of the insulating layer on the mounting surface of the multilayer substrate, the number of layers from the mounting surface is appropriately set as in the case where the convex portion is formed by the through hole of the insulating layer on the mounting surface of the multilayer substrate. The through hole of the insulating layer should not be directly under the bump. That is, when seen through in the stacking direction of the insulating layers, the through holes formed in the insulating layers corresponding to the appropriate number of layers from the mounting surface may be separated from all the bumps for mounting the electronic components.

なお、本発明の電子部品実装構造は、上記した実施の形態に限定されるものではなく、種々変更を加えて実施することが可能である。   The electronic component mounting structure of the present invention is not limited to the above-described embodiment, and can be implemented with various modifications.

多層基板の模式断面図である。（実施例）It is a schematic cross section of a multilayer substrate. (Example) 多層基板の凹凸の説明図である。（実施例）It is explanatory drawing of the unevenness | corrugation of a multilayer substrate. (Example) 多層基板への電子部品の実装の説明図である。（実施例）It is explanatory drawing of mounting of the electronic component on a multilayer substrate. (Example) 多層基板への電子部品の実装の説明図である。（比較例）It is explanatory drawing of mounting of the electronic component on a multilayer substrate. (Comparative example) 多層基板の断面図である。（従来例）It is sectional drawing of a multilayer substrate. (Conventional example) 中空構造を有する電子部品の説明図である。（従来例）It is explanatory drawing of the electronic component which has a hollow structure. (Conventional example)

符号の説明Explanation of symbols

１０ 多層基板
１１〜１４ 絶縁層
１１ａ，１１ｂ 貫通孔
１２ａ，１２ｂ 貫通孔
１３ａ 貫通孔
４０ 表面
４１，４２，４３ 凸部
５０ 電子部品 DESCRIPTION OF SYMBOLS 10 Multilayer substrate 11-14 Insulating layer 11a, 11b Through-hole 12a, 12b Through-hole 13a Through-hole 40 Surface 41, 42, 43 Convex part 50 Electronic component

Claims (4)

積層された絶縁層と、該絶縁層に配置された導体パターンとを備えた多層基板に、バンプを介して少なくとも一つの電子部品をフリップチップボンディングにより実装した電子部品実装構造であって、
前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層のうち前記バンプに最も近い第１の絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れていることを特徴とする、電子部品実装構造。 An electronic component mounting structure in which at least one electronic component is mounted by flip-chip bonding on a multilayer substrate including a laminated insulating layer and a conductor pattern disposed on the insulating layer via a bump,
When seen through in the stacking direction of the insulating layer, all the through holes formed in the first insulating layer closest to the bump among the insulating layers of the multilayer substrate are all the electronic components for mounting the electronic components. An electronic component mounting structure characterized by being separated from a bump. 前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層のうち前記第１の絶縁層の前記電子部品とは反対側に隣接する第２の絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れていることを特徴とする、請求項１に記載の電子部品実装構造。   When viewed through in the stacking direction of the insulating layer, all through holes formed in the second insulating layer adjacent to the electronic component of the first insulating layer on the opposite side of the insulating layer of the multilayer substrate are 2. The electronic component mounting structure according to claim 1, wherein the electronic component mounting structure is separated from all the bumps for mounting the electronic component. 前記絶縁層の積層方向に透視すると、前記多層基板の前記絶縁層に形成された全ての貫通孔が、前記電子部品を実装するための全ての前記バンプから離れていることを特徴とする、請求項１に記載の電子部品実装構造。   When viewed through in the stacking direction of the insulating layer, all the through holes formed in the insulating layer of the multilayer substrate are separated from all the bumps for mounting the electronic component. Item 2. The electronic component mounting structure according to Item 1. 前記電子部品は、その内部に空間を有し、主要部が前記空間に浮いた状態で変位可能に支持されていることを特徴とする、請求項１、２又は３に記載の電子部品実装構造。   4. The electronic component mounting structure according to claim 1, wherein the electronic component has a space therein and is supported so as to be displaceable in a state in which a main part is floated in the space. .
JP2005376589A 2005-12-27 2005-12-27 Electronic component mounting structure Pending JP2007180248A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288658A (en) * 1995-04-18 1996-11-01 Mitsubishi Electric Corp Printed wiring board for bga package mount
JPH11330295A (en) * 1998-05-02 1999-11-30 Elliston Investment Pte Ltd Integrated circuit assembly and its forming method
JP2002094241A (en) * 2000-09-18 2002-03-29 Nippon Avionics Co Ltd Built-up printed wiring board
WO2005098359A1 (en) * 2004-04-07 2005-10-20 Murata Manufacturing Co., Ltd. Angular speed measuring equipment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288658A (en) * 1995-04-18 1996-11-01 Mitsubishi Electric Corp Printed wiring board for bga package mount
JPH11330295A (en) * 1998-05-02 1999-11-30 Elliston Investment Pte Ltd Integrated circuit assembly and its forming method
JP2002094241A (en) * 2000-09-18 2002-03-29 Nippon Avionics Co Ltd Built-up printed wiring board
WO2005098359A1 (en) * 2004-04-07 2005-10-20 Murata Manufacturing Co., Ltd. Angular speed measuring equipment

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