JPH0827709B2 - Multiplier type D / A converter - Google Patents

Description

The present invention relates to a D / A converter used in a servo circuit such as a motor, and more particularly to a D / A converter capable of correcting the loop gain of a control loop of the servo circuit. A converter.

[Prior Art] Conventionally, in a motor servo circuit such as a VTR, the loop gain of a control loop is optimized to prevent a motor rotation delay or overshoot.

FIG. 9 is a circuit diagram showing a control loop of a conventional motor servo circuit. In the figure, the rotation frequency of the motor 10 is
Waveform shaping circuit 14 detected by frequency generator (FG) 12
Is input to The waveform shaping circuit 14 outputs a pulse signal fg having a predetermined width for each cycle of the input frequency.

The pulse signal fg is input to the F / V conversion circuit 16, and the F / V conversion circuit 16 generates an output voltage corresponding to one cycle each time the input frequency (pulse) is repeated a predetermined number of times. This output voltage is serially output from the F / V conversion circuit 16, and is input to the D / A converter 18 as a pulse train corresponding to the input frequency, that is, as a voltage value (digital data) of m (m: integer) bits. .

This digital voltage value is converted into an analog voltage value by the D / A converter 18, and the motor drive amplifier (MDA) 2
Entered in 0. The MDA 20 drives the motor 10 to rotate at a predetermined speed based on the analog voltage value.

Now, in the above motor servo loop,
As described above, the loop gain of the control loop is changed by the load fluctuation of the motor 10, the rising, the constant speed rotation and the like. When changing the loop gain, the frequency of the clock signal CK and the preset value P in the F / V counter 22 of the F / V conversion circuit 16 are changed.

FIG. 10 is a timing chart showing the operation of the F / V conversion circuit 16. The pulse signal fg from the waveform shaping circuit 14 is (
10 (see FIG. 10A), and is input to the F / V counter 22 and the latch circuit 24. A clock signal CK1 for counting is input to the F / V counter 22 (see FIG. 10 (b)). The F / V counter 22 counts up in synchronization with the clock signal CK1 (see FIG. 10 (c)). At this time, the preset value P1 is given to the F / V counter 22 in advance,
A count value equal to or greater than the preset value P1 is accumulated as the digital value V1 between the rising edges of the pulse signal fg. The digital value V1 is transferred from the F / V counter 22 to the latch circuit 24 at the rising timing of the pulse signal fg. Then, the latched digital value V1 is D / D according to a predetermined transfer rate.
Output to the A converter 18.

Here, when the loop gain is set high, the clock signal CK2 having a higher frequency than the clock signal CK1 is input to the F / V counter 22, as shown in FIG. 10 (d). Therefore, the count-up operation in the F / V counter 22 becomes faster, and the tilt angle of the count changes as shown in FIGS. 10 (c) and 10 (e). Then, the clock signal GK
The preset value P2 corresponding to 2 is given to the F / V counter 22, and as described above, the digital value V2 converted from the input frequency (fg) to the voltage value is output to the D / A converter 18.

[Problems to be Solved by the Invention] By the way, as described above, when it is necessary to change the loop gain in the conventional servo circuit, the inclination angle of the count is changed by changing the frequency of the clock signal CK, and F / V corresponding to the frequency of R signal CK
It was necessary to change the preset value P of the counter 22. Therefore, when it is desired to switch a plurality of types of loop gain, it is necessary to have a plurality of preset values P of the F / V counter 22 in advance, and the ROM data becomes enormous.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is a D / A that can change a loop gain while fixing a clock signal and a preset value of an F / V counter. To provide a converter.

[Means for Solving the Problems] In order to achieve the above object, a D / A converter according to the present invention includes a capacitor that accumulates charges while corresponding to digital data sequentially input in bit units from a lower digit. D / A that includes a voltage value corresponding to the digital data
In the converter, a shift register that sequentially outputs bit data less than the most significant bit data of the digital data from the lower digit while synchronizing with the input read shift clock, and the number of read shift clocks input to this shift register A pulse generating circuit for multiplication that variably sets according to a desired multiplication value, and the bit unit data output from the shift register, when the multiplication value is other than 2 ⁿ times, the bit of the upper digit of this bit data An adder for adding data, an addition gate for inputting higher-order bit data to the adder when the multiplication value is other than 2 ⁿ times, latching the most significant bit data of the digital data, and synchronizing with the shift clock. The MSB latch that outputs this most significant bit data after finishing the addition operation
It is characterized by including.

[Operation] In the D / A converter of the present invention having the above configuration, the digit of the bit data can be moved in the vertical direction, and by this digit movement, the original data can be multiplied by 2 ⁿ .

Also, by adding the bit data of the upper digit to the bit data, it is possible to obtain (2 ⁿ × 1.5) times multiplication data.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a multiplication unit which is a characteristic constituent element in the multiplication type D / A converter of the present invention.

In the figure, 30 is a latch circuit, which is the F / V shown in FIG.
The digital value (data to be D / A converted) input from the conversion circuit 16 is latched. In this embodiment, from LSB to MSB,
For example, assume that 10-bit digital data is handled. 32
Is a shift register, which is a data latch register 32a corresponding to LSB to 9 bits of the latch circuit 30, an output register 32b grounded through a switch, an addition register 32c, and a virtual MSB register 32d corresponding to the MSB. It consists of and. Each data is input to the shift register 32 by a load pulse. A shift clock for reading is input to the shift register 32, and bit data of LSB to 9 bits excluding MSB is sequentially output from the lower digit in synchronization with the shift clock for reading.

An adder (1 bit full adder) 34 adds the bit data output from the output register 32b of the shift register 32 and the output data of the AND gate 36. The AND date 36 functions as the addition gate of the present invention. That is,
The terminal 38 of the AND gate 36, except when 2 ⁿ times the digital data latched in the latch circuit 30, for example, (2 ⁿ × 1.
5) “H” is input when multiplying.

At this time, the AND gate 36 outputs the bit data of the addition register 32c, that is, the bit data of the upper digit to the bit data of the output register 32b to the adder 34.
On the other hand, when multiplying by 2 ⁿ , "L" is input to the terminal 38 and the bit data of the addition register 32c is not input to the adder 34. The output of the adder 34 is sent as digital data to be converted via the switch 40 for MSB transfer to Sou
Input from the t output terminal 42 to the D / A converter shown in FIG.

Reference numeral 44 denotes an MSB latch, which outputs the MSB to the Sout output terminal 42 after the adder 34 completes the adding operation in synchronization with the shift clock. That is, the MSB is output from the Sout output terminal 42 when the MSB transfer clock is applied to the MSB transfer switch 40 via the D latch 46.

This MSB is combined with the output of the adder 34 described above,
Digital data to be converted to the D / A converter shown in FIG.
0 bit) Input as Sout. The latch circuit 30
The MSB is latched in the MSB latch 44 by the load pulse.

Reference numeral 48 denotes a multiplication pulse generation circuit, which generates pulse signals for controlling the multiplication operation of the present invention, such as the shift clock, load pulse, MSB transfer clock, gate pulse supplied to the terminal 38, and the like. In the present invention, this multiplication pulse generation circuit 48 variably sets the number of pulses of the read shift clock input to the shift register 34 according to the desired multiplication value that has been set, that is, the loop gain.

Reference numeral 50 is an OR gate for overflow detection, which detects an overflow when the MSB transfer clock is supplied to the D latch 52 and outputs a forced H signal. 54 is an OR gate for underflow, and the MSB transfer clock is D latch 56
When it is supplied to the
Output a signal.

FIG. 2 is a circuit diagram showing a D / A conversion section in the multiplication D / A converter of the present invention, and FIG. 3 is a timing chart thereof. The D / A converter of this embodiment is conventionally called a switched capacitor D / A converter, and supports digital data (Sout in this embodiment) sequentially input in bit units from the lower digit. While including the capacitor, it includes a capacitor for accumulating electric charge and generates a voltage value according to the digital data.

In FIG. 2, 60 is a D / A conversion pulse generation circuit,
The Sout and load pulse shown in Fig. 1 are input and the D / A
Generates various pulse signals required for conversion. The pulse generation operation in the D / A conversion pulse generation circuit 60 is performed in synchronization with the clock signal CK shown in FIG.

When the load pulse is input to the D / A conversion pulse generation circuit 60, first, the signal PIN1 shown in FIG. 3 (b) is output. PIN1 excites transistor Tr1 and capacitor C1
It acts as a reset signal to discharge the electric charge of.

On the other hand, signals P2 and N2 shown in FIGS. 3C and 3D corresponding to "1" and "0" of the digital data Sout are output from the D / A conversion pulse generation circuit 60. Signals P2 and N2 are output to excite transistors Tr2 and Tr3, respectively, and S
When out is "1", P2 is "L", and when Sout is "0", N2 is "H". Signals P2 and N2 charge capacitor C2 when Tr2 is ON, and capacitor C when Tr3 is ON.
Two discharges are made.

The charge of the capacitor C2 is distributed to the capacitor C1 by the switch SW1 which is closed and controlled for each bit. The control signal S1 of the switch SW1 is output in synchronization with the clock signal CK when the Tr2 and Tr3 are at rest, as shown in FIG. 3 (e).

In this way, the capacitor corresponding to the digital data Sout
The voltage value stored in C1 is connected to the buffer 62. Then, according to the present embodiment, the symbol S2 shown in FIG. 3 (f) is output at the time when the charge is accumulated for the 10-bit decimal data Sout.

The signal S2 closes the switch SW2 and charges the capacitor C3. The voltage value of the capacitor C3 is finally output as a D / A converted voltage value via the buffer 64.
Note that transistors Tr4 and Tr5 are provided to forcibly charge or discharge the capacitor C3.

Next, the operation of the multiplication unit in the multiplication type D / A converter of the present invention will be described with reference to FIGS.

Figure 4 is 1 times the digital data (2 ⁰⁾ times and 1.5 times (2
FIG. 9 is a state change diagram showing a multiplication operation in the case of ( ⁰ × 1.5 times). Note that A to J in the figure represent bit data of "1" or "0". When performing this multiplication, the multiplication pulse generation circuit 48 of FIG. 1 sets the number of pulses of the shift clock to 10, and further delays the first clock output timing by the clock.

First, when the load pulse is output when the MSB latch 44 and the shift register 3 are in the initial state of all 0s (first row), the MSB latch 44 and the shift register 32 are set to the second row. Bit data is read into. The bit data read into the shift register 32 is shifted by the shift clock from the fourth row since the shift clock has a time lag of one clock.

When 10 shift clocks are transmitted, overflow is detected and the MSB latch 44 outputs the most significant bit data A to the Sout output terminal. Where D / in Fig. 2
Ten bit data A to J counting from A are input to the A conversion pulse generation circuit 60.

This 10-bit data is equal to the original digital data A to J and is equal to the multiplication result of 2 ⁰ = 1.0.

On the other hand, when performing 2 ⁰ × 1.5 times multiplication, the gate pulse "H" is given to the terminal 38, multiplication data A, 0 + B, B + C,
…, I + J ”is obtained. This multiplication data will be considered below. For example, the original digital data BJ
Is 000001010 (= 10), the multiplication data is 000001111
(= 15), and a multiplication result of 1.5 times is obtained.

In the digital data, the bit data A is, for example, a flag bit indicating positive or negative polarity, and indicates positive when the data A = 1 and negative when A = 0 as shown in FIG. Then, the bit data B to J, which corresponds to 2 ⁹ = 512 gradation, respectively positive and negative.

FIG. 5 is a state change diagram showing a multiplication operation when digital data is doubled (2 ¹ ) times and tripled (2 ¹ × 1.5 times). When performing this multiplication, the multiplication pulse generation circuit 48 of FIG. 1 sets the number of pulses of the shift clock to 9, and further delays the initial clock output timing by 2 clocks.

First, when the load pulse is output when the MSB latch 44 and the shift register 3 are in the initial state of all 0s (first row), the MSB latch 44 and the shift register 32 are set to the second row. Bit data is read into. The bit data read into the shift register 32 is shifted by the shift clock from the fifth row since the shift clock has a time lag of 2 clocks.

When nine shift clocks are sent, overflow is detected and the MSB latch 44 outputs the most significant bit data A to the Sout output terminal. Where D / in Fig. 2
Ten bit data A, C to J, 0 counting from A are input to the A conversion pulse generation circuit 60.

This multiplication data will be considered below. For example, if the original digital data B to J is 000000101 (= 5), the multiplication data is 000001010 (= 10), and the multiplication result of 2.0 times is obtained.

On the other hand, when multiplying 2 ¹ × 1.5 = 3.0 times, the gate pulse “H” is given to the terminal 38 and the multiplication data A, B + C, C +
D, ... J + 0 is obtained.

This multiplication data will be considered below. For example,
Original digital data B to J is 000000101 (= 5)
Then, the multiplication data becomes 000001111 (= 15), which is 3.0
Double multiplication result is obtained.

Here, as is apparent from FIG. 8, for example, when a multiplication of 2 times is performed, the multiplication data for 256 becomes 512, and since there is no data corresponding to the subsequent multiplication data, forcible H or It is specified as 512 by compulsory L.

6 is a state change diagram showing a multiplication operation for four times the digital data (2 ^twice), and 6 times (2 ² × 1.5 fold). When performing this multiplication, the multiplication pulse generation circuit 48 of FIG. 1 sets the number of pulses of the shift clock to 8 and further delays the first clock output timing by 3 clocks.

First, when the load pulse is output when the MSB latch 44 and the shift register 3 are in the initial state of all 0s (first row), the MSB latch 44 and the shift register 32 are set to the second row. Bit data is read into. The bit data read into the shift register 32 is shifted by the shift clock from the sixth row since the shift clock has a time lag of 3 clocks.

When eight shift clocks are transmitted, overflow is detected and the MSB latch 44 outputs the most significant bit data A to the Sout output terminal. Where D / in Fig. 2
Ten bit data A, D to J, 0, 0 counting from A are input to the A conversion pulse generation circuit 60.

This multiplication data will be considered below. For example, if the original digital data B to J is 000000111 (= 3), the multiplication data is 000001100 (= 12), and the multiplication result of 4.0 times is obtained.

On the other hand, when multiplying 2 ² × 1.5 = 6.0 times, the gate pulse “H” is given to the terminal 38 and the multiplication data A, C + D, D +
E, ... J + 0,0 is obtained. This multiplication data will be considered below. For example, the original digital data BJ
If 000000011 (= 3), the multiplication data is 000010010
(= 18), and a multiplication result of 6.0 times is obtained.

Figure 7 shows digital data 0.5 times (2 ^-1 times) and 0,75 times.
FIG. 9 is a state change diagram showing a multiplication operation when multiplying (2 ⁻¹ × 1.5 times). When performing this multiplication, the multiplication pulse generation circuit 48 of FIG. 1 sets the number of pulses of the shift clock to 11, and does not delay the clock.

First, when the load pulse is output when the MSB latch 44 and the shift register 3 are in the initial state of all 0s (first row), the MSB latch 44 and the shift register 32 are set to the second row. Bit data is read into. The bit data read into the shift register 32 is shifted from the third row by the first shift clock.

When 11 shift clocks are sent, overflow is detected and the MSB latch 44 outputs the most significant bit data A to the Sout output terminal. Where D / in Fig. 2
Ten bit data A, O, B to I counting from A are input to the A conversion pulse generation circuit 60.

This multiplication data will be considered below. For example, if the original digital data B to J is 000001110 (= 14), the multiplication data will be 000000111 (= 7), and a multiplication result of 0.5 times can be obtained.

On the other hand, when multiplying by 2 ^-1 × 1.5 = 0.75 times, pin 38
Gate pulse “H” is given to the multiplication data A, 0,0 +
B, B + C, ... H + I are obtained. This multiplication data will be considered below. For example, the original digital data B ~
If J is 000010000 (= 16), the multiplication data is 0000011
It becomes 00 (= 12), and a 0.75 times multiplication result is obtained.

By carrying out the above multiplication, as shown in FIG. 8, it is possible to obtain multiplication data of 2 ⁿ times or (2 ⁿ × 1.5) times. By changing the multiplication data in this way, the loop gain in the control loop can be changed. Therefore, it is not necessary to prepare a plurality of F / V conversion preset values in ROM as described in the prior art.

In the above embodiment, the multiplication type D / A converter of the present invention is applied to the servo circuit, and the configuration for correcting the loop gain is illustrated, but the present invention is not limited to the above configuration.
For example, it can be applied to a signal processing circuit that amplifies digital data, a computer, or the like.

[Effects of the Invention] As described above, according to the multiplication type D / A converter of the present invention, it is possible to convert the original data into two at the digital data stage.
It can be multiplied by ⁿ times (2 ⁿ × 1.5), and the loop gain of the control loop can be variably set in correspondence with the multiplication value of this multiplication data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a multiplication unit which is a characteristic constituent element in the multiplication type D / A converter of the present invention, and FIG. 2 is a D / A conversion unit in the multiplication type D / A converter of the present invention. schematic, Figure 3 (a) ~ (f) are timing charts for explaining the operation of FIG. 2, FIG. 4 is 1 times the digital data (2 ^0-fold) and 1.5 (2 ⁰
× 1.5) State change diagram showing the multiplication operation when multiplying, Fig. 5 shows that the digital data is doubled (2 ¹ ×) and tripled (2 ¹ ×)
State change diagram showing the multiplication operation when 1.5) multiplied, FIG. 6 is four times the digital data (2 ^twice), and 6 times (2 ² ×
1.5) State change diagram showing multiplication operation when multiplying, Figure 7 is a state change diagram showing multiplication operation when multiplying digital data by 0.5 times (2 ^-1 times) and 0.75 times (2 ^-1 × 1.5) FIG. 8 is a characteristic diagram showing an example of multiplication data according to the present invention, FIG. 9 is a circuit diagram showing a control loop of a conventional motor servo circuit, and FIGS. 10 (a) to 10 (e) are F of FIG. 6 is a timing chart for explaining the operation of the / V conversion circuit. 32 …… Shift register 34 …… Adder (1 bit full adder) 36 …… AND gate (addition gate) 44 …… MSB latch 48 …… Multiplication pulse generator

Claims (1)

[Claims] 1. A D / A converter for generating a voltage value according to the digital data, which includes a capacitor for accumulating charges while corresponding to digital data sequentially input from the lower digit in bit units A shift register that sequentially outputs the bit data less than the most significant bit data of the digital data from the lower digit while synchronizing with the read shift clock, and the number of read shift clocks input to this shift register according to a desired multiplication value. And a pulse generator for multiplication that variably sets, and an adder that adds the bit data of the upper digit of the bit data to the bit-unit data output from the shift register when the multiplication value is other than 2 ⁿ times. , an addition gate the multiplication value to input the bit data of the upper digits when other than 2 ⁿ times the adder, the digital Latches the most significant bit data of over data,
An MSB latch that outputs the most significant bit data after the addition operation in synchronization with the shift clock is completed, and a multiplication type D / A converter.