JPH08274343A - Insulated-gate semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain an insulated-gate semiconductor device whose high breakdown strength is realized in a small device area as a high-breakdown-strength MOS and whose high breakdown strength and high integration accuracy are realized in a gate overlap LDDMOS by a method wherein a gate electrode is formed in a shape in which a space obtained as a result of a three- dimensional SOI structure is filled. CONSTITUTION: An SiO2 film 121 is formed on the inner surface of a groove part formed in a part of a silicon(Si) substrate 100, and a channel region 172 (P<-> ) and a lightly doped region 176 (n<-> ) in an LDD part are formed on a silicon single-crystal layer at the groove part. Then, a gate insulating film 180 is formed on them, and a polysilicon gate electrode 181 is formed in a shape to fill the groove. That is to say, a high-breakdown-strength MOS transistor comprises a U-shaped three-dimensional SOI structure, the LDD part is arranged in a part of the longitudinal part and the horizontal part of the three-dimensional structure, a plane occupied area is made extremely small, the LDD part is made long, and a high withstand voltage is achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a semiconductor device such as a power MOS which requires a high breakdown voltage and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example of the structure of a conventional high breakdown voltage MOS transistor is shown in FIGS. 7 (a) and 7 (b).

The MOS transistor shown in the figure is an SOI
(LDD (lightly doped Dor) using a (Silicon On Insulator) substrate
It is a lateral n-channel enhancement MOS device having an ein) structure. The MOS transistor shown in FIG. 10A is formed on the insulating layer 1100 provided on the surface of the silicon substrate 1000, and is characterized by a long LDD portion (that is, a low impurity concentration) in order to realize a high breakdown voltage. It has a high resistance region) 1400.

Further, the MOS transistor shown in FIG. 1B is a device adopting a gate overlap LDD structure. That is, the LDD portions (low-impurity-concentration high-resistance regions) 1300a and 1300b are provided so as to overlap the polysilicon gate electrode 1700 to achieve high integration and high breakdown voltage.

Such gate-overlapped L
The DD portion is generally formed by an oblique ion implantation method, which is a simple and easy-to-control method.

[0006]

The above-mentioned conventional technique has the following problems.

(1) In the LDD structure MOS transistor of FIG. 7A, a long LDD portion must be formed in order to realize a high breakdown voltage, and therefore the device occupies a very large area. There is a problem that

(2) The LDD portion of the conventional gate overlap LDDMOS transistor shown in FIG. 7B is generally formed by using an oblique ion implantation method. It is difficult to form the lap LDD portion, and the LDD has a long distance.
Even if the part is molded, the problem is that the area of the device becomes large.

The present invention has been made in view of the above problems, and an object thereof is to realize a high breakdown voltage with a small device area in a high breakdown voltage MOS, and a conventional gate overlap LDDMOS. To achieve higher breakdown voltage and higher integration.

Another object is to provide a process technology capable of efficiently producing these devices.

[0011]

The present invention which achieves the above object has the following constitution.

(1) In the insulated gate semiconductor device of the present invention according to claim 1, a three-dimensional SOI is formed on a part of a silicon substrate.
(Silicon On Insulator) structure is formed, and an impurity introduction region and a channel region forming a part of an insulated gate transistor are provided in a silicon layer on an insulating layer forming this three-dimensional SOI structure. A gate insulating film is formed on the gate insulating film, a gate electrode is formed on the gate insulating film, and the gate electrode is provided so as to fill a space obtained as a result of the three-dimensional SOI structure. Is characterized by.

(2) In the insulated gate semiconductor device according to the second aspect of the present invention, a three-dimensional SOI structure is formed on a part of the silicon substrate, and the three-dimensional SOI structure is a part of the silicon substrate. A groove portion having a side wall perpendicular to the surface of the silicon substrate, an insulating layer is provided on the inner surface of the groove portion, and a silicon layer is further provided on the insulating layer. A channel region is provided in a portion along a side wall perpendicular to the surface of the silicon substrate, a low impurity concentration region that is connected to the channel region is provided in the groove, and is further connected to the low impurity concentration region. A high impurity concentration region is provided to extend on the silicon substrate, a gate insulating film is formed on the channel region, and the groove portion is filled in contact with the gate insulating film. It is characterized in that the sea urchin gate electrode becomes formed.

(3) The present invention according to claim 3 provides the method according to claim 1 or 2, wherein the insulated gate semiconductor device is LDD (l
It is a MOS transistor having a lightly doped drain structure.

(4) In the insulated gate semiconductor device according to the present invention of claim 4, a three-dimensional SOI structure is formed on a part of the silicon substrate, and the three-dimensional SOI structure is a part of the silicon substrate. A groove portion having a side wall perpendicular to the surface of the silicon substrate, an insulating layer is provided on the inner surface of the groove portion, and a silicon layer is further provided on the insulating layer. , A channel region is provided in a portion along the bottom of the groove, and a low impurity concentration region connected to the channel region is provided in a portion along a side wall perpendicular to the surface of the silicon substrate. A high impurity concentration region connected to the concentration region is provided to extend on the silicon substrate, a gate insulating film is formed on the channel region, and the groove portion is formed in contact with the gate insulating film. It is characterized in that the gate electrode to Hama is formed.

(5) In the insulated gate type semiconductor device of the present invention according to claim 5, the insulated gate type semiconductor device according to claim 4 is an LDD (lightly doped dorei).
n) structure, the low impurity concentration region is characterized in that the LDD structure is formed so as to overlap with the gate electrode. (6) In the method for manufacturing an insulated gate semiconductor device according to the present invention of claim 6, a part of the silicon substrate whose surface is covered with an insulating film is provided with a sidewall substantially perpendicular to the surface of the silicon substrate. Forming a groove portion having a groove, and forming an insulating layer on the inner surface of the groove portion; forming an amorphous silicon layer on the insulating layer formed on the inner surface of the groove portion; and crystallizing the amorphous silicon layer. A step of forming a crystalline silicon layer by an ion implantation method including a portion of the crystalline silicon layer along a sidewall of the groove portion substantially perpendicular to the surface of the silicon substrate. And forming an impurity introduction layer, the impurity introduction layer having an impurity concentration determined by the impurity introduction is used as an active layer of an insulated gate transistor. Characterized in that the production of insulated gate transistors by using Te.

(7) A method of manufacturing an insulated gate semiconductor device according to a seventh aspect of the present invention is directed to a part of a silicon substrate whose surface is covered with an insulating film and is substantially perpendicular to the surface of the silicon substrate. Forming a groove having a side wall, and forming an insulating layer on the inner surface of the groove, and forming an opening in a part of the insulating film covering the surface of the silicon substrate so that a part of the silicon substrate is formed. A step of forming an exposed seed region, a step of forming an amorphous silicon layer on the seed region and an insulating layer provided on the inner surface of the groove, and by performing a heat treatment, the seed in the amorphous silicon layer is formed. Solid Phase Epitaxial Growth Starting from Region
y; SPE) to obtain a single crystal silicon layer, and ion implantation including a portion of the single crystal silicon layer along a sidewall substantially perpendicular to the surface of the silicon substrate in the groove portion. Impurities by the method,
And a step of forming an impurity introduction layer, wherein the impurity introduction layer having an impurity concentration determined by the impurity introduction is used as an active layer of the insulated gate transistor to manufacture an insulated gate transistor. To do.

(8) The method of manufacturing an insulated gate semiconductor device according to the present invention is the method of manufacturing an insulated gate type semiconductor device according to the sixth or seventh aspect, wherein the impurity introduction layer is an LDD (l) of an insulated gate transistor.
It is characterized in that an insulated gate transistor having an LDD structure is manufactured by using the layer as a layer forming a lightly doped drain structure.

[0019]

[Action]

(1) According to the present invention described in claim 1, a power device with higher breakdown voltage and higher integration can be obtained by utilizing the vertical region in the three-dimensional SOI structure.

(2) According to the present invention as set forth in claims 2 and 3, due to the operation illustrated in FIG. 8, the occupied area can be reduced and the LDD portion can be designed more freely.

In other words, the planar low impurity concentration layer having a length W1 formed in the Y1 region of FIG. 8 has an extremely large layout area in plan view in the Y2 and Y3 regions using the three-dimensional structure. It can be reduced in size. In the invention of this claim, the LDD structure is formed by utilizing such an action. In FIG. 8, the underlying insulating film forming the SOI structure is omitted for convenience.

(3) According to the present invention described in claims 4 and 5, the occupied area is reduced and the gate overlap LDD portion can be designed more freely by the action as illustrated in FIG. .

That is, in the conventional planar MOS structure as shown on the left side of FIG. 9, the LDD portion (LD1) is formed by performing ion implantation from the oblique direction of the gate G1. There is a limit to the length of the part.

On the other hand, the three-dimensional structure (which is constituted by the groove portion in this figure) as shown on the right side of FIG.
When the high resistance region (LD2) is formed in the vertical direction (vertical side wall portion) and the gate electrode G2 is configured to fill the groove, the high resistance region (LD2) having a sufficient length is overlapped with the gate. ) Can be formed.

The high resistance region (LD2) can be formed not only on the vertical side wall portion but also on the bottom portion (horizontal direction) portion of the groove so as to be connected, whereby a high breakdown voltage can be achieved. Note that in FIG. 9, the underlying insulating film forming the SOI structure is omitted for convenience.

(4) In the present invention according to claims 6, 7 and 8, a three-dimensional SOI structure is formed by recrystallizing amorphous, and impurity introduction including a side wall portion (vertical direction portion) is performed by an oblique ion implantation method. To manufacture the device. In claim 7, recrystallization of amorphous is performed by solid phase epitaxial growth (SPE).

By this manufacturing method, it is possible to efficiently manufacture an extremely compact device while maximizing the advantages of the ion implantation method having a high impurity concentration controllability.

[0028]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an embodiment (high breakdown voltage MOS) of the semiconductor device of the present invention.

In this embodiment, the silicon (Si) substrate 10 is used.
A groove is provided in a part of 0, and SiO is formed on the inner surface of the groove.
_{The two} films 121 are formed, and the channel region 172 (p ⁻ ) and the low impurity concentration region 176 (n ⁻ ) in the LDD portion are formed in the silicon single crystal layer in this groove.

Then, this channel region 172 (p ⁻ )
Then, the gate insulating film 180 is formed on the low impurity concentration region 176 (n ⁻ ) in the LDD portion, and the polysilicon gate electrode 181 is provided so as to fill the groove.
In the figure, reference numeral 174 (n ⁺ ) is a source region which is a high concentration impurity region, reference numeral 175 (n ⁺ ) is a drain region which is a high concentration impurity region, and reference number 120
Is a surface insulating film, and reference numeral 200 is an interlayer insulating film (B
PSG; Borophospho Silicate
Glass) and reference numeral 190 is an Al electrode.

The channel region 172 (p ⁻ ) is formed along the inner wall surface on the left side of the figure, and the low impurity concentration region 176 (n ⁻ ) in the LDD portion is formed along the bottom surface of the groove and the inner wall surface on the right side. There is.

That is, the high breakdown voltage MOS transistor of this embodiment has a U-shaped three-dimensional SOI structure, and LDD
The part is located in the vertical part and part of the horizontal part of the three-dimensional structure, while occupying a very small area on a plane,
The LDD portion is lengthened to increase the breakdown voltage.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be explained. Figure 2 shows the gate overlap LD
The structural example of a DMOS transistor is shown, and it is structurally the same as the example of FIG. Therefore, the same or corresponding parts as in FIG. 1 are designated by the same reference numerals.

The difference of this embodiment from the embodiment of FIG.
DD portions (high resistance regions 176 and 177) are provided on both sides of the inner wall surface (vertical portion) of the groove portion, and the channel region 17 is formed.
2 (p ⁻ ) is provided at the bottom of the groove.

In this embodiment, in order to effectively utilize the vertical portion of the three-dimensional structure, the LDD portion (high resistance region 1) has a sufficient overlap with the polysilicon gate electrode 181.
76,177) can be formed.

Next, an example of a method of manufacturing the device structure shown in FIGS. 1 and 2 will be described with reference to FIGS. 3, 4 and 5.

FIG. 3 is a process common to the structures of FIGS. 1 and 2, FIG. 4 is a process for making the structure of FIG. 1 following the process of FIG. 3, and FIG. 5 is a process of FIG. Is a process for creating the structure of FIG.

First, the process of FIG. 3 will be described.

As shown in step (a) of FIG. 3, a part of the Si substrate 100 is subjected to photolithography and RIE (Rea).
The groove 50 is formed by etching to a desired depth by active ion etching or the like.

Next, as shown in step (b) of FIG. 3, after forming an insulating film 120 to be a base, a part of the insulating film is etched by photolithography and RIE to remove S.
A portion where the surface of the i substrate is exposed (a portion that becomes a seed crystal in solid phase epitaxial growth, hereinafter referred to as a seed portion) is formed.

Next, as shown in step (c) of FIG. 3, an amorphous silicon layer is formed on the inner surface of the groove 50 and the surface of the silicon substrate 100, and then a heat treatment is performed at about 600 ° C. Solid phase epitaxial growth is caused from the seed portion 130 as a starting point to form a recrystallized layer (single crystal layer) 150.

That is, solid phase epitaxial growth proceeds in the vertical and horizontal directions starting from the seed portion by the heat treatment, and amorphous silicon is monocrystallized from the seed crystal portion, and finally the silicon single crystal (SPE film) 150.
Is obtained.

For this solid phase epitaxial growth (SPE), the method previously proposed by the applicant of the present application (the technique disclosed in Japanese Patent Application No. 6-193604) can be used.

In this way, a U-shaped three-dimensional SOI structure is formed by the SPE method, and subsequently, as shown in step (d) of FIG. 3, a device isolation region 160 is formed and a low impurity concentration is obtained by channel impurity diffusion. Then, the p-type impurity introduced layer 170 and the gate insulating film 180 are formed.

Next, the process of FIG. 4 will be described.

First, as shown in step (a) of FIG. 4, for example, oblique ion implantation of arsenic (As) (implantation perpendicular to the upper left direction and implantation perpendicular to the left) is performed to form vertical and horizontal portions of the groove. An LDD portion (171, 173) is formed in part.

Thereafter, as shown in step (b) of FIG.
A polysilicon gate electrode 181 is formed, ions are implanted into the source and drain regions using this as a mask,
A source layer 174 and a drain layer 175 are formed.

Subsequently, an interlayer insulating film (BPSG) 200
And a metal wiring 190 such as Al is formed, and the high breakdown voltage M of FIG.
OS device is completed.

Next, the process of FIG. 5 will be described.

Following the process of FIG. 3, first of all, FIG.
As shown in the step (a) of step (a), for example, oblique ion implantation of arsenic (As) (implantation in the direction perpendicular to the implantation from the diagonally left upper side and the implantation from the diagonally right upper side) is performed to form vertical portions on both sides of the groove. Low-concentration impurity region (n ⁻ ) 1 including both side wall parts
71 is formed. At this time, no impurities are introduced into the bottom of the groove, and this portion becomes the channel region 172.

Thereafter, as shown in step (b) of FIG.
A polysilicon gate electrode 181 is formed, ions are implanted into the source and drain regions using this as a mask,
Source layers 174 and 175 are formed.

Subsequently, an interlayer insulating film (BPSG) 200
Then, a metal wiring 190 such as Al is formed, and the MOS device having the gate overlap LDD structure of FIG. 2 is completed.

Although the embodiments of the present invention for MOS transistors have been described above, the present invention is not limited to this, and can be applied to other insulated gate semiconductor devices.

FIG. 6 shows an I having an LDD structure similar to that of FIG.
GBT (Insulated Gate Bipolar)
FIG. 3 is a diagram showing a part of the method for producing r Transistar).

In FIG. 6A, similar to the step (a) in FIG. 4, for example, oblique ion implantation of arsenic (As) (implantation perpendicular to the upper left direction and implantation perpendicular to the left) is performed to form a vertical groove. LDD portions (171, 173) are formed on the portion and a portion of the horizontal portion.

Thereafter, as shown in step (b) of FIG.
A polysilicon gate electrode 181 is formed, and using this as a mask, first, n-type impurities are introduced into the source region to form n ^+.
A source region 174 is formed. Then, next, by performing ion implantation of a p-type impurity (for example, boron) having a conductivity type opposite to that of the source region into the drain region 179 of the MOS transistor, an IGBT can be formed.

In the above embodiment, the three-dimensional SOI is used.
Although SPE was used for forming the structure, the present invention is not limited to this, and a method such as laser irradiation or X-ray irradiation can be adopted as an amorphous recrystallization method.

Further, although the n-type MOS transistor has been described as an example in the above description of the embodiments, the present invention can be similarly applied to the p-type MOS transistor of the opposite conductivity type.

Further, the high withstand voltage MOS transistor and the gate overlap MOS transistor of the present invention can be formed on the substrate at the same time. Therefore, by using the present invention, a high withstand voltage and highly integrated intelligent power LSI which has never been seen in the past. Can also be manufactured.

[0061]

As described above, according to the present invention, the following effects can be obtained.

(1) According to the present invention described in claim 1, by utilizing the vertical region in the three-dimensional SOI structure, a power device with higher breakdown voltage and higher integration can be obtained.

(2) In the present invention according to claims 2 and 3, the LDD portion is a vertical portion of a U-shaped three-dimensional SOI structure,
Alternatively, the LDD portion can be formed at an arbitrary distance by using oblique ion implantation, which is a simple and highly controllable method for forming the LDD portion, by arranging the LDD portion in a part of the vertical portion and the horizontal portion. A high breakdown voltage MOS can realize a high breakdown voltage with a small device area.

(3) In the present invention as set forth in claims 4 and 5, by producing a U-shaped three-dimensional SOI structure and disposing the LDD portion in the vertical direction portion of the U-shaped three-dimensional SOI structure,
Using the oblique ion implantation method, which is a simple and easy-to-control method for LDD partial molding, the gate-overlapped LDD part can be molded at an arbitrary distance, and higher breakdown voltage and higher integration than ever can be realized. .

(4) In the present invention according to claims 6, 7 and 8, a three-dimensional SOI structure is formed by recrystallizing amorphous, and impurity introduction including a side wall portion (vertical direction portion) is performed by oblique ion implantation. To manufacture the device. In claim 7, recrystallization of amorphous is performed by solid phase epitaxial growth (SPE).

By this manufacturing method, it is possible to efficiently manufacture an extremely compact device while maximizing the advantages of the SOI technology and the ion implantation method having a high impurity concentration controllability.

(5) Furthermore, the high withstand voltage MOS transistor and the gate overlap MOS transistor of the present invention can be formed on the substrate at the same time. Therefore, by using the present invention, a high withstand voltage and a high integration which has never been obtained can be obtained. It is possible to manufacture an intelligent power LSI.

[0068]

[Brief description of drawings]

FIG. 1 is a sectional view showing the configuration of an embodiment of the present invention.

FIG. 2 is a sectional view showing the configuration of another embodiment of the present invention.

3 (a) to 3 (d) are views showing respective manufacturing steps of processes common to the devices shown in FIGS. 1 and 2;

4 (a) and (b) are diagrams showing a process for producing the device of FIG. 1 following the process of FIG. 3 respectively.

5 (a) and 5 (b) are diagrams showing a process for making the device of FIG. 2 following the process of FIG. 3 respectively.

6 (a) and 6 (b) are diagrams showing a process for producing an IGBT, following the process of FIG. 3 respectively.

7A and 7B are cross-sectional views showing a structure of a conventional example, respectively.

FIG. 8 is a supplementary diagram for explaining the characteristics of the present invention.

FIG. 9 is a supplementary view for explaining the characteristics of the present invention.

[Explanation of symbols]

100 Silicon (Si) substrate 120,121 SiO ₂ film 172 Channel region 174,175 High impurity concentration (n ⁺ ) region 176 Low impurity concentration (n ⁻ ) region 180 Gate insulating film 181 Polysilicon gate 190 Metal electrode such as aluminum 200 Interlayer insulation film (BPSG)

Claims (8)

[Claims] 1. A three-dimensional SOI on a part of a silicon substrate.
(Silicon On Insulator) structure is formed, and an impurity introduction region and a channel region forming a part of the insulated gate transistor are provided in the silicon layer on the insulating layer forming this three-dimensional SOI structure. A gate insulating film is formed on the gate insulating film, a gate electrode is formed on the gate insulating film, and the gate electrode is provided in a form that fills a space obtained as a result of the three-dimensional SOI structure. A characteristic insulated gate semiconductor device. 2. A three-dimensional SOI on a part of a silicon substrate.
A structure is formed, and this three-dimensional SOI structure has a groove portion having a side wall perpendicular to the surface of the silicon substrate in a part of the silicon substrate, and an insulating layer is provided on the inner surface of the groove portion. It is formed by providing a silicon layer on this insulating layer, a channel region is provided in a portion of the silicon layer along a side wall perpendicular to the surface of the silicon substrate, and a low impurity that is connected to the channel region is provided. A concentration region is provided in the groove, and a high impurity concentration region connected to the low impurity concentration region is provided so as to extend on the silicon substrate, and a gate insulating film is formed on the channel region. An insulated gate semiconductor device having a gate electrode formed in contact with an insulating film to fill the groove. 3. The insulated gate semiconductor device comprises an LDD (l
3. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is a MOS transistor having a lightly doped drain structure. 4. A three-dimensional SOI on a part of a silicon substrate.
A structure is formed, and this three-dimensional SOI structure has a groove portion having a side wall perpendicular to the surface of the silicon substrate in a part of the silicon substrate, and an insulating layer is provided on the inner surface of the groove portion. A silicon layer is formed on the insulating layer, a channel region is provided in a portion of the silicon layer along the bottom of the groove, and a low impurity concentration region connected to the channel region is formed in the silicon substrate. A high impurity concentration region that is provided along a side wall perpendicular to the surface and that is connected to the low impurity concentration region extends over the silicon substrate, and a gate insulating film is formed on the channel region. An insulated gate semiconductor device is formed, in which a gate electrode is formed so as to contact the gate insulating film and fill the groove. 5. The insulated gate semiconductor device comprises an LDD (l
A MOS transistor having a lightly doped drain structure, wherein the low impurity concentration region overlaps with the gate electrode.
The insulated gate semiconductor device according to claim 4, wherein the insulated gate semiconductor device has a DD structure. 6. A groove portion having a sidewall substantially perpendicular to the surface of the silicon substrate is formed in a part of the silicon substrate whose surface is covered with an insulating film, and an insulating layer is formed on the inner surface of the groove portion. A step of forming, a step of forming an amorphous silicon layer on the insulating layer formed on the inner surface of the groove part, a step of crystallizing the amorphous silicon layer to form a crystalline silicon layer, the crystal An impurity is introduced by an ion implantation method to include a portion of the silicon layer having a property along the side wall substantially perpendicular to the surface of the silicon substrate in the groove portion,
And a step of forming an impurity introduction layer, wherein the impurity introduction layer having an impurity concentration determined by the impurity introduction is used as an active layer of the insulated gate transistor to manufacture an insulated gate transistor. Method for manufacturing insulated gate semiconductor device. 7. A groove portion having a side wall substantially perpendicular to the surface of the silicon substrate is formed in a part of the silicon substrate whose surface is covered with an insulating film, and an insulating layer is formed on the inner surface of the groove portion. A step of forming, a step of forming an opening in a part of the insulating film covering the surface of the silicon substrate to form a seed region in which a part of the silicon substrate is exposed, and a step of forming a seed region on the seed region and the groove part. A step of forming an amorphous silicon layer on the insulating layer provided on the inner surface, and a heat treatment are performed to solid phase epitaxial growth (Solid Phase Epitaxy; S) from the seed region in the amorphous silicon layer.
PE) to obtain a single crystal silicon layer by an ion implantation method including a portion of the single crystal silicon layer along a sidewall substantially perpendicular to the surface of the silicon substrate in the groove portion. A step of introducing an impurity to form an impurity introduction layer, and manufacturing an insulated gate transistor by using the impurity introduction layer having an impurity concentration determined by the impurity introduction as an active layer of the insulated gate transistor. A method of manufacturing an insulated gate semiconductor device, comprising: 8. An LDD (lightly doped Dore) of an insulated gate type transistor is provided with an impurity introduction layer.
The method of manufacturing an insulated gate semiconductor device according to claim 6 or 7, wherein an insulated gate transistor having an LDD structure is manufactured by using the same as a layer constituting the (in) structure.