JPH08274164A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08274164A
JPH08274164A JP7668695A JP7668695A JPH08274164A JP H08274164 A JPH08274164 A JP H08274164A JP 7668695 A JP7668695 A JP 7668695A JP 7668695 A JP7668695 A JP 7668695A JP H08274164 A JPH08274164 A JP H08274164A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor device
wiring
film
columnar structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7668695A
Other languages
Japanese (ja)
Inventor
Kazuyuki Oba
一之 大場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7668695A priority Critical patent/JPH08274164A/en
Publication of JPH08274164A publication Critical patent/JPH08274164A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To secure an excellent coverage of conducing wiring layers with a second insulation film in a connecting hole regardless of the thickness of the film, easily connect the wiring layers to each other with low resistance, and prevent the deterioration of the reliability of the connecting sections of the wiring layers and the occurrence of discontinuity by providing a columnar structure below the lower wiring layer of the connecting hole section between the wiring layers. CONSTITUTION: A semiconductor device has a first insulating film 104, a lower conducting wiring layer 102, a second insulating film 103, and an upper conducting wiring layers 101 successively formed on the surface of a semiconductor substrate, and a connecting hole for connecting the upper and lower wiring layers 101 and 102. In this semiconductor device constituted in such a way, the connecting hole section between the wiring layers 101 and 102 has columnar structures 105 above the wiring layer 104 and below the wiring layer 102. For example, the wiring layer 102 is formed by removing the unnecessary part of an Al alloy film formed on the columnar structure 105 by sputtering after the structure 105 is formed on the first insulating film 104 of a conductive material or insulator.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に導電配線間の接続に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to connection between conductive wirings.

【0002】[0002]

【従来の技術】従来の半導体装置は図5にある様であっ
た。すなわち、半導体基板上の第1絶縁膜901上にス
パッタ法にて形成される上層導電配線903その上に形
成される第2絶縁膜902、及び前記902上にスパッ
タ法にて形成される上層導電配線903、前記2層の導
電配線を接続するための接続孔部を有し、前記接続孔部
は、前記第2絶縁膜902に開口された前記下層導電配
線904まで達する孔の上から前記上層導電配線903
が形成され、上層導電配線903が下に凸の形状となる
ことにより、上層導電配線903と下層導電配線904
が接続される構造であった。
2. Description of the Related Art A conventional semiconductor device is shown in FIG. That is, the upper conductive wiring 903 formed on the first insulating film 901 on the semiconductor substrate by the sputtering method, the second insulating film 902 formed thereon, and the upper conductive film formed on the 902 by the sputtering method. The wiring 903 has a connection hole portion for connecting the conductive wirings of the two layers, and the connection hole portion is formed on the upper layer from the hole reaching the lower conductive wiring 904 opened in the second insulating film 902. Conductive wiring 903
Is formed, and the upper conductive wiring 903 has a convex shape downward, so that the upper conductive wiring 903 and the lower conductive wiring 904 are formed.
Was the structure to be connected.

【0003】以上が従来技術の半導体装置である。The above is the conventional semiconductor device.

【0004】[0004]

【発明が解決しようとする課題】しかし、前述の従来の
技術では、前記第2絶縁膜902が厚くなるに従い接続
孔の直径に対する高さの比であるアスペクト比が高くな
り、通常スパッタにて形成される前記上層導電層903
の、接続孔での被覆性が低下する。このため、低抵抗な
配線間接続を形成するのが難しく、接続部での信頼性の
低下、断線など生じさせてしまう。またそのため第2絶
縁膜を厚くすることができず配線容量を低減することが
難しい。
However, in the above-mentioned conventional technique, the aspect ratio, which is the ratio of the height to the diameter of the connection hole, increases as the thickness of the second insulating film 902 increases. The upper conductive layer 903
, The coverage of the connection hole is reduced. For this reason, it is difficult to form a low resistance inter-wiring connection, resulting in a decrease in reliability and a disconnection at the connection portion. Therefore, it is difficult to reduce the wiring capacitance because the second insulating film cannot be thickened.

【0005】そこで本発明はこの様な問題を解決するも
ので、その目的とするところは、第2絶縁膜の厚さによ
らず接続孔での配線の被覆性を確保することができ、低
抵抗な配線間接続の形成を容易にし、接続部での信頼性
の低下、断線など生じさせず、第2絶縁膜を厚くでき配
線容量を低減することができる、半導体基板上の第1絶
縁膜上に形成されている第2絶縁膜を挟んだ上層及び下
層の導電配線及び、前記2層の導電配線を接続するため
の接続孔を有する半導体装置を提供するところにある。
Therefore, the present invention solves such a problem, and an object thereof is to ensure the coverage of the wiring in the connection hole irrespective of the thickness of the second insulating film. A first insulating film on a semiconductor substrate that facilitates formation of resistive interconnections, does not reduce reliability at connection portions, does not cause disconnection, etc., and can thicken the second insulating film to reduce wiring capacitance. An object of the present invention is to provide a semiconductor device having upper and lower conductive wirings sandwiching a second insulating film formed thereabove and a connection hole for connecting the conductive wirings of the two layers.

【0006】[0006]

【課題を解決するための手段】前述の課題を解決するた
め本発明の半導体装置は、半導体基板上の第1絶縁膜上
に形成されている第2絶縁膜を挟んだ上層及び下層の導
電配線及び、前記2層の導電配線を接続するための接続
孔を有する半導体装置において、前記導電配線間の接続
孔部の前記下層配線の下に、柱状の構造を有することを
特徴とする半導体装置の構造とする。
In order to solve the above-mentioned problems, a semiconductor device of the present invention has a conductive wiring in upper and lower layers sandwiching a second insulating film formed on a first insulating film on a semiconductor substrate. And a semiconductor device having a connection hole for connecting the conductive wirings of the two layers, wherein the semiconductor device has a columnar structure below the lower layer wiring in the connection hole portion between the conductive wirings. The structure.

【0007】[0007]

【実施例】本発明における半導体装置は、基本的には図
1(a)、図1(b)で示される構造をしている。図1
(b)は図1(a)のA−Bにおける断面図である。1
01は上層導電配線、102は下層導電配線、103は
第2絶縁膜、104は第1絶縁膜である。105は接続
孔部柱状構造で、この上に102を形成することによ
り、103の第2絶縁膜を挟んだ上下の配線101と1
02が接続される構造となる。図2から図6は、本発明
の行程毎の主要断面図である。以下図2から図6に従
い、順に説明していく。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention basically has the structure shown in FIGS. 1 (a) and 1 (b). FIG.
FIG. 1B is a sectional view taken along the line AB of FIG. 1
Reference numeral 01 is an upper conductive wire, 102 is a lower conductive wire, 103 is a second insulating film, and 104 is a first insulating film. Reference numeral 105 denotes a connection hole columnar structure, and by forming 102 thereon, upper and lower wirings 101 and 1 sandwiching the second insulating film 103 are formed.
02 is connected. 2 to 6 are main cross-sectional views of each step of the present invention. Hereinafter, description will be made in order with reference to FIGS. 2 to 6.

【0008】図2の如く、半導体基板上に第1絶縁膜2
01を形成、201上に接続孔部柱状構造形成膜202
を形成する。前記202は0.5μmから3μm程度形
成する。前記202の膜厚は配線容量の削減には厚く形
成するのが望ましいが、上層導電配線フォト時の焦点深
度との関係からむやみに厚くすることは難しく、0.5
μmから1.2μm程度が特に望ましい。次に図3の如
く、202をフォト及びエッチング法により不要な部分
を取り除き、配線間接続孔の部分を柱状に残す。これが
接続孔部柱状構造203となる。
As shown in FIG. 2, the first insulating film 2 is formed on the semiconductor substrate.
01 is formed, and a connection hole portion columnar structure forming film 202 is formed on 201.
To form. The 202 is formed with a thickness of 0.5 μm to 3 μm. It is desirable that the film thickness of 202 is formed thick in order to reduce the wiring capacitance, but it is difficult to unnecessarily increase the film thickness in view of the depth of focus at the time of photo of the upper conductive wiring.
It is particularly desirable that the thickness be from μm to 1.2 μm. Next, as shown in FIG. 3, an unnecessary portion of 202 is removed by a photo and etching method, and a portion of the inter-wiring connection hole is left in a pillar shape. This becomes the connection hole portion columnar structure 203.

【0009】その後図4の如く、スパッタによりAl合
金膜を形成する。前記Al合金膜は0.5μmから1.
5μm程度形成する。前記Al合金膜をフォト及びエッ
チング法により不要な部分を取り除き、これが、下層導
電配線204となる。
Thereafter, as shown in FIG. 4, an Al alloy film is formed by sputtering. The Al alloy film has a thickness of 0.5 μm to 1.
The thickness is about 5 μm. An unnecessary portion of the Al alloy film is removed by photo and etching methods, and this becomes the lower layer conductive wiring 204.

【0010】次に図5の如く、第2絶縁膜205となる
Si酸化膜を化学気相反応法(CVD法)により全面に
0.5μmから3μm程度デポする。その後203上の
204が表面に現れるまで前記Si酸化膜を全面エッチ
ングする。エッチングの前に前記Si酸化膜の平坦化を
行うのが望ましい。例えば、有機SOGを塗布し205
と共にエッチバック、CMP(化学的機械研磨)などの
方法がある。その次に図6の如く、スパッタによりAl
合金膜を形成する。前記Al合金膜は0.5μmから
1.5μm程度形成し、前記Al合金膜をフォト及びエ
ッチング法により不要な部分を取り除き、これが、上層
導電配線206となる 以上の製造行程が本発明の第1の実施例の半導体装置の
製造方法である。
Next, as shown in FIG. 5, a Si oxide film to be the second insulating film 205 is deposited on the entire surface by chemical vapor deposition (CVD) by about 0.5 μm to 3 μm. Thereafter, the Si oxide film is entirely etched until 204 on 203 appears on the surface. It is desirable to flatten the Si oxide film before etching. For example, applying organic SOG 205
In addition, there are methods such as etch back and CMP (Chemical Mechanical Polishing). Then, as shown in FIG. 6, Al is sputtered.
An alloy film is formed. The Al alloy film is formed to a thickness of about 0.5 μm to 1.5 μm, and unnecessary portions of the Al alloy film are removed by a photo and etching method to form the upper conductive wiring 206. 2 is a method of manufacturing a semiconductor device according to the embodiment.

【0011】前記実施例1の様に、導電配線接続部が形
成されることにより、スパッタにて形成される導電配線
の接続孔での被覆性を第2絶縁膜の厚さによらず確保す
ることができ、低抵抗な配線間接続の形成を容易にし、
接続部での信頼性の低下、断線など生じさせない、導電
配線間接続孔を有する半導体装置の製造が容易になる。
また第2絶縁膜を厚くでき配線容量を低減することがで
きる。
By forming the conductive wiring connecting portion as in the first embodiment, the coverage of the conductive wiring formed by sputtering in the connection hole is ensured regardless of the thickness of the second insulating film. And facilitates formation of low-resistance interconnections,
This facilitates the manufacture of a semiconductor device having a conductive interconnection connecting hole that does not cause a decrease in reliability or disconnection at the connecting portion.
Further, the second insulating film can be thickened to reduce the wiring capacitance.

【0012】図7(a)及び図7(b)は、本発明の第
2の実施例における半導体装置の主要断面図である。本
発明の第2の実施例における半導体装置の製造方法を行
程順に説明していく。
FIGS. 7A and 7B are main sectional views of a semiconductor device according to the second embodiment of the present invention. A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described step by step.

【0013】半導体基板上にCVDにより絶縁膜701
を形成する。701は第1絶縁膜として必要な厚さと第
2絶縁膜の厚さを加えた厚さ以上の厚さに形成する。次
にフォト及びエッチング法により図7(b)の如く柱状
構造を形成する。
An insulating film 701 is formed on the semiconductor substrate by CVD.
To form. 701 is formed to have a thickness not less than the sum of the thickness required for the first insulating film and the thickness of the second insulating film. Next, a columnar structure is formed as shown in FIG. 7B by photo and etching methods.

【0014】これ以降は前記実施例1の図4以降と同様
な行程により製造していく。
From this point onward, the manufacturing process is carried out in the same manner as in FIG.

【0015】以上の製造行程が本発明の第2の実施例の
半導体装置の製造方法である。
The above manufacturing process is the manufacturing method of the semiconductor device of the second embodiment of the present invention.

【0016】前記実施例2の様に、導電配線接続部が形
成されることにより、スパッタにて形成される導電配線
の接続孔での被覆性を第2絶縁膜の厚さによらず確保す
ることができ、低抵抗な配線間接続の形成を容易にし、
接続部での信頼性の低下、断線など生じさせない、導電
配線間接続孔を有する半導体装置の製造が容易になる。
また第2絶縁膜を厚くでき配線容量を低減することがで
きる。
By forming the conductive wiring connection portion as in the second embodiment, the coverage of the conductive wiring formed by sputtering in the connection hole is ensured regardless of the thickness of the second insulating film. And facilitates formation of low-resistance interconnections,
This facilitates the manufacture of a semiconductor device having a conductive interconnection connecting hole that does not cause a decrease in reliability or disconnection at the connecting portion.
Further, the second insulating film can be thickened to reduce the wiring capacitance.

【0017】また、第1絶縁膜と接続孔部柱状構造とな
る膜を同時に形成することができ、行程数を減らすこと
ができる。
Further, the first insulating film and the film having the columnar structure of the connection hole can be formed at the same time, and the number of steps can be reduced.

【0018】図8は、本発明の第3の実施例における半
導体装置の主要断面図である。本発明の第3の実施例に
おける半導体装置の製造方法は、前記第1の実施例と同
様である。
FIG. 8 is a main sectional view of a semiconductor device according to the third embodiment of the present invention. The method of manufacturing a semiconductor device according to the third embodiment of the present invention is the same as that of the first embodiment.

【0019】実施例3の様に、前記第1の実施例と同様
に導電配線接続部を形成することにより、スパッタにて
形成される導電配線の接続孔での被覆性を第2絶縁膜の
厚さによらず確保することができ、低抵抗な配線間接続
の形成を容易にし、接続部での信頼性の低下、断線など
生じさせない、導電配線間接続孔を有する半導体装置の
製造が容易になる。また第2絶縁膜を厚くでき配線容量
を低減することができる。
As in the third embodiment, by forming the conductive wiring connecting portion in the same manner as in the first embodiment, the coverage of the connection hole of the conductive wiring formed by sputtering can be improved by the second insulating film. It can be secured regardless of the thickness, facilitates formation of low-resistance wiring-to-wiring connections, and does not reduce reliability at the connection part, does not cause disconnection, etc. become. Further, the second insulating film can be thickened to reduce the wiring capacitance.

【0020】図10は、本発明の第4の実施例における
半導体装置の主要断面図である。本発明の第4の実施例
における半導体装置の製造方法は、接続孔部柱状構造1
5を導電材料により形成すること以外は前記第1の実施
例と同様である。
FIG. 10 is a main sectional view of a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device manufacturing method according to the fourth embodiment of the present invention is the same as that of the connection hole portion columnar structure 1
It is similar to the first embodiment except that 5 is made of a conductive material.

【0021】実施例4の様に、導電配線接続部を形成す
るることにより、スパッタにて形成される導電配線の接
続孔での被覆性を第2絶縁膜の厚さによらず確保するこ
とができ、低抵抗な配線間接続の形成を容易にし、接続
部での信頼性の低下、断線など生じさせない、導電配線
間接続孔を有する半導体装置の製造が容易になる。また
第2絶縁膜を厚くでき配線容量を低減することができ
る。さらに接続孔部柱状構造を導電材料により形成する
ことにより、導電配線接続部の抵抗を更に低くすること
が可能となる。
By forming the conductive wiring connecting portion as in the fourth embodiment, the coverage of the conductive wiring formed by sputtering in the connection hole is ensured regardless of the thickness of the second insulating film. Therefore, it is easy to form a low-resistance inter-wiring connection, and it is easy to manufacture a semiconductor device having a conductive inter-wiring connection hole that does not cause a decrease in reliability at a connection portion or a disconnection. Further, the second insulating film can be thickened to reduce the wiring capacitance. Further, by forming the connection hole columnar structure with a conductive material, it is possible to further reduce the resistance of the conductive wiring connection portion.

【0022】以上本発明者によってなされた発明を、前
記実施例に用い説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて、変形し得ることは勿論である。例えば、前記導電
配線材料はスパッタ以外の方法、CVDあるいはメッキ
などの方法でも同様な効果が得られ、またAl合金以外
のAu、Ag、Cuなどの金属又はその合金、その他の
導電性材料においても同様である。また例えば第1、第
2絶縁膜にSi酸化物以外のSi窒化物その他の絶縁性
材料を用いた場合でも有効である。
Although the invention made by the present inventor has been described with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and may be modified without departing from the scope of the invention. Of course. For example, the same effect can be obtained by a method other than sputtering, such as CVD or plating, for the conductive wiring material, and also for metals such as Au, Ag, and Cu other than Al alloy or alloys thereof, and other conductive materials. It is the same. Further, for example, it is also effective when an insulating material other than Si oxide such as Si nitride is used for the first and second insulating films.

【0023】[0023]

【発明の効果】本発明によれば、前記第2絶縁膜の厚さ
によらず前記導電配線間接孔での配線の被覆性を確保す
ることができ、低抵抗な配線間接続の形成を容易にし、
接続部での信頼性の低下、断線など生じさせない、導電
配線間接続が可能になる。
According to the present invention, the coverage of the wiring in the conductive wiring indirect hole can be ensured irrespective of the thickness of the second insulating film, and the formation of a low-resistance interwiring connection can be facilitated. West,
The connection between the conductive wirings can be performed without lowering the reliability of the connection portion or causing the disconnection.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の第1の実施例を示す主要
図面である。
FIG. 1 is a main drawing showing a first embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の製造方法の第1の実施例
を行程順に説明するための主要断面図である。
FIG. 2 is a main sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

【図3】本発明の半導体装置の製造方法の第1の実施例
を行程順に説明するための主要断面図である。
FIG. 3 is a main sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

【図4】本発明の半導体装置の製造方法の第1の実施例
を行程順に説明するための主要断面図である。
FIG. 4 is a main sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

【図5】本発明の半導体装置の製造方法の第1の実施例
を行程順に説明するための主要断面図である。
FIG. 5 is a main cross-sectional view for explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.

【図6】本発明の半導体装置の製造方法の第1の実施例
を行程順に説明するための主要断面図である。
FIG. 6 is a main sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

【図7】本発明の半導体装置の製造方法の第2の実施例
を説明するための主要断面図である。
FIG. 7 is a main cross-sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device of the present invention.

【図8】本発明の半導体装置の製造方法の第3の実施例
を説明するための主要断面図である。
FIG. 8 is a main sectional view for explaining a third embodiment of the method for manufacturing a semiconductor device of the present invention.

【図9】従来の半導体装置の一例を示す主要断面図であ
る。
FIG. 9 is a main cross-sectional view showing an example of a conventional semiconductor device.

【図10】本発明の半導体装置の製造方法の第4の実施
例を説明するための主要断面図である。
FIG. 10 is a main cross-sectional view for explaining the fourth embodiment of the method for manufacturing the semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

101 上層導電配線 102 下層導電配線 103 第2絶縁膜 104 第1絶縁膜 105 接続孔部柱状構造 201 第1絶縁膜 202 接続孔部柱状構造形成膜 203 接続孔部柱状構造 204 下層導電配線 205 第2絶縁膜 206 上層導電配線 701 絶縁膜 801 上層導電配線 802 下層導電配線 803 第2絶縁膜 804 第1絶縁膜 805 接続孔部柱状構造 901 第1絶縁膜 902 第2絶縁膜 903 上層導電配線 904 下層導電配線 801 上層導電配線 802 下層導電配線 803 第2絶縁膜 804 第1絶縁膜 805 接続孔部柱状構造 101 Upper Conductive Wiring 102 Lower Conductive Wiring 103 Second Insulating Film 104 First Insulating Film 105 Connection Hole Column Structure 201 First Insulating Film 202 Connection Hole Column Structure Forming Film 203 Connection Hole Column Structure 204 Lower Conduction Wire 205 Second Insulating film 206 Upper conductive wiring 701 Insulating film 801 Upper conductive wiring 802 Lower conductive wiring 803 Second insulating film 804 First insulating film 805 Connection hole columnar structure 901 First insulating film 902 Second insulating film 903 Upper conductive wiring 904 Lower conductive Wiring 801 Upper conductive wiring 802 Lower conductive wiring 803 Second insulating film 804 First insulating film 805 Connection hole columnar structure

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上の第1絶縁膜上に形成された
下層導電配線、前記下層導電配線上に形成された第2絶
縁膜、前記第2絶縁膜上に形成された上層導電配線及
び、前記上層、下層の導電配線を接続するための接続孔
を有する半導体装置において、前記導電配線間の接続孔
部は、前記第1絶縁膜上かつ前記下層配線の下に、柱状
の構造を有することを特徴とする半導体装置。
1. A lower-layer conductive wiring formed on a first insulating film on a semiconductor substrate, a second insulating film formed on the lower-layer conductive wiring, an upper-layer conductive wiring formed on the second insulating film, and In the semiconductor device having a connection hole for connecting the upper and lower conductive wires, the connection hole portion between the conductive wires has a columnar structure on the first insulating film and under the lower wiring. A semiconductor device characterized by the above.
【請求項2】前記柱状の構造は、前記第1絶縁膜と同一
の層であることを特徴とする前記請求項1記載の半導体
装置。
2. The semiconductor device according to claim 1, wherein the columnar structure is the same layer as the first insulating film.
【請求項3】前記柱状の構造は、前記第1絶縁膜と異な
る層であることを特徴とする前記請求項1記載の半導体
装置。
3. The semiconductor device according to claim 1, wherein the columnar structure is a layer different from the first insulating film.
【請求項4】前記柱状の構造は、前記第1絶縁膜の膜厚
と同一の高さであることを特徴とする前記請求項1記載
の半導体装置。
4. The semiconductor device according to claim 1, wherein the columnar structure has the same height as the film thickness of the first insulating film.
【請求項5】前記柱状の構造は、前記第1絶縁膜の膜厚
より高いことを特徴とする前記請求項1記載の半導体装
置。
5. The semiconductor device according to claim 1, wherein the columnar structure has a thickness higher than that of the first insulating film.
【請求項6】前記柱状の構造は、導電材料からなること
を特徴とする前記請求項3記載の半導体装置。
6. The semiconductor device according to claim 3, wherein the columnar structure is made of a conductive material.
【請求項7】前記柱状の構造は、絶縁材料からなること
を特徴とする前記請求項3記載の半導体装置。
7. The semiconductor device according to claim 3, wherein the columnar structure is made of an insulating material.
JP7668695A 1995-03-31 1995-03-31 Semiconductor device Pending JPH08274164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7668695A JPH08274164A (en) 1995-03-31 1995-03-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7668695A JPH08274164A (en) 1995-03-31 1995-03-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08274164A true JPH08274164A (en) 1996-10-18

Family

ID=13612344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7668695A Pending JPH08274164A (en) 1995-03-31 1995-03-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08274164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159326A (en) * 2003-11-04 2005-06-16 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005159326A (en) * 2003-11-04 2005-06-16 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method

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