JPH08255834A - ０．５および０．５以下のｕｌｓｉ回路用の中間レベル誘電体内要素としての水素シルシクイオクサンをベースとした流動性酸化物 - Google Patents

０．５および０．５以下のｕｌｓｉ回路用の中間レベル誘電体内要素としての水素シルシクイオクサンをベースとした流動性酸化物

Info

Publication number
JPH08255834A
JPH08255834A JP7330694A JP33069495A JPH08255834A JP H08255834 A JPH08255834 A JP H08255834A JP 7330694 A JP7330694 A JP 7330694A JP 33069495 A JP33069495 A JP 33069495A JP H08255834 A JPH08255834 A JP H08255834A
Authority
JP
Japan
Prior art keywords
layer
intermediate connection
dielectric
connection pattern
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7330694A
Other languages
English (en)
Japanese (ja)
Inventor
Byron T Ahlburn
ティー．アールバーン バイロン
Thomas R Seha
アール．シーハ トーマス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH08255834A publication Critical patent/JPH08255834A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP7330694A 1994-12-20 1995-12-19 ０．５および０．５以下のｕｌｓｉ回路用の中間レベル誘電体内要素としての水素シルシクイオクサンをベースとした流動性酸化物 Pending JPH08255834A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/359,784 US5607773A (en) 1994-12-20 1994-12-20 Method of forming a multilevel dielectric
US359784 1994-12-20

Publications (1)

Publication Number Publication Date
JPH08255834A true JPH08255834A (ja) 1996-10-01

Family

ID=23415255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7330694A Pending JPH08255834A (ja) 1994-12-20 1995-12-19 ０．５および０．５以下のｕｌｓｉ回路用の中間レベル誘電体内要素としての水素シルシクイオクサンをベースとした流動性酸化物

Country Status (4)

Country Link
US (1) US5607773A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH08255834A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR100372216B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW295696B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448245B1 (ko) * 1997-12-30 2004-11-16 주식회사 하이닉스반도체 반도체 소자의 금속배선간 절연막 형성방법
KR100476371B1 (ko) * 1997-12-30 2005-07-05 주식회사 하이닉스반도체 금속층간의평탄화절연막형성방법

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910003742B1 (ko) * 1986-09-09 1991-06-10 세미콘덕터 에너지 라보라터리 캄파니 리미티드 Cvd장치
JPH10163192A (ja) * 1996-10-03 1998-06-19 Fujitsu Ltd 半導体装置およびその製造方法
JP3123449B2 (ja) * 1996-11-01 2001-01-09 ヤマハ株式会社 多層配線形成法
US6030706A (en) * 1996-11-08 2000-02-29 Texas Instruments Incorporated Integrated circuit insulator and method
US5854503A (en) * 1996-11-19 1998-12-29 Integrated Device Technology, Inc. Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
JP3109449B2 (ja) * 1997-04-25 2000-11-13 日本電気株式会社 多層配線構造の形成方法
US5866197A (en) * 1997-06-06 1999-02-02 Dow Corning Corporation Method for producing thick crack-free coating from hydrogen silsequioxane resin
TW392288B (en) 1997-06-06 2000-06-01 Dow Corning Thermally stable dielectric coatings
GB2330001B (en) * 1997-10-06 1999-09-01 United Microelectronics Corp Method of forming an integrated circuit device
TW354417B (en) * 1997-10-18 1999-03-11 United Microelectronics Corp A method for forming a planarized dielectric layer
US5888898A (en) * 1997-10-23 1999-03-30 Advanced Micro Devices, Inc. HSQ baking for reduced dielectric constant
US6083850A (en) * 1997-12-18 2000-07-04 Advanced Micro Devices, Inc. HSQ dielectric interlayer
US6087724A (en) * 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. HSQ with high plasma etching resistance surface for borderless vias
US5958798A (en) * 1997-12-18 1999-09-28 Advanced Micro Devices, Inc. Borderless vias without degradation of HSQ gap fill layers
US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6833280B1 (en) * 1998-03-13 2004-12-21 Micron Technology, Inc. Process for fabricating films of uniform properties on semiconductor devices
KR100643105B1 (ko) * 1998-05-06 2006-11-13 텍사스 인스트루먼츠 인코포레이티드 플립-칩 전자 디바이스를 언더필링하는 저응력 방법 및 장치
TW441006B (en) * 1998-05-18 2001-06-16 United Microelectronics Corp Method of forming inter-metal dielectric layer
US6350673B1 (en) * 1998-08-13 2002-02-26 Texas Instruments Incorporated Method for decreasing CHC degradation
US6384466B1 (en) 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
KR20000024717A (ko) * 1998-10-01 2000-05-06 김영환 다공성 절연막 형성 방법
US6159842A (en) * 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
US6211063B1 (en) 1999-05-25 2001-04-03 Taiwan Semiconductor Manufacturing Company Method to fabricate self-aligned dual damascene structures
US6358841B1 (en) 1999-08-23 2002-03-19 Taiwan Semiconductor Manufacturing Company Method of copper CMP on low dielectric constant HSQ material
US20050158666A1 (en) * 1999-10-15 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma
US6372664B1 (en) 1999-10-15 2002-04-16 Taiwan Semiconductor Manufacturing Company Crack resistant multi-layer dielectric layer and method for formation thereof
US6403464B1 (en) 1999-11-03 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to reduce the moisture content in an organic low dielectric constant material
US6531389B1 (en) 1999-12-20 2003-03-11 Taiwan Semiconductor Manufacturing Company Method for forming incompletely landed via with attenuated contact resistance
US6548901B1 (en) 2000-06-15 2003-04-15 International Business Machines Corporation Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
US6642552B2 (en) 2001-02-02 2003-11-04 Grail Semiconductor Inductive storage capacitor
US6759327B2 (en) 2001-10-09 2004-07-06 Applied Materials Inc. Method of depositing low k barrier layers
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US6838393B2 (en) * 2001-12-14 2005-01-04 Applied Materials, Inc. Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide
JP2003332423A (ja) * 2002-05-14 2003-11-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6925357B2 (en) * 2002-07-25 2005-08-02 Intouch Health, Inc. Medical tele-robotic system
US6727184B1 (en) * 2002-10-29 2004-04-27 Taiwan Semiconductor Manufacturing Co., Ltd Method for coating a thick spin-on-glass layer on a semiconductor structure
US6902440B2 (en) * 2003-10-21 2005-06-07 Freescale Semiconductor, Inc. Method of forming a low K dielectric in a semiconductor manufacturing process
US7030041B2 (en) * 2004-03-15 2006-04-18 Applied Materials Inc. Adhesion improvement for low k dielectrics
US20050233555A1 (en) * 2004-04-19 2005-10-20 Nagarajan Rajagopalan Adhesion improvement for low k dielectrics to conductive materials
US7229911B2 (en) * 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US20050277302A1 (en) * 2004-05-28 2005-12-15 Nguyen Son V Advanced low dielectric constant barrier layers
US7288205B2 (en) * 2004-07-09 2007-10-30 Applied Materials, Inc. Hermetic low dielectric constant layer for barrier applications
KR100675895B1 (ko) * 2005-06-29 2007-02-02 주식회사 하이닉스반도체 반도체소자의 금속배선구조 및 그 제조방법
JP6726142B2 (ja) * 2017-08-28 2020-07-22 信越化学工業株式会社 有機膜形成用組成物、半導体装置製造用基板、有機膜の形成方法、パターン形成方法、及び重合体
JP6940335B2 (ja) 2017-08-30 2021-09-29 信越化学工業株式会社 有機膜形成用組成物、半導体装置製造用基板、有機膜の形成方法、パターン形成方法、及び重合体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4756977A (en) * 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448245B1 (ko) * 1997-12-30 2004-11-16 주식회사 하이닉스반도체 반도체 소자의 금속배선간 절연막 형성방법
KR100476371B1 (ko) * 1997-12-30 2005-07-05 주식회사 하이닉스반도체 금속층간의평탄화절연막형성방법

Also Published As

Publication number Publication date
US5607773A (en) 1997-03-04
KR100372216B1 (ko) 2003-03-28
TW295696B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1997-01-11

Similar Documents

Publication Publication Date Title
US5607773A (en) Method of forming a multilevel dielectric
US7948083B2 (en) Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
US7842518B2 (en) Method for fabricating semiconductor device
JP3568537B2 (ja) マイクロエレクトロニクス構造体用電子ビーム加工膜
EP1050599B1 (en) Method of forming interlayer insulating film
US6207555B1 (en) Electron beam process during dual damascene processing
US5435888A (en) Enhanced planarization technique for an integrated circuit
US6566283B1 (en) Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US6271127B1 (en) Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials
US7705431B1 (en) Method of improving adhesion between two dielectric films
US6531389B1 (en) Method for forming incompletely landed via with attenuated contact resistance
US6518646B1 (en) Semiconductor device with variable composition low-k inter-layer dielectric and method of making
KR100383498B1 (ko) 반도체 장치 제조방법
US6436850B1 (en) Method of degassing low k dielectric for metal deposition
US5930677A (en) Method for reducing microloading in an etchback of spin-on-glass or polymer
EP0790645A2 (en) Intermetal dielectric planarization
US20020033486A1 (en) Method for forming an interconnection line using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer
US5723380A (en) Method of approach to improve metal lithography and via-plug integration
US6037251A (en) Process for intermetal SOG/SOP dielectric planarization
US6784095B1 (en) Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
JP2001118928A (ja) 集積回路の製造方法
JP2000106357A (ja) 半導体装置の製造方法及び絶縁膜の形成方法
EP0810648A2 (en) Improvements in or relating to semiconductor devices
JP4028032B2 (ja) 半導体装置及びその製造方法
US5920791A (en) Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050527

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060613

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060913

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070126