JPH08250934A - Fm demodulation circuit - Google Patents

Abstract

PURPOSE: To allow a circuit to be used without adjustment in the case of demodulating an FM modulation signal with a high modulation or of demodulating a modulation signal with a broad band including DC to a high frequency signal such as a video signal and to demodulate a modulation signal with a high frequency by extracting a change in a power current from both leading and trailing edges of the modulation signal so as to improve the S/N at demodulation. CONSTITUTION: The circuit is provided with an inverter IC circuit 1 having a 1st inverter element 2, and 2nd and 3rd inverter elements 3, 4 inverting a modulation signal f1 into a square wave, a current mirror circuit 5a giving/ receiving a 1st current mirror circuit input current I1 to/from the inverter IC circuit 1, 1st and 2nd capacitors C1 , C2 used to adjust a change in the 1st current mirror circuit input current at leading and trailing states of a square wave, a current 7 voltage conversion circuit 6a converting an output current I2 of the 2nd current mirror circuit into a voltage, and an LPF 7 eliminating harmonics of the waveform of the voltage obtained by the current/voltage conversion circuit 6a and providing an output of a demodulation signal f2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM demodulation circuit, and particularly for demodulating an FM modulated signal having a large degree of modulation in a device connected to a dedicated line such as an intercom device,
Wide band F including DC to high frequency like video signal
The present invention relates to an FM modulation circuit that can be used without adjustment when demodulating an M modulation signal.

[0002]

2. Description of the Related Art Conventionally, a PLL type FM shown in FIG.
Demodulation circuit EQ ₃ or mono-multi FM shown in FIG.
A demodulation circuit EQ ₄ has been proposed. The PLL type FM demodulation circuit EQ ₃ shown in FIG. 4 includes a phase comparator 71 and an LPF 7.
2, is composed of a VCO circuit 73, the input terminal T ₅ of the modulation signal f ₅ is input is connected to the first phase comparison pin 71a of the phase comparator 71.

The phase difference pin 71c of the phase comparator 71 is LP
Through F72 is connected to the input side of the output terminal T ₆ and the VCO circuit 73, to which the demodulation signal f ₆ is output, the oscillation signal pin 73a that outputs an oscillation signal f _V of the VCO circuit 73 and the second phase comparator 71 Is connected to the phase comparison pin 71b.
When there is no signal in the FM demodulation circuit EQ ₃ as described above, the VCO circuit 73 is in the free-run state and continues to oscillate at a constant frequency. Since the modulation signal f ₅ is not input to the input terminal T ₅ , the phase comparator 71 passes the output of the VCO circuit 73
F72 continues to output a constant DC potential.

When the modulation signal f ₅ is input to the input terminal T ₅ , as shown in FIG. 5, the modulation signal f ₅ of the first phase comparison pin 71a of the phase comparator 71 and the oscillation signal pin of the VCO circuit 73 are input. Each rising edge of the oscillation signal f _V output from 73a to the second phase comparison pin 71b becomes a phase difference and is sent from the phase difference pin 71c to the LPF 72, as indicated by the solid arrow.

The LPF 72 takes out a variation of the DC component from the phase difference signal input from the phase difference pin 71c as shown by the solid line arrow, and sends the average level shown by the dotted line from the LPF 72 to the VCO circuit 73 as an error signal. V
The CO circuit 73 generates an oscillation signal f according to the input error signal.
_The operation is continued until the frequency of _V is changed and the frequencies of the oscillation signal f _V and the modulation signal f ₅ match.

The mono-multi type FM demodulation circuit EQ ₄ shown in FIG. 6 has a differentiating circuit 81 and an externally attached time constant resistor R.
_82, mono-multi circuit 82 having a capacitor C _82, LP
The input terminal T ₇ of the F83, to which the modulation signal f ₇ is input, is connected via the capacitor C ₈₁ provided in the differentiating circuit 81 to the other end of the resistor R ₈₁ whose one end is connected to the reference potential point. There is.

The other end of the resistor R ₈₁ is connected to the trigger pin 82a of the monomulti circuit 82 together with the cathode of the diode D ₈₁ whose anode is connected to the reference potential point, and the output pin 82b of the monomulti circuit 82 is connected via the LPF 83. It is connected to the output terminal T ₈ for outputting the demodulated signal f ₈ . An externally attached time constant resistor R ₈₂ of the mono-multi circuit 82 is connected to the power source + V _{CC at} one end, and is connected to the reference potential point via the capacitor C ₈₂ at the other end.

The connection point between the resistor R ₈₂ and the capacitor C ₈₂ is connected to the time constant pin 82c of the mono-multi circuit 82.
When there is no signal in the FM demodulation circuit EQ ₄ as described above, since the trigger pulse from the differentiation circuit 81 to the mono-multi circuit 82 is not generated, the demodulation signal f ₈ is not output to the output terminal T ₈ .

As shown in FIG. 7, when the modulation signal f ₇ is input to the input terminal T ₇ , the modulation signal f ₇ is charged / discharged with a time constant by the capacitor C ₈₁ and the resistor R ₈₁ of the differentiating circuit 81, and the modulation signal f ₇ is generated. Only the rising edge of f ₇ is taken out as shown by the solid line arrow and is sent as a trigger signal to the trigger pin 82a of the mono-multi circuit 82 at the next stage. The diode D ₈₁ has a role of extracting only the rising edge of the modulation signal f ₇ .

When the trigger signal is input, the mono-multi circuit 82 has a capacitor C ₈₂ connected to the time constant pin 82c.
Discharge all of the charged charges once as indicated by the solid arrow. When all the charge of the capacitor C ₈₂ is discharged,
The waveform of the output pin 82b is inverted from the L level to the H level as shown by the solid arrow, and the charging is started with the time constant determined by the resistor R ₈₂ and the capacitor C ₈₂ .

When the capacitor C ₈₂ connected to the time constant pin 82c reaches the threshold level TH1 shown by the alternate long and short dash line, the output waveform of the mono-multi circuit 82 is inverted again and becomes L level. The waveform of the output pin 82b of the mono-multi circuit 82 is input to the LPF 83, the change of the DC component is taken out by the LPF 83 as shown by the solid arrow, and is output from the output terminal T ₈ as the demodulated signal f ₈ shown by the dotted line.

[0012]

The FM demodulation circuit EQ ₃ according INVENTION Problem to be Solved] Such PLL system, it is necessary to adjust so that the oscillation frequency of the VCO circuit 73 can follow the frequency of the modulation signal f _5, the modulation signal f ₅ The frequency of VCO circuit 73
When it exceeds the fluctuation range (lock range) of the oscillating frequency, it becomes a runaway state, so when demodulating an FM modulated signal having a large modulation degree or when demodulating a wide band FM modulated signal such as a video signal including direct current to high frequency. There is a drawback that it cannot be used without adjustment.

An FM demodulation circuit E based on the mono-multi system
In Q ₄ , the output pulse width of the mono-multi circuit 82 is determined by the resistor R ₈₂ and the capacitor C ₈₂ for the time constant, so that there is a drawback that the modulated signal f ₇ of high frequency cannot be demodulated.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and is used for demodulating an FM-modulated signal having a large degree of modulation in a device connected to a dedicated line, such as an intercom device, or a video. An object of the present invention is to provide an FM demodulation circuit that can be used without adjustment when demodulating a wideband modulated signal such as a signal from a direct current to a high frequency and that can demodulate a high frequency modulated signal.

[0015]

In order to achieve such an object, an FM demodulation circuit according to the present invention is provided with a first inverter element and second and third inverter elements for converting a modulated signal into a square wave. An inverter IC, a current mirror circuit for transmitting and receiving a first current mirror circuit current between the inverter IC, and an output side of the second and third inverter elements, respectively, are connected to the first and second current mirror circuits at the rising and falling edges of a square wave, respectively. The first and second capacitors for adjusting the change in the current mirror circuit current of No. 1 and the current for converting the second current mirror circuit current of the current mirror circuit to voltage /
It is provided with a voltage conversion circuit and an LPF for removing a harmonic component of the voltage waveform converted by the current / voltage conversion circuit and outputting a demodulation signal.

[0016]

The first current mirror circuit input current is transmitted and received between the current mirror circuit and the inverter IC provided with the first, second and third inverter elements. The modulated signal is converted into a square wave by the first inverter element,
Is sent to the inverter element of.

The first and second capacitors respectively connected to the output sides of the second and third inverter elements adjust the change of the first current mirror circuit current when the square wave rises and falls. The second current mirror circuit current of the current mirror circuit is converted into a voltage by current / voltage conversion circuit conversion.

The LPF removes the harmonic component of the voltage waveform converted by the current / voltage conversion circuit and outputs it as a demodulated signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an FM demodulation circuit of the present invention will be described in detail below with reference to the drawings. The FM demodulation circuit EQ ₁ according to the present invention,
EQ ₂ is an inverter IC 1 provided with a first inverter element 2 for converting the modulated signals f ₁ and f ₃ into a square wave and second and third inverter elements 3 and 4, and an inverter I.
It is connected to the current mirror circuits 5a and 5b for transmitting and receiving the _first current mirror circuit current I ₁ to and from C and the output sides of the second and third inverter elements, respectively. The first and second capacitors C ₁ , C ₄ , C ₂ , which adjust the change in the current of the current mirror circuit of No. 1,
C ₅ and a current / voltage conversion circuit 6a for converting the _second current mirror circuit current I ₂ of the current mirror circuit into a voltage,
6b and an LPF 7 that removes the harmonic components of the voltage waveform converted by the current / voltage conversion circuit and outputs demodulated signals f ₂ and f _4.
It has and.

The FM demodulation circuit EQ ₁ shown in FIG. 1 includes a CMOS structure inverter IC ₁ having a first inverter element 2, a second inverter element 3 and a third inverter element 4, PNP transistors Q ₁ and Q _2. The discharge-type current mirror circuit 5a, the capacitors C ₁ , C ₂ , the capacitor C ₃ , the coil L ₁ , and the current / voltage conversion circuit 6a provided with the resistor R ₁ and the LPF 7,
The input terminal T ₁ is connected to the input side of the first inverter element 2 provided in the inverter IC 1, and the input terminal T ₁
The modulated signal f ₁ is input via.

The power source terminal P _A of the inverter IC1 is a PNP transistor Q provided in the current mirror circuit 5a.
_The PNP transistor Q _{2 has} its emitter connected to the power supply + V _CC . PNP
The base of the transistor Q ₁ is connected to the base of the PNP transistor Q ₂ , and the emitter of the PNP transistor Q ₁ is connected to the power source + V _CC .

The ground terminal P _B of the inverter IC1 is connected to the reference potential point. The output side of the first inverter element 2 provided in the inverter IC1 is connected to the input sides of the second inverter element 3 and the third inverter element 4, respectively, and the output side of the second inverter element 3 is impulse-shaped. It is connected to the power supply terminal P _A via a capacitor C ₁ that adjusts the amplitude of the through current.

The output side of the third inverter element 4 is a capacitor C ₂ for adjusting the amplitude of the impulse-like through current.
Is connected to the reference potential point via. The collector of the PNP transistor Q ₁ provided in the current mirror circuit 5a is connected to one end of the capacitor C ₃ provided in the current / voltage conversion circuit 6a, and the other end of the capacitor C ₃ is connected to the reference potential point. .

[0024] One end of the capacitor C ₃ is connected to a reference potential point via a coil L ₁ and the resistor R _1, a coil L ₁ and the resistor R
The connection point of ₁ is connected to the output terminal T ₂ for outputting the demodulated signal f ₂ via the LPF 7. The FM demodulation circuit EQ ₂ shown in FIG. 2 is a CMO having a first inverter element 2, a second inverter element 3 and a third inverter element 4.
Suction-type current mirror circuit 5 composed of an inverter IC 1 having an S structure and NPN transistors Q ₃ and Q _4.
b, the capacitors C ₄ , C ₅ , the coil L ₂ , the resistor R ₂ , and the current / voltage conversion circuit 6b and LP provided with the capacitor C _6.
First composed of F7 and provided in the inverter IC1
The input terminal T ₃ is connected to the input side of the inverter element 2 of the above, and the modulation signal f ₃ is input through the input terminal T ₃ .

The output side of the first inverter element 2 provided in the inverter IC1 is the second inverter element 3 on the output side.
And the input side of the third inverter element 4, and the output side of the second inverter element 3 is connected to the power supply terminal P _A via a capacitor C ₄ for adjusting the amplitude of the impulse-like through current, The power supply terminal P _{A of} IC1 is connected to the power supply + V _CC .

The output side of the third inverter element 4 is a capacitor C ₅ for adjusting the amplitude of the impulse-like through current.
Is connected to the ground terminal P _B via. The ground terminal P _B of the inverter IC1 is connected to the collector and base of the NPN transistor Q ₄ provided in the current mirror circuit 5b, and the emitter of the NPN transistor Q ₄ is connected to the reference potential point.

The base of the NPN transistor Q ₄ is NPN.
Is connected to the base of the transistor Q _3, the emitter of NPN transistor Q ₃ are connected to the reference potential point. The collector of the NPN transistor Q ₃ provided in the current mirror circuit 5b is connected to one end of the resistor R ₂ provided in the current / voltage conversion circuit 6b, and the other end of the resistor R ₂ is the power source + V.
Connected to _CC .

Further, one end of the resistor R ₂ is connected to a reference potential point via a coil L ₂ and capacitor C _6, a connection point of the coil L ₂ and capacitor C ₆ outputs a demodulated signal f ₄ through LPF7 It is connected to the output terminal T ₄ . In the FM demodulation circuit EQ ₁ shown in FIG. 1, when the modulation signal f ₁ is not input and there is no signal, the output of the inverter element 2 is as shown in FIG.
The square wave with a constant period shown in is continuously output,
The demodulated signal f ₂ does not change.

When the modulation signal f ₁ as shown in FIG. 3 is input, a square wave is output from the output of the inverter element 2, and this output is consumed by the capacitors C ₁ and C ₂ . When the output of the inverter IC1 is inverted, a through current flows in an impulse shape, and this waveform is output to the power supply terminal P _A. The current mirror circuit 5a is provided in order to prevent the influence of the input-side impedance, the first change of the current mirror circuit input current I ₁ is input to the collector of the PNP transistor Q _1, Figure 3 from the PNP transistor Q ₂ A second current mirror circuit output current I _{2 as shown}
Output as That is, as shown by the alternate long and short dash line arrows, the impulse waveforms corresponding to the rising and falling edges of the output waveforms of the inverter elements 3 and 4 are used as the current mirror circuit output current as the input pin P _C of the current / voltage conversion circuit 6a.
Formed.

At this time, a change in voltage appears as shown by the two-dot chain line arrow in FIG. 3 at both ends of the capacitor C ₃ of the current / voltage conversion circuit 6a. The coil L ₁ and the resistor R ₁ of the current / voltage conversion circuit 6a generate a waveform including this interval. The harmonic component of the waveform is removed via LPF7,
The demodulated signal f ₂ as shown in is output from the output terminal T ₂ .

[0031] Also in the FM demodulation circuit EQ _2, as shown in FIG. 2, it is basically the same as the operation sequence of the FM demodulation circuit EQ ₁ shown in FIG. 1, the second current mirror circuit input current I ₂ current / It is formed at the input pin P _R of the voltage conversion circuit 6b. At the connection point between the capacitor C ₆ and the LPF 7 of the current / voltage conversion circuit 6b, the high frequency component is removed by the LPF 7, and the modulation signal f ₃ input from the input terminal T ₃ shown in FIG.
A change in the demodulation voltage appears according to. Current / voltage conversion circuit 6
b is the output terminal T ₄ the demodulated voltage change as a demodulated signal f ₄
Output from

The above current mirror circuit is an example, and other elements may be used to form the current mirror circuit. The above inverter IC is NAN in addition to NOT
A logic element such as D or NOR may be used. However, the number of gate elements to which the capacitors are connected is not limited to two, and may be four, six, or the like.

The capacitor of the above inverter IC may be connected to either the power supply terminal or the reference potential point.

[0034]

As is apparent from the above description, according to the FM demodulation circuit of the present invention, an inverter provided with the first inverter element and the second and third inverter elements for converting the modulated signal into a square wave. The current mirror circuit for transmitting and receiving the first current mirror circuit current between the IC and the inverter IC, and the output side of the second and third inverter elements, respectively, are connected, and the first and Of the current mirror circuit, the first and second capacitors for adjusting the change in the current, the current / voltage conversion circuit for converting the second current mirror circuit output current of the current mirror circuit into a voltage, and the conversion by the current / voltage conversion circuit Since it has an LPF that removes the harmonic components of the generated voltage waveform and outputs a demodulation signal, the power supply current from both edges of the falling and rising edges of the modulation signal is increased. The S / N ratio at the time of demodulation is improved, and when demodulating an FM modulated signal with a large degree of modulation in a device connected to a dedicated line such as an intercom device, or from a direct current such as a video signal. It can be used without adjustment when demodulating a wide band modulated signal including a high frequency, and can demodulate a high frequency modulated signal.

Brief Description of the Drawings.

FIG. 1 is a block diagram showing an embodiment of an FM demodulation circuit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the FM demodulation circuit according to the present invention.

FIG. 3 is a time chart showing an operation in one embodiment of the FM demodulation circuit according to the present invention.

FIG. 4 is a block diagram of a conventional FM demodulation circuit based on a PLL system.

FIG. 5 is a time chart showing the operation of an FM demodulation circuit according to a conventional PLL system.

FIG. 6 is a block diagram of a conventional FM demodulation circuit using a mono-multi system.

FIG. 7 is a time chart showing the operation of an FM demodulation circuit according to the conventional mono-multi system.

[Explanation of symbols]

1-inverter IC 2-first inverter element 3-second inverter element 4-third inverter element 5a, 5b-・ ・ ・ Current mirror circuit 6a, 6b ・ ・ ・ ・ ・ Current / voltage conversion circuit 7 ・ ・ ・ ・ LPF C ₁ , C ₄・ ・ ・ ・ ・ First capacitors C ₂ , C ₅・・ ・ ・ ・ ・ Second capacitor I ₁・ ・ ・ ・ ・ First current mirror circuit current I ₂・ ・ ・ ・ ・ Second current mirror circuit current f ₁ , f ₃・ ・ ・ ・ ・Modulation signal f ₂ , f ₄ ··· Demodulation signal

Claims (1)

[Claims] 1. An inverter IC (1) provided with a first inverter element (2) and second and third inverter elements (3, 4) for converting modulated signals (f ₁ , f ₃ ) into a square wave.
And a current mirror circuit (5) for transmitting and receiving a _first current mirror circuit current (I ₁ ) between the inverter and the inverter IC.
a, 5b) and the output sides of the second and third inverter elements, respectively, for adjusting changes in the current of the first current mirror circuit when the square wave rises and falls. Capacitors (C ₁ , C ₄ , C ₂ , C ₅ )
A current / voltage conversion circuit (6a, 6b) for converting the second current mirror circuit current (I ₂ ) of the current mirror circuit into a voltage; and a harmonic of the voltage waveform converted by the current / voltage conversion circuit. Demodulated signal with components removed (f ₂ , f ₄ )
And an LPF (7) for outputting
M demodulation circuit.