JPH08248402A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH08248402A
JPH08248402A JP4948895A JP4948895A JPH08248402A JP H08248402 A JPH08248402 A JP H08248402A JP 4948895 A JP4948895 A JP 4948895A JP 4948895 A JP4948895 A JP 4948895A JP H08248402 A JPH08248402 A JP H08248402A
Authority
JP
Japan
Prior art keywords
thin film
film
silicon nitride
insulating
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4948895A
Other languages
Japanese (ja)
Inventor
Hideo Yoshihashi
英生 吉橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4948895A priority Critical patent/JPH08248402A/en
Publication of JPH08248402A publication Critical patent/JPH08248402A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To enhance gate breakdown strength and to improve a yield without adding stages exclusive of a stage for depositing silicon nitride thin films by removing the silicon nitride thin films exclusive of the thin film on the lower side of gate electrodes. CONSTITUTION: An insulating film is formed as a gate insulating film formed of the silicon oxide thin film 203 of the lower layer and the silicon nitride thin film 204 of the upper layer. The silicon nitride thin film 204 of the upper layer is formed only right under the gate electrodes 212 and is removed in the parts exclusive of the parts right under the gate electrodes 212. Namely, the gate insulating film of a thin-film semiconductor device of a coplanar type to be used as a switching element or peripheral driving circuit is formed into the two-layered structure of the thermal silicon oxide thin film 203 of the lower layer on the side near the active layer 202 and the silicon nitride thin film 204 of the upper layer on the side near the gate electrodes 212 and the silicon nitride thin film 204 exclusive of the film under the gate electrodes 212 is removed simultaneously at the time of etching to form the gate electrodes 212. As a result, the liquid crystal display device having the thin-film semiconductor device of the high gate breakdown strength is obtd. without increasing the special stages exclusive of the state for depositing the silicon nitride thin film 204.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device.

【0002】[0002]

【従来の技術】液晶表示装置のスイッチング素子や基板
周囲に配置される周辺駆動回路(液晶ドライバ回路)に
用いられる薄膜半導体装置のうち、特に駆動回路内蔵型
の多結晶薄膜半導体装置は、透明絶縁性基板上に形成さ
れるため、一般にその活性層は基板上に珪素薄膜を堆積
しこれを島状にエッチングして形成される。
2. Description of the Related Art Among thin film semiconductor devices used for a switching element of a liquid crystal display device and a peripheral driving circuit (liquid crystal driver circuit) arranged around a substrate, a polycrystalline thin film semiconductor device having a built-in driving circuit is particularly transparent. Since it is formed on a transparent substrate, its active layer is generally formed by depositing a silicon thin film on the substrate and etching it into an island shape.

【0003】このため、いわゆる集積回路等のような単
結晶珪素基板上に形成される半導体装置の場合とは異な
り、配線形成時にゲート線や信号線等の下地の凹凸が大
きくなりがちであることから、平坦化が困難であるとい
う問題がある。
For this reason, unlike the case of a semiconductor device formed on a single crystal silicon substrate such as a so-called integrated circuit, the unevenness of the base such as the gate line and the signal line tends to become large at the time of forming the wiring. Therefore, there is a problem that flattening is difficult.

【0004】また、活性層の端部の形状が逆テーパ型と
なることもある。このため、特に活性層の端部での絶縁
膜の被覆性が劣悪になりやすく、これが半導体装置のゲ
ート耐圧の低下の原因となり、最悪の場合にはこの部分
で短絡不良が生じるという問題がある。
Further, the shape of the end of the active layer may be an inverse taper type. Therefore, the covering property of the insulating film is apt to be deteriorated particularly at the end portion of the active layer, which causes a reduction in the gate breakdown voltage of the semiconductor device, and in the worst case, a short circuit defect occurs in this portion. .

【0005】また、液晶表示装置に用いられる薄膜半導
体装置は、液晶層の動作特性上、一般のメモリ等に使用
される半導体装置と比較して、より高い電圧で駆動する
必要があるため、耐圧(耐電圧性)のさらに高い絶縁膜
が要求される。
In addition, a thin film semiconductor device used in a liquid crystal display device needs to be driven at a higher voltage than a semiconductor device used in a general memory or the like because of the operating characteristics of the liquid crystal layer, and therefore the breakdown voltage is high. An insulating film having higher (voltage resistance) is required.

【0006】このため、絶縁膜を低温で形成しなければ
ならない非晶質珪素薄膜半導体装置の場合には、ゲート
絶縁膜を例えば酸化珪素膜と窒化珪素膜のような種類の
異なる 2層以上の絶縁膜を用いて形成することが多い。
Therefore, in the case of an amorphous silicon thin film semiconductor device in which the insulating film must be formed at a low temperature, the gate insulating film is composed of two or more layers of different types such as a silicon oxide film and a silicon nitride film. It is often formed using an insulating film.

【0007】また、高温工程を使用可能な駆動装置内蔵
型の多結晶珪素薄膜半導体装置においては、ゲート絶縁
膜として活性層を形成する珪素膜の表層部などの一部分
を高温酸化したものが使用されることが多い。
Further, in a polycrystalline silicon thin film semiconductor device with a built-in driving device which can use a high temperature process, a high temperature oxidation of a part of a surface layer portion of a silicon film forming an active layer is used as a gate insulating film. Often.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、熱酸化
法で絶縁膜を形成する場合に、絶縁膜を厚くすることに
よって耐圧を向上させようとすると、酸化時間が長時間
となり、その製造上のスループットの大幅な低下を招く
という問題がある。
However, in the case of forming an insulating film by the thermal oxidation method, if an attempt is made to increase the breakdown voltage by increasing the thickness of the insulating film, the oxidation time will be long and the manufacturing throughput will be high. However, there is a problem in that

【0009】また、駆動装置内蔵型の液晶表示装置の場
合には、イオン注入装置を用いて不純物を添加すること
により半導体層にソース・ドレイン領域を形成してCM
OS(相補的MOS構造)とするが、これはゲート電極
をマスクとして自己整合的に形成されることが多い。
In the case of a liquid crystal display device with a built-in driving device, the source / drain regions are formed in the semiconductor layer by adding impurities using an ion implantation device, and CM is used.
An OS (complementary MOS structure) is used, but this is often formed in a self-aligned manner using the gate electrode as a mask.

【0010】この場合、ゲート絶縁膜を通して半導体層
に不純物が注入されることになるが、単に酸化膜を厚く
したり種類の異なる 2層以上の絶縁膜を積層した場合に
は、それらの厚い絶縁膜を通して不純物を注入しなけれ
ばならない。このため、注入電圧の高電圧化(注入エネ
ルギの増大化)が必要となる。特に絶縁性基板を使用す
るため注入時の不純物イオンの注入エネルギを大きくと
れない場合には、その製造上のスループット低下が著し
いという問題がある。
In this case, impurities are injected into the semiconductor layer through the gate insulating film. However, if the oxide film is simply thickened or two or more kinds of insulating films of different types are laminated, the thick insulating film Impurities must be implanted through the film. Therefore, it is necessary to increase the injection voltage (increase the injection energy). In particular, since an insulating substrate is used, when the implantation energy of the impurity ions at the time of implantation cannot be made large, there is a problem that the manufacturing throughput is significantly reduced.

【0011】本発明は、このような問題を解決するため
に成されたもので、その目的は、従来の製造工程に窒化
珪素薄膜を堆積する以外の煩雑な工程を追加することな
しに、ゲート耐圧の高い信頼性に富んだ半導体装置を備
えた液晶表示装置であって高歩留まりで良好なスループ
ットで形成することが可能な液晶表示装置を提供するこ
とにある。
The present invention has been made to solve such a problem, and an object thereof is to add a gate to a conventional manufacturing process without adding a complicated process other than depositing a silicon nitride thin film. An object of the present invention is to provide a liquid crystal display device including a highly reliable semiconductor device having a high breakdown voltage, which can be formed with a high yield and a good throughput.

【0012】[0012]

【課題を解決するための手段】本発明の液晶表示装置
は、絶縁性基板上と、該絶縁性基板上に島状に形成され
ており活性領域とその両脇に形成されたソース領域及び
ドレイン領域とを備えた半導体層と、該半導体層を覆う
ように形成された絶縁層と、該絶縁層を介して前記半導
体層の活性領域と対向するゲート電極と、を備えた薄膜
半導体装置を、各画素部のスイッチング素子および/ま
たは前記絶縁性基板上に配置された液晶駆動回路として
用いた液晶表示装置において、前記絶縁膜は、下層の酸
化珪素薄膜と上層の窒化珪素薄膜とから形成されたゲー
ト絶縁膜であって、前記上層の窒化珪素薄膜は、前記ゲ
ート電極直下のみに形成されており該ゲート電極直下以
外の部分では除去されていることを特徴としている。
A liquid crystal display device according to the present invention comprises an insulating substrate, an island-shaped active region formed on the insulating substrate, and a source region and a drain formed on both sides of the active region. A thin film semiconductor device including a semiconductor layer having a region, an insulating layer formed to cover the semiconductor layer, and a gate electrode facing the active region of the semiconductor layer with the insulating layer interposed therebetween, In a liquid crystal display device used as a switching element of each pixel portion and / or a liquid crystal driving circuit arranged on the insulating substrate, the insulating film is formed of a lower silicon oxide thin film and an upper silicon nitride thin film. The gate insulating film is characterized in that the upper silicon nitride thin film is formed only under the gate electrode and is removed in a portion other than under the gate electrode.

【0013】また、絶縁性基板上と、該絶縁性基板上に
島状に形成されており活性領域とその両脇に形成された
ソース領域及びドレイン領域とを備えた半導体層と、該
半導体層を覆うように形成された絶縁層と、該絶縁層を
介して前記半導体層の活性領域と対向するゲート電極
と、を備えた薄膜半導体装置を、各画素部のスイッチン
グ素子および/または前記絶縁性基板上に配置された液
晶駆動回路として用いた液晶表示装置において、前記絶
縁膜は、下層の酸化珪素薄膜と上層の窒化珪素薄膜とか
ら形成されたゲート絶縁膜であって、前記上層の窒化珪
素薄膜は、前記ゲート電極直下および前記島状の半導体
層の端部の側面を覆う前記下層の酸化珪素薄膜に沿った
部分に形成されており、該ゲート電極直下および前記下
層の酸化珪素薄膜に沿った部分以外の部分では除去され
ていることを特徴としている。
Further, a semiconductor layer formed on the insulating substrate, island-shaped on the insulating substrate, and having an active region and source and drain regions formed on both sides of the active region, and the semiconductor layer. A thin film semiconductor device having an insulating layer formed so as to cover the active layer and a gate electrode facing the active region of the semiconductor layer via the insulating layer, and a switching element in each pixel portion and / or the insulating layer. In a liquid crystal display device used as a liquid crystal drive circuit arranged on a substrate, the insulating film is a gate insulating film formed of a lower silicon oxide thin film and an upper silicon nitride thin film, and the upper silicon nitride film is formed. The thin film is formed directly below the gate electrode and in a portion along the side surface of the end of the island-shaped semiconductor layer along the lower silicon oxide thin film. The portions other than Tsu portion is characterized in that it is removed.

【0014】また、絶縁性基板上と、該絶縁性基板上に
島状に形成されており活性領域とその両脇に形成された
ソース領域及びドレイン領域とを備えた半導体層と、該
半導体層を覆うように形成された絶縁層と、該絶縁層を
介して前記半導体層の活性領域と対向するゲート電極
と、を備えた薄膜半導体装置を、各画素部のスイッチン
グ素子および/または前記絶縁性基板上に配置された液
晶駆動回路として用いた液晶表示装置において、前記絶
縁膜は、下層の酸化珪素薄膜と上層の窒化珪素薄膜とか
ら形成されたゲート絶縁膜であって、前記上層の窒化珪
素薄膜は、平面形状寸法が前記ゲート電極直下よりも 3
μm以内広い寸法に形成されるとともに、前記島状の半
導体層の端部の側面を覆う前記下層の酸化珪素薄膜に沿
った部分にも形成されており、該ゲート電極下および前
記下層の酸化珪素薄膜に沿った部分以外の部分では除去
されていることを特徴としている。
Also, a semiconductor layer having an insulating substrate, an island-shaped active region, and a source region and a drain region formed on both sides of the active region, the semiconductor layer being formed on the insulating substrate. A thin film semiconductor device having an insulating layer formed so as to cover the active layer and a gate electrode facing the active region of the semiconductor layer via the insulating layer, and a switching element in each pixel portion and / or the insulating layer. In a liquid crystal display device used as a liquid crystal drive circuit arranged on a substrate, the insulating film is a gate insulating film formed of a lower silicon oxide thin film and an upper silicon nitride thin film, and the upper silicon nitride film is formed. The planar shape of the thin film is smaller than that directly below the gate electrode.
It is formed in a wide dimension within μm and is also formed in a portion along the lower silicon oxide thin film which covers the side surface of the end portion of the island-shaped semiconductor layer, and is formed under the gate electrode and in the lower silicon oxide. It is characterized in that the portions other than the portion along the thin film are removed.

【0015】なお、上記の上層の窒化珪素薄膜は、 3μ
m以内であればゲート電極直下からはみだしても良いこ
とは言うまでもない。むしろ、上記の如く 3μm以内に
積極的にはみだすようにその平面形状をパターニングす
ることで、そのはみだした 3μm以内の領域の窒化珪素
薄膜をマスクとして用いてセルフアラインでLDD構造
を形成することもできるという利点が得られるからであ
る。
The upper silicon nitride thin film is 3 μm thick.
Needless to say, it may be protruded from directly under the gate electrode as long as it is within m. Rather, the LDD structure can be formed by self-alignment by patterning the planar shape so as to positively protrude within 3 μm as described above and using the protruding silicon nitride thin film within 3 μm as a mask. This is because the advantage is obtained.

【0016】[0016]

【作用】本発明の液晶表示装置においては、スイッチン
グ素子や周辺駆動回路として用いられるコプラナ型の薄
膜半導体装置のゲート絶縁膜を活性層に近い側の下層熱
酸化膜とゲート電極に近い側の上層窒化珪素膜との 2層
構造とし、かつゲート電極を形成するエッチングの際に
同時にゲート電極の下以外の窒化珪素膜は除去する。つ
まりゲート電極に対応する部分の絶縁膜は良好な絶縁性
を得るために適切な厚さに厚く形成できるとともに、そ
れ以外の部分の同一層(絶縁膜)の厚さは薄くできる。
これにより、窒化珪素薄膜を堆積する以外の特別な工程
を増加させることなしにゲート耐圧の高い薄膜半導体装
置を備えた液晶表示装置を提供することができる。
In the liquid crystal display device of the present invention, the gate insulating film of the coplanar type thin film semiconductor device used as a switching element or a peripheral drive circuit is provided with a lower thermal oxide film near the active layer and an upper layer near the gate electrode. It has a two-layer structure with a silicon nitride film, and the silicon nitride film except under the gate electrode is removed at the same time as the etching for forming the gate electrode. That is, the insulating film in the portion corresponding to the gate electrode can be formed thick to have an appropriate thickness in order to obtain good insulating properties, and the thickness of the same layer (insulating film) in the other portions can be thin.
As a result, it is possible to provide a liquid crystal display device including a thin film semiconductor device having a high gate breakdown voltage without increasing a special process other than depositing a silicon nitride thin film.

【0017】即ち、この方法によれば、活性層側の絶縁
膜は活性層をなす多結晶珪素薄膜を熱酸化することによ
って形成されているため、両者の界面部分の欠陥等が少
なく良好な特性を有するトランジスタを得ることができ
る。一方、ゲート下側以外の絶縁膜は除去されているた
め、ゲートをマスクとして不純物を注入することにより
自己整合的にソース・ドレイン領域を形成する場合にも
絶縁膜厚の増大によるスループットの低下は生じない。
That is, according to this method, since the insulating film on the active layer side is formed by thermally oxidizing the polycrystalline silicon thin film forming the active layer, there are few defects at the interface between the two and good characteristics are obtained. Can be obtained. On the other hand, since the insulating film other than the lower side of the gate is removed, even if the source / drain regions are formed in a self-aligned manner by implanting impurities using the gate as a mask, there is no decrease in throughput due to an increase in the insulating film thickness. Does not happen.

【0018】また、窒化珪素膜のエッチング特性は多結
晶珪素膜のそれに近いため、ゲートエッチング時に同時
に窒化珪素膜を除去することは特別な手段を用いること
なく容易であり、またこの条件で下層酸化珪素膜との選
択性は十分にある。
Further, since the etching characteristics of the silicon nitride film are similar to those of the polycrystalline silicon film, it is easy to remove the silicon nitride film at the same time during the gate etching without using any special means, and under this condition, the lower layer oxide film is oxidized. The selectivity with respect to the silicon film is sufficient.

【0019】また、液晶表示装置に用いられる薄膜半導
体装置においては、絶縁基板上に活性層を島状に形成す
るが、このとき従来の技術では、活性層の断面形状は端
面が急峻になることが多く、このような切り立った面と
その近傍にはエッチングが進行し難いため、図1(a)
に示すように、ゲート電極104を形成するためにゲー
ト電極用の多結晶珪素薄膜をエッチングする際に、その
ゲート電極用多結晶珪素薄膜の一部がエッチング除去さ
れずにエッチング残り104´として活性層102端面
の長手方向に沿って取り残され、これが原因でゲート配
線(図示省略)や信号配線(図示省略)などの配線が短
絡不良を起こしていた。また薄膜半導体装置の微細化に
伴なって寸法制御を確実に行なうためエッチングの垂直
性が求められているが、このとき活性層102の端部に
おけるエッチング残りに関してさらに厳しい条件となっ
ていた。
Further, in a thin film semiconductor device used in a liquid crystal display device, an active layer is formed in an island shape on an insulating substrate. At this time, in the conventional technique, the cross section of the active layer has a sharp end face. 1 (a) because it is difficult for etching to proceed on the raised surface and its vicinity.
As shown in FIG. 6, when the polycrystalline silicon thin film for the gate electrode is etched to form the gate electrode 104, a part of the polycrystalline silicon thin film for the gate electrode is not removed by etching and is activated as an etching residue 104 ′. Wiring was left along the longitudinal direction of the end face of the layer 102, and due to this, short circuits occurred in wiring such as gate wiring (not shown) and signal wiring (not shown). Further, verticality of etching is required in order to surely control the dimensions as the thin film semiconductor device is miniaturized, but at this time, the etching residue at the end of the active layer 102 becomes more severe.

【0020】しかし、本発明によれば、エッチング残り
の生じやすい活性層102の端面を覆う酸化珪素膜10
3とその近傍の絶縁性基板101面上には、その活性層
102端面の長手方向に沿って、図1(b)に示すよう
に絶縁性の窒化珪素膜105の一部のエッチング残り1
06を残すことができ、かつこの部分にはゲート電極1
04の形成材料である導電性材料は残ること無く選択的
にエッチング除去できる。そしてこのように絶縁性材料
である窒化珪素膜105がエッチング残り106として
多少残っても、短絡不良は生じることがなく、むしろ後
の層間絶縁膜の形成の際などに段切れを防止する効果が
ある。
However, according to the present invention, the silicon oxide film 10 that covers the end face of the active layer 102 where etching residue is likely to occur.
3 and its vicinity on the surface of the insulating substrate 101 along the longitudinal direction of the end surface of the active layer 102, as shown in FIG.
06 can be left, and the gate electrode 1
The conductive material, which is a forming material of 04, can be selectively removed by etching without remaining. Even if the silicon nitride film 105, which is an insulating material, remains as the etching residue 106 in this way, a short-circuit defect does not occur, but rather it has an effect of preventing step disconnection when forming an interlayer insulating film later. is there.

【0021】従って、本発明によれば、上述したような
従来技術の問題点を解消することができる。
Therefore, according to the present invention, it is possible to solve the above-mentioned problems of the prior art.

【0022】[0022]

【実施例】以下、本発明に係る液晶表示装置の実施例を
図面に基づいて詳細に説明する。本実施例では、多結晶
珪素薄膜を材料として活性層が形成された薄膜半導体装
置を液晶駆動回路として備えた液晶表示装置に本発明を
適用した場合の一実施例について述べる。
Embodiments of the liquid crystal display device according to the present invention will be described in detail below with reference to the drawings. In this embodiment, an embodiment in which the present invention is applied to a liquid crystal display device including a thin film semiconductor device in which an active layer is formed using a polycrystalline silicon thin film as a material, will be described.

【0023】本実施例の駆動回路基板の断面図の構造お
よびその製造フローを図2に示す。まず、石英基板など
の絶縁性基板201上に、活性層(後述)を形成する材
料として活性層202の形成材料膜である多結晶珪素薄
膜を減圧CVD法で 100nmの厚さに形成する。
FIG. 2 shows the structure of a sectional view of the drive circuit board of this embodiment and the manufacturing flow thereof. First, on an insulating substrate 201 such as a quartz substrate, a polycrystalline silicon thin film that is a forming material film of an active layer 202 is formed with a thickness of 100 nm as a material for forming an active layer (described later) by a low pressure CVD method.

【0024】この活性層202の形成材料の多結晶珪素
薄膜をフォトリソグラフィ法を用いて島状に加工した
後、その表面に下層ゲート絶縁膜となる酸化珪素膜20
3を熱酸化法によって30nmの厚さに形成する。
The polycrystalline silicon thin film as the material for forming the active layer 202 is processed into an island shape by the photolithography method, and then the silicon oxide film 20 to be the lower gate insulating film is formed on the surface thereof.
3 is formed to a thickness of 30 nm by the thermal oxidation method.

【0025】次に、上層ゲート絶縁膜となる窒化珪素薄
膜204を減圧CVD法により30nmの厚さに形成す
る。続いて、ゲート電極(後述)を形成する材料として
多結晶珪素薄膜205を減圧CVD法によって 400nm
の厚さに形成した後、燐(P)などの不純物を添加して
活性化熱処理を行なう(図2(a))。
Next, a silicon nitride thin film 204 to be an upper gate insulating film is formed to a thickness of 30 nm by the low pressure CVD method. Then, a polycrystalline silicon thin film 205 is formed as a material for forming a gate electrode (described later) by a low pressure CVD method to 400 nm.
Then, an activation heat treatment is performed by adding impurities such as phosphorus (P) (FIG. 2A).

【0026】続いて、後にゲート電極212となるべき
部分以外の多結晶珪素薄膜205と、そのゲート電極2
12直下以外の部分の窒化珪素薄膜204とを、同時に
フォトリソグラフィ法により除去し、ゲート電極212
を形成する。
Subsequently, the polycrystalline silicon thin film 205 other than the portion to be the gate electrode 212 later and the gate electrode 2 thereof are formed.
A portion of the silicon nitride thin film 204 other than directly under 12 is simultaneously removed by photolithography, and the gate electrode 212 is removed.
To form.

【0027】続いて、ゲート電極212をマスクとして
用いて自己整合的に不純物イオンを注入し、ソース拡散
領域206およびドレイン拡散領域207を形成する
(図2(b))。
Subsequently, impurity ions are implanted in a self-aligned manner using the gate electrode 212 as a mask to form a source diffusion region 206 and a drain diffusion region 207 (FIG. 2B).

【0028】次に、CVD法により層間絶縁膜である酸
化珪素膜208を形成し、フォトリソグラフィ法を用い
てソース拡散領域206・ドレイン拡散領域207のそ
れぞれ表面の一部を露出させるコンタクトホールを穿設
する。そしてアルゴンガスのスパッタリング等によって
アルミニウムもしくはその合金薄膜のような導電材料を
400nmの厚さに成膜し、これをフォトリソグラフィ法
によりパターニングして、ソース接続配線209a、ド
レイン接続配線209b等をそれぞれ形成する。
Next, a silicon oxide film 208, which is an interlayer insulating film, is formed by the CVD method, and contact holes are formed by photolithography to expose a part of the surface of each of the source diffusion region 206 and the drain diffusion region 207. Set up. Then, a conductive material such as aluminum or its alloy thin film is formed by sputtering argon gas.
A film having a thickness of 400 nm is formed and patterned by a photolithography method to form a source connection wiring 209a, a drain connection wiring 209b, and the like.

【0029】そして、窒素雰囲気中で 450℃・30分間の
熱処理を行なうことによって、上記のソース接続配線2
09a、ドレイン接続配線209bとそれぞれソース拡
散領域206、ドレイン拡散領域207の表面との界面
における相互拡散を行なって配線を形成する(図2
(c))。
Then, by performing heat treatment at 450 ° C. for 30 minutes in a nitrogen atmosphere, the above-mentioned source connection wiring 2 is formed.
09a and drain connection wiring 209b and the surface of the source diffusion region 206 and the surface of the drain diffusion region 207, respectively, are interdiffused to form wiring (FIG. 2).
(C)).

【0030】次に、酸化珪素膜を常圧CVD法により 6
00nmの厚さに形成し層間絶縁膜210を得る。
Next, the silicon oxide film is formed by an atmospheric pressure CVD method 6
It is formed to a thickness of 00 nm to obtain an interlayer insulating film 210.

【0031】そしてこの層間絶縁膜210にITOから
なる画素電極211(後述)との接触をとるためのコン
タクトホールをフォトリソグラフィ法により開孔する。
Then, a contact hole for making contact with a pixel electrode 211 (described later) made of ITO is formed in the interlayer insulating film 210 by a photolithography method.

【0032】続いて、アルゴンガスのスパッタリングに
よりITO膜を 150nmの厚さに成膜し、これをフォト
リソグラフィ法を用いてパターニングして、画素電極2
11を得る(図2(d))。
Subsequently, an ITO film having a thickness of 150 nm is formed by sputtering with an argon gas, and the ITO film is patterned by a photolithography method to form a pixel electrode 2.
11 is obtained (FIG. 2 (d)).

【0033】このようにして主要部が完成された液晶表
示装置用の薄膜半導体装置は、ゲート耐圧が50Vとなっ
た。またゲート絶縁不良に起因した薄膜半導体装置の不
良率は0.01%となった。
The thin film semiconductor device for a liquid crystal display device, the main part of which is completed in this way, has a gate breakdown voltage of 50V. In addition, the defective rate of the thin film semiconductor device due to defective gate insulation was 0.01%.

【0034】従来の熱酸化膜単層をゲート絶縁膜に用い
た場合のゲート耐圧が30V・不良率が0.03%であること
と比較すると、本発明の効果は顕著に大きいことが確認
された。
It was confirmed that the effect of the present invention is remarkably large as compared with the gate withstand voltage of 30 V and the defect rate of 0.03% when the conventional single layer of thermal oxide film is used as the gate insulating film.

【0035】なお、上記の上層の窒化珪素薄膜204
は、 3μm以内であればゲート電極212の直下から、
はみだしても良いことは言うまでもない。むしろ、上記
の如く3μm以内に積極的にはみだすようにその平面形
状をパターニングすることで、そのはみだした 3μm以
内の領域の窒化珪素薄膜204をマスクとして用いてセ
ルフアラインでLDD構造を形成することもできるとい
う利点が得られる。従ってLDD構造が必要な場合に
は、そのように形成すれば、簡易にLDD構造をえるこ
とができるので好ましい。
The above-mentioned upper silicon nitride thin film 204 is formed.
Is within 3 μm, directly below the gate electrode 212,
It goes without saying that it is okay to protrude. Rather, the LDD structure can be formed by self-alignment by patterning the planar shape so as to positively protrude within 3 μm as described above and using the silicon nitride thin film 204 in the protruded region within 3 μm as a mask. The advantage is that you can. Therefore, when the LDD structure is required, it is preferable to form the LDD structure because the LDD structure can be easily obtained.

【0036】また、図1(b)に示したように、島状の
活性層102の端面部分を覆う酸化珪素膜103および
その近傍の絶縁性基板101の面上(つまり活性層10
2両脇、図2では活性層202の端面部分の酸化珪素膜
203およびその近傍の絶縁性基板201の面上)に、
その長手方向に沿って上層ゲート絶縁膜の形成材料であ
る窒化珪素薄膜106(図2における窒化珪素薄膜20
4)を積極的に残しても良い。このように窒化珪素薄膜
204を積極的に残すことによって、この部分を覆うよ
うに酸化珪素膜208等が層間絶縁膜として積層される
際の、いわゆる段切れと呼ばれる成膜不良を解消すると
いう効果を得ることができる。
As shown in FIG. 1B, the silicon oxide film 103 covering the end face portion of the island-shaped active layer 102 and the surface of the insulating substrate 101 in the vicinity thereof (that is, the active layer 10).
2 on both sides, in FIG. 2, on the surface of the silicon oxide film 203 at the end face portion of the active layer 202 and in the vicinity thereof on the insulating substrate 201),
Along the longitudinal direction, the silicon nitride thin film 106 (the silicon nitride thin film 20 in FIG. 2) that is a material for forming the upper gate insulating film is formed.
You may leave 4) positively. By positively leaving the silicon nitride thin film 204 in this manner, an effect of eliminating a film formation defect called so-called step disconnection when the silicon oxide film 208 or the like is laminated as an interlayer insulating film so as to cover this portion Can be obtained.

【0037】このように窒化珪素薄膜204を残すこと
は、窒化珪素薄膜204のエッチングレートとその下層
の酸化珪素膜203のエッチングレート、およびその上
層の多結晶珪素薄膜205のエッチングレートとが異な
っているために、十分正確かつ簡易な制御が可能である
ので、本発明によれば簡易に実現できるのである。
By leaving the silicon nitride thin film 204 in this way, the etching rate of the silicon nitride thin film 204 is different from the etching rate of the lower silicon oxide film 203 and the etching rate of the upper polycrystalline silicon thin film 205. Therefore, since the control is sufficiently accurate and simple, the present invention can be easily realized.

【0038】[0038]

【発明の効果】以上、詳細な説明で明示したように、本
発明によれば、ゲート絶縁膜を下層熱酸化膜と上層窒化
珪素膜の積層構造とし、かつゲート電極の下側以外の窒
化珪素薄膜を除去した構造とすることにより、従来工程
に窒化珪素薄膜を堆積する以外の工程を追加することな
しに、ゲート耐圧が高くかつ歩留まりが良いものとな
る。 また、ゲート電極下側以外の絶縁膜膜厚が増加し
ないため、ソース・ドレイン形成のための不純物打ち込
み時にスループットの低下を招くことがない。
As is clear from the detailed description above, according to the present invention, the gate insulating film has a laminated structure of a lower thermal oxide film and an upper silicon nitride film, and silicon nitride other than the lower side of the gate electrode is formed. With the structure in which the thin film is removed, the gate breakdown voltage is high and the yield is good without adding a process other than the deposition of the silicon nitride thin film to the conventional process. In addition, since the thickness of the insulating film other than under the gate electrode does not increase, throughput does not decrease when implanting impurities for forming the source / drain.

【0039】また、ゲート絶縁膜上層の窒化珪素膜の形
成には被覆性の良い減圧CVD法を用いることができる
ため、活性層に島状にエッチングした多結晶珪素薄膜を
用いる液晶表示装置の場合でも、この窒化珪素層により
島端部の凹凸が緩和され、ゲート電極の断線等の少ない
薄膜半導体装置を得ることができる。
Further, since a low pressure CVD method having a good covering property can be used to form the silicon nitride film as the upper layer of the gate insulating film, in the case of a liquid crystal display device using an island-shaped polycrystalline silicon thin film as an active layer. However, the silicon nitride layer alleviates irregularities at the island ends, so that a thin film semiconductor device with less breakage of the gate electrode can be obtained.

【0040】また、ゲート下層は絶縁体である窒化珪素
膜であるため、島状の活性層端部が逆テーパをなすよう
な場合でもエッチング残りに起因した配線の短絡不良が
生じることがない。
Further, since the lower layer of the gate is a silicon nitride film which is an insulator, even if the end portion of the island-shaped active layer has a reverse taper, the short circuit of the wiring due to the etching residue does not occur.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来技術に係る薄膜半導体装置におけるゲート
電極材料のエッチング残りが生じた状態を示す断面図
(a)、および本発明に係る薄膜半導体装置の断面図
(b)である。
FIG. 1 is a sectional view (a) showing a state where an etching residue of a gate electrode material occurs in a thin film semiconductor device according to a conventional technique, and a sectional view (b) of a thin film semiconductor device according to the present invention.

【図2】本発明に係る液晶表示装置に用いられる薄膜半
導体装置の構造およびその製造プロセスフローの、概要
を示す断面図である。
FIG. 2 is a cross-sectional view showing an outline of a structure of a thin film semiconductor device used in a liquid crystal display device according to the present invention and a manufacturing process flow thereof.

【符号の説明】[Explanation of symbols]

101………絶縁性基板 102………活性層(多結晶珪素薄膜) 103………酸化珪素膜 104………ゲート電極用多結晶珪素薄膜 105………窒化珪素膜 106………エッチング残り(多結晶珪素) 201………絶縁性基板 202………活性層(多結晶珪素薄膜) 203………酸化珪素膜 204………窒化珪素薄膜 205………多結晶珪素薄膜 206………ソース拡散領域 207………ドレイン拡散領域 208………酸化珪素膜(層間絶縁膜) 209a……ソース接続配線 209b……ドレイン接続配線 210………層間絶縁膜 211………画素電極 212………ゲート電極 101 ... Insulating substrate 102 ... Active layer (polycrystalline silicon thin film) 103 ... Silicon oxide film 104 ... Polycrystalline silicon thin film for gate electrode 105 ... Silicon nitride film 106 ... Etching residue (Polycrystalline silicon) 201 ... Insulating substrate 202 ... Active layer (Polycrystalline silicon thin film) 203 ... Silicon oxide film 204 ... Silicon nitride thin film 205 ... Polycrystalline silicon thin film 206 ... Source diffusion region 207 ... Drain diffusion region 208 ... Silicon oxide film (interlayer insulating film) 209a Source connection wiring 209b ... Drain connection wiring 210 ... Interlayer insulating film 211 ... Pixel electrode 212 ... ... Gate electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上と、該絶縁性基板上に島状
に形成されており活性領域とその両脇に形成されたソー
ス領域及びドレイン領域とを備えた半導体層と、該半導
体層を覆うように形成された絶縁層と、該絶縁層を介し
て前記半導体層の活性領域と対向するゲート電極と、を
備えた薄膜半導体装置を、各画素部のスイッチング素子
および/または前記絶縁性基板上に配置された液晶駆動
回路として用いた液晶表示装置において、 前記絶縁膜は、下層の酸化珪素薄膜と上層の窒化珪素薄
膜とから形成されたゲート絶縁膜であって、 前記上層の窒化珪素薄膜は、前記ゲート電極直下のみに
形成されており該ゲート電極直下以外の部分では除去さ
れていることを特徴とする液晶表示装置。
1. A semiconductor layer having an insulating substrate, an island-shaped active region, and a source region and a drain region formed on both sides of the active region, the semiconductor layer being formed on the insulating substrate in an island shape. A thin film semiconductor device having an insulating layer formed so as to cover the active layer and a gate electrode facing the active region of the semiconductor layer via the insulating layer, and a switching element in each pixel portion and / or the insulating layer. In a liquid crystal display device used as a liquid crystal drive circuit arranged on a substrate, the insulating film is a gate insulating film formed of a lower silicon oxide thin film and an upper silicon nitride thin film, and the upper silicon nitride thin film is formed. The liquid crystal display device, wherein the thin film is formed only under the gate electrode and is removed in a portion other than under the gate electrode.
【請求項2】 絶縁性基板上と、該絶縁性基板上に島状
に形成されており活性領域とその両脇に形成されたソー
ス領域及びドレイン領域とを備えた半導体層と、該半導
体層を覆うように形成された絶縁層と、該絶縁層を介し
て前記半導体層の活性領域と対向するゲート電極と、を
備えた薄膜半導体装置を、各画素部のスイッチング素子
および/または前記絶縁性基板上に配置された液晶駆動
回路として用いた液晶表示装置において、 前記絶縁膜は、下層の酸化珪素薄膜と上層の窒化珪素薄
膜とから形成されたゲート絶縁膜であって、 前記上層の窒化珪素薄膜は、前記ゲート電極直下および
前記島状の半導体層の端部の側面を覆う前記下層の酸化
珪素薄膜に沿った部分に形成されており、該ゲート電極
直下および前記下層の酸化珪素薄膜に沿った部分以外の
部分では除去されていることを特徴とする液晶表示装
置。
2. A semiconductor layer having an insulating substrate, an island-shaped semiconductor region formed on the insulating substrate, and an active region and source and drain regions formed on both sides of the active region, and the semiconductor layer. A thin film semiconductor device having an insulating layer formed so as to cover the active layer and a gate electrode facing the active region of the semiconductor layer via the insulating layer, and a switching element in each pixel portion and / or the insulating layer. In a liquid crystal display device used as a liquid crystal drive circuit arranged on a substrate, the insulating film is a gate insulating film formed of a lower silicon oxide thin film and an upper silicon nitride thin film, and the upper silicon nitride thin film is formed. The thin film is formed immediately below the gate electrode and along the lower silicon oxide thin film covering the side surface of the end portion of the island-shaped semiconductor layer, and directly below the gate electrode and along the lower silicon oxide thin film. A liquid crystal display device characterized in that it is removed in the portion other than the portion.
【請求項3】 絶縁性基板上と、該絶縁性基板上に島状
に形成されており活性領域とその両脇に形成されたソー
ス領域及びドレイン領域とを備えた半導体層と、該半導
体層を覆うように形成された絶縁層と、該絶縁層を介し
て前記半導体層の活性領域と対向するゲート電極と、を
備えた薄膜半導体装置を、各画素部のスイッチング素子
および/または前記絶縁性基板上に配置された液晶駆動
回路として用いた液晶表示装置において、 前記絶縁膜は、下層の酸化珪素薄膜と上層の窒化珪素薄
膜とから形成されたゲート絶縁膜であって、 前記上層の窒化珪素薄膜は、平面形状寸法が前記ゲート
電極直下よりも 3μm以内広い寸法に形成されるととも
に、前記島状の半導体層の端部の側面を覆う前記下層の
酸化珪素薄膜に沿った部分にも形成されており、該ゲー
ト電極下および前記下層の酸化珪素薄膜に沿った部分以
外の部分では除去されていることを特徴とする液晶表示
装置。
3. A semiconductor layer having an insulating substrate, an island-shaped active region, and a source region and a drain region formed on both sides of the active region, the semiconductor layer being formed on the insulating substrate. A thin film semiconductor device having an insulating layer formed so as to cover the active layer and a gate electrode facing the active region of the semiconductor layer via the insulating layer, and a switching element in each pixel portion and / or the insulating layer. In a liquid crystal display device used as a liquid crystal drive circuit arranged on a substrate, the insulating film is a gate insulating film formed of a lower silicon oxide thin film and an upper silicon nitride thin film, and the upper silicon nitride thin film is formed. The thin film is formed so that the planar shape dimension is within 3 μm wider than directly below the gate electrode, and is also formed in a portion along the lower silicon oxide thin film that covers the side surface of the end portion of the island-shaped semiconductor layer. Oh The liquid crystal display device is characterized in that it is removed under the gate electrode and in a portion other than the portion along the lower silicon oxide thin film.
JP4948895A 1995-03-09 1995-03-09 Liquid crystal display device Pending JPH08248402A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4948895A JPH08248402A (en) 1995-03-09 1995-03-09 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4948895A JPH08248402A (en) 1995-03-09 1995-03-09 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH08248402A true JPH08248402A (en) 1996-09-27

Family

ID=12832546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4948895A Pending JPH08248402A (en) 1995-03-09 1995-03-09 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH08248402A (en)

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Effective date: 20041005