JPH0824141B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for groove filling and planarization when insulating isolation of a semiconductor element is performed by groove filling.

2. Description of the Related Art With higher integration of semiconductor devices, miniaturization of element isolation regions has become one of important factors. Therefore, in the conventional method of manufacturing a semiconductor device, the isolation region is reduced by forming a groove in the semiconductor substrate and filling it with an insulating film or the like. For example, referring to FIGS. 3 (a) to 3 (c), first, as shown in FIG. 3 (a), a groove serving as an isolation region is formed on the surface of the semiconductor substrate 31, and then shown in FIG. 3 (b). Thus, a CVD-oxide film 32 having a film thickness almost equal to the groove depth is formed to fill the groove on the silicon substrate 31. Further, a resist pattern 33 having the same film thickness as the surface step, that is, the groove depth is formed in a wide groove (hereinafter referred to as a field region), and a photoresist 34 for planarization is formed on the entire surface to flatten the surface. To do. Next, the photoresist 34, the resist pattern 33 in the field portion and the CVD-oxide film 32 are formed by the etch-back technique.
Was etched at a substantially constant rate to fill the isolation region and the field region with the CVD-oxide film 32 to make it flat as shown in FIG. 3 (c).

However, the conventional manufacturing method shown in FIG. 3 still has the following problems.

(1) When the ratio of groove width to depth {(groove depth) / (groove width)} due to device miniaturization becomes 0.5 or more, when the groove is filled with the CVD-oxide film 32, the CVD oxide film is removed. Even if the cover ledge is formed well, the CVD-oxide film grown from both sides is physically in contact with each other in the central part of the groove, and the film quality of the contacted part is extremely poor. , After partially removing the CVD-oxide film 32 as shown in FIG. 3c,
When the wet etching used for cleaning or the like is performed, the etching rate of the above-mentioned portion having poor film quality is remarkably large, so that the slit 35 is formed from the surface as shown in c. Further, when the CVD-oxide film 32 is formed and the coverage is poor, a cavity called a void 36 is formed near the center of the groove. Therefore, when etch back is applied, voids
36 parts will be slits 35 and will remain on the surface. As described above, in the state where the slits are formed on the surface, there arises a problem that an etching defect is caused when the gate wiring for the MOS transistor is formed later and the gate wirings are short-circuited.

(2) It is necessary to expose the active region of the silicon substrate 31 by etching the CVD-oxide film by etch back.
Considering the uniformity and controllability of oxide film etching, it is necessary to perform over-etching to completely expose the active region, and as a matter of course, the CVD-oxide film portion of the isolation region or the field region is more than the active region. This lowers the characteristics of the MOS transistor formed on the active region and increases the capacitance of the wiring and the substrate formed on the field region, which hinders high-speed operation of the device.

Means for Solving the Problems In the method for manufacturing a semiconductor device of the present invention, the following method is used to solve the problems described above.

First, the semiconductor substrate in the region other than the active region is selectively removed by a desired amount, and in at least one main surface of the substrate on which the groove is formed, a level difference of the groove portion formed on the substrate surface is formed at least over the entire surface. Forming a first insulating film of equal thickness and filling the groove on the surface of the substrate, and an aspect ratio of 0.
Forming an organic thin film pattern in the groove region of 5 or less; removing the first insulating film by using the organic thin film pattern as a mask until the semiconductor substrate in the active region is exposed; and the organic thin film pattern And using the semiconductor substrate in the active region as a mask, removing the first insulating film in the groove until the aspect ratio of the surface recess is 0.5 or less in the groove having the narrowest width, and the organic thin film pattern The step of removing the second insulating film, the step of forming a second insulating film on the entire surface, the step of forming a flattening film on the entire surface to flatten the surface, and the flattening film and the second insulating film at the same speed. It is a method that includes a step of removing the semiconductor substrate in the active region until it is exposed, and fills a groove on the substrate with an insulator and flattens it.

The other is that the semiconductor substrate in the region other than the active region is selectively removed by a desired amount to form a groove, and at least the entire surface of the substrate having the groove is formed. A step of forming a first insulating film having a film thickness substantially equal to the step, a step of forming a first planarizing organic thin film to planarize the surface, the first planarizing organic thin film and the first planarizing film. Removing the desired amount of the insulating film at a constant rate, and further using the semiconductor substrate in the active region as a mask to remove the desired amount of the first insulating film in the groove, and the second insulating film over the entire surface. A step of forming a film, a step of forming a second flattening organic thin film to flatten the surface, and a step of removing the second flattening organic thin film and the second insulating film in a desired amount at a constant rate. Is a method of filling the groove of the substrate with an insulating material and flattening it.

Further, in addition to the method described above, the performance can be improved by forming an etching stopper film on the semiconductor substrate in the active region and removing it after planarization.

Action The present invention having the above-described configuration acts as follows.

(1) When the first insulating film is formed on the stepped substrate, when the groove width-depth ratio {(groove depth) / (groove width)} (hereinafter referred to as aspect ratio) is 0.5 or less, Since the first insulating film is physically in contact with both sides in the central part, the film quality is remarkably deteriorated, or a cavity called a void is formed. Therefore, if an organic thin film for flattening is formed, the surface is flattened and then etched back, and the first insulating film in the groove is removed by a desired amount, the aspect ratio of the groove remaining on the substrate surface is 0.5 or less. Can be On this occasion,
Since the etching rate is high, the portion with poor film quality (or the hollow portion) at the center of the groove becomes a V-type or U-type slit. After that, when the second insulating film is formed on the entire surface, since the aspect ratio of the surface step is 0.5 or less, a portion having poor film quality is not formed in the film of the second insulating film, and a cavity is also formed. Not done. Then, by etching back, the second
After the insulating material is removed and the surface is flattened, even if cleaning such as wet etching is performed, it is possible to perform embedded flattening in which no slit is generated on the surface.

(2) When the etching stopper film is formed on the semiconductor substrate in the active region and then the groove is filled and flattened by the above-mentioned method, when the second insulating film is etched back, the thickness of the etching stopper film is equal to the thickness of the etching stopper film. Even if overetching is performed up to this point, the etching stopper film can be selectively removed later, so that the insulating film in the groove does not become lower than the semiconductor substrate surface in the active region, which can prevent deterioration of device characteristics.

Example A method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a process sectional view for explaining a first embodiment of a semiconductor device of the first invention, in which a P-type (100) silicon (Si) substrate 11 is oxidized. After forming SiO ₂ (50 nm) 12, polysilicon (po
ly Si, 200nm) 13 and phosphorus-doped glass (PSG 800nm) 14
After forming by CVD, a resist pattern 15 is formed in a portion which will be an active region (FIG. 1A). Next, using the resist pattern 15 as an etching mask, PSG 14 and poly Si 13
And SiO ₂ 12 are anisotropically etched by dry etching. Next, after removing the resist pattern 15, PS
The Si substrate 11 is anisotropically etched (800 nm) by dry etching using G14 as an etching mask (FIG. 1B).

Next, after the impurity for channel stop is diffused by ion implantation (not shown in the figure), PSG14 is used by using hydrofluoric acid or the like.
Are selectively removed. At this time, PSG14 has a large significantly etching rate compared with SiO ₂ 12, SiO ₂ 12 is hardly etched. Next, the Si substrate 11 is oxidized (20 nm,
(Omitted in the figure), and then CVD oxide film (1
050 nm) 16 is formed to fill the groove. At this time, a portion having a poor film quality or a cavity is formed where the groove width is narrow (2 μm or less). Further, a resist pattern 17 as an organic thin film pattern is formed in a wide groove region (for example, all portions having a groove width of 3 μm or more) as shown in FIG. 1C. The CVD oxide film 16 is anisotropically etched by dry etching using the resist pattern 17 as an etching mask.
When exposed, the CVD oxide film 16 is etched by about 400 nm using poly Si 13 as an etching mask (FIG. 1D). At this time, depending on the dry etching selection ratio,
The poly Si 13 is reduced to about 100 nm, the step is about 0.3 μm, and the aspect ratio is 0.5 or less at the groove width of 0.6 μm or more.

Further, the portion of the CVD oxide film having a poor film quality in the groove width of 2 μm or less is V-shaped. From this state, oxidize the groove side surface of the Si substrate 11 (20 nm, omitted in the figure)
Then, a CVD oxide film (1000 nm) 18 is formed as a second insulating film. The aspect ratio of the groove width of 0.6 μm or more is 0.5
The CVD oxide film 18 includes portions and cavities with poor film quality because of the following, and because the shape of the groove is V-shaped (or a shape similar to it) as shown in FIG. 1D. Can be formed without. Next, a resist 19 as a flattening film is formed to flatten the surface (FIG. 1E). Next, the resist 19 and the CVD oxide film 18 are etched by the etch-back technique under the condition that the etching rates are almost the same until the poly Si 13 is exposed (FIG. 1F). At this time, poly Si
Since the variation in etching is allowed by the film thickness of 13, the controllability becomes easier. Next, after removing poly Si 13 isotropically by dry etching or wet etching, SiO ₂ 12 is removed by wet etching,
Embedding and planarization are completed (FIG. 1G). After that, a MOS transistor or the like is formed on the active region by a known technique.

(Second Embodiment) FIG. 2 is a process sectional view for explaining a second embodiment of the semiconductor device of the second invention. Similar to the first embodiment, a P-type (100) is shown. Oxide Si substrate to SiO ₂ (50 nm) 12
After forming, poly S as an etching stopper film
After forming i (200 nm) and PSG (800 nm) 14 by CVD,
A resist pattern 15 is formed on a portion which will be an active region (FIG. 2H). Next, using the resist pattern 15 as an etching mask, the PSG 14, poly Si 13 and SiO ₂ 12 are anisotropically etched by dry etching. Next, after removing the resist pattern 15, the Si substrate 11 is anisotropically etched (800 nm) by dry etching using the PSG 14 as an etching mask (FIG. 2I). Next, diffuse impurities for channel stop by ion implantation (not shown in the figure)
After that, PSG14 is selectively removed using hydrofluoric acid or the like.

Next, after the Si substrate 11 is oxidized (20 nm, omitted in the figure), a CVD oxide film (1100 nm) 16 as a first insulating film is formed to fill the groove. At this time, when the groove width is narrow (2 μm or less), a portion or cavity with poor film quality is formed. Further, as shown in FIG. 2J, the resist as the first planarizing organic thin film
A wide groove area (for example, 3μ) to form 20 uniformly.
resist pattern with a film thickness almost equal to the step
17 is formed and a resist 20 for flattening is formed to flatten the plane. Next, the resist 20, the resist pattern 17, and the CVD oxide film 16 are etched by the etch-back technique under the condition that the etching rates are almost the same until the poly Si 13 is exposed. Next, the CVD oxide film 16 is etched by about 400 nm using poly Si 13 on the active region as an etching mask (FIG. 2K). At this time, the aspect ratio at a groove width of 0.6 μm or more is 0.5 or less. Next, Si substrate 1
The side surface of the groove 1 is oxidized (20 nm, omitted in the figure) to form a CVD oxide film (1000 nm) 23 as a second insulating film. CVD oxide film 23
It does not contain any parts with poor film quality or voids.

Next, similar to the above, a wide groove width region (3 μm or more)
Then, after forming a resist pattern 21 having the same film thickness as the step, a resist 22 as a second planarizing organic thin film is formed to flatten the surface (FIG. 2L). Next, the resist 22 and the resist pattern and the CVD oxide film 2 are formed by the etch back technique.
Etch 3 to the point where poly Si 13 is exposed (Fig. 2M). Next, poly Si 13 is selectively removed, and SiO ₂ 12 is removed by wet etching to complete the buried planarization (N in FIG. 2). After that, a MOS transistor or the like is formed on the active region by a known technique.

As described above, in the first and second embodiments, the Si substrate
Although the method of using PSG as an etching mask in the anisotropic etching of 11 has been described, this may use a resist pattern, and after forming the resist pattern 15 on poly Si 13, poly Si 13, SiO ₂ 12 and Etch each Si substrate. After that, the resist pattern may be removed.

In the first embodiment, the resist is used as the planarizing film.
Although the resist 19 and the CVD oxide film 18 were etched back under the condition that the etching rate was the same, the coating baked oxide film (SOG film) may be used as the flattening film.

Furthermore, in the second embodiment, when the resist is flattened, the resist for flattening is formed after the resist pattern having a film thickness almost equal to the step is formed in the wide groove width region. There is no problem even if a resist for planarization is formed without forming.

In the first and second embodiments, the resist pattern 17 is used as the organic thin film pattern, but this can be used as an etching mask during etching, and can perform constant-rate etching when performing etch back. Any thin film such as an inorganic thin film may be used.

EFFECTS OF THE INVENTION As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

(1) Ratio of groove width to groove depth when embedding and flattening a groove in an insulator on a semiconductor substrate {(depth) / (width)}
Regardless of the (aspect ratio), there is no slit and good embedding is possible. Therefore, formation defects such as wirings to be formed later are not caused.

(2) By using an etching stopper film and selectively removing it, the element isolation region can be prevented from falling below the active region, so that the element characteristics can be improved.

(3) By using an etching stopper film,
It becomes easy to set the etching amount at the time of etch back.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining one embodiment of a method for manufacturing a semiconductor device of the present invention, FIG. 2 is a process sectional view for explaining the other embodiment, and FIG. 3 is a conventional example. It is a process sectional view for explaining. 11 …… Si substrate, 13 …… poly Si, 14 …… PSG, 15,17 ……
Resist pattern, 16,18 ... CVD oxide film, 19 ... Resist.

Claims (3)

[Claims] 1. A semiconductor substrate in a region other than an active region is selectively removed by a desired amount and is substantially the same as a step of a groove portion formed on the surface of the substrate at least on the main surface of the substrate where the groove is formed. Forming a first insulating film having a film thickness to fill the groove on the surface of the substrate; forming an organic thin film pattern in the groove region having an aspect ratio of 0.5 or less; and using the organic thin film pattern as a mask, A step of removing the first insulating film until the semiconductor substrate in the active region is exposed, and further, using the organic thin film pattern and the semiconductor substrate in the active region as a mask, the aspect ratio of the concave portion on the surface in the groove portion having the narrowest width Until the ratio becomes 0.5 or less, the step of removing the first insulating film in the groove, the step of removing the organic thin film pattern, the step of forming the second insulating film on the entire surface, and the planarization on the entire surface. Shape the membrane A step of flattening the surface,
A semiconductor having a step of removing the flattening film and the second insulating film at a constant rate until the semiconductor substrate in the active region is exposed, the groove on the substrate is filled with the insulating film, and the surface is made flat. Device manufacturing method. 2. A step of forming a first insulating film on at least the entire main surface of a substrate in which a groove is formed by selectively removing a desired amount of the semiconductor substrate in a region other than the active region and filling the groove. A step of forming a first planarizing organic thin film to flatten the surface, removing the desired amount of the first planarizing organic thin film and the first insulating film at a constant rate, and Using the semiconductor substrate in the region as a mask, the first
Removing a desired amount of the insulating film, forming a second insulating film on the entire surface, forming a second planarizing organic thin film to planarize the surface, and the second planarizing A method of manufacturing a semiconductor device, which comprises a step of removing a desired amount of the organic thin film and the second insulating film at a constant rate, so that the groove of the semiconductor substrate is filled with the insulating film and flattened. 3. A substrate in which an etching stopper film is formed on a semiconductor substrate to be an active region, and the semiconductor substrate other than the active region is selectively removed in a desired amount, and the groove of the semiconductor substrate is filled and flattened. 3. The method of manufacturing a semiconductor device according to claim 1, wherein damage to the semiconductor substrate in the active region is prevented by selectively removing the etching stopper film thereafter.