JPH0824133B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a structure of a control electrode for improving the characteristics of a compound semiconductor transistor used in a microwave or millimeter wave band, And a method for manufacturing a semiconductor device using a control electrode having a plurality of feeding points.

[Prior Art] FIG. 6 shows a basic field effect transistor (Field Effe
ct Transistor; hereinafter referred to as FET). In the figure, reference numeral 1 denotes a semiconductor substrate on which a conductive layer, an insulating layer and the like necessary for operation are formed. Reference numeral 2 is a gate electrode for modulating a current flowing from the drain electrode 3 to the source electrode 4 by an applied electric field.

Now, one of the major applications of such FET is a low noise amplifier. In this application, the most important figure of merit is the noise figure (N
F). Since NF deteriorates as the frequency used increases, various measures are required to use it at extremely high frequencies such as microwaves and millimeter waves. Minimum noise figure (NF _min )
Is usually expressed by the following equation.

Where gm is transconductance, Rs is source series resistance, Rg is gate resistance, Cgs is gate-source capacitance, K _f
Is a constant and f is a frequency. As you can see from the above formula,
In order to reduce NF, it is important to increase transconductance gm, reduce gate-source capacitance Cgs, gate-source resistance Rs, and gate resistance Rg.

The most effective way to reduce Cgs and increase gm is to shorten the device gate length (Lg). Recently, GaAs MESFET and HEMT (High E
In devices such as lectron Mobility Transistor) Lg
It is usually formed to be very fine with a thickness of 0.5 μm or less. However, reduction of shortening the gate cross-sectional area of Lg, thus leading to increase in Rg, the reduction of NF is the gate electrode of the rectangle as shown in FIG. 6 there is a limit, the value of NF _min in example frequency 12 GHz 1 dB Stay back and forth.

One measure for reducing Rg is to make the gate electrode T-type as shown in FIG. In FIG. 7, 2
Is a gate electrode and has a T-shaped cross section,
Lg is a portion in contact with the semiconductor substrate 1, and even if it is formed to be very fine (for example, 0.2 μm), it is enlarged at the upper portion to increase the cross-sectional area, thereby suppressing an increase in Rg. With such a structure, an element having an NF _min of 0.5 to 0.6 dB is realized, which shows that the reduction of Rg is extremely effective. However, forming a T-shaped gate electrode reduces Lg
This is not industrially easy because it must be made as fine as 0.2 μm.

Further, FIG. 8 is a plan view of the FET. In the figure, 2a
Is a gate finger, 2b is a gate pad, 3 is a drain electrode, 4 is a source electrode, and 5 is a feeding point for applying a voltage to the gate finger 2a. Figures 6 and 7 are shown in Figure 8.
This corresponds to the cross section at VI, VII-VI, VII in the figure. Wires are bonded to the gate pad 2b to connect to the outside.

Normally, the FET element is configured as shown in FIG. 8, voltage is applied to the gate finger 2a from two feeding points 5, and the length of the gate finger 2a (total gate width: W
g) is electrically divided into four, and the unit gate width Z is Wg /
It will be 4. Gate resistance Rg and total gate width W
Between g and unit gate width Z, It can be seen that it is effective to increase the number of feeding points 5 and reduce the unit gate width Z if the total gate width Wg is the same.

In this way, by increasing the number of feeding points, it is possible to prevent the increase of Rg, but if the number of feeding points is simply increased with the configuration shown in FIG. 8, the number of gate pads 2b also increases and the connection with the outside is increased. And a large area of the gate pad increases the stray capacitance.

Therefore, FIG. 9 shows an example in which the number of power feeding points is increased without increasing the number of gate pads. The figure (a) is a top view and the figure (b) is a partial cross section schematic diagram in bb in the figure (a).

In this configuration, the number of feeding points is five, the unit gate width Z is Wg / 10, and Rg is greatly reduced. The gate pad 2b and the feeding point 5 are connected by the gate wiring 6, but the gate wiring 6 intersects with the source electrode 4. The gate wiring 6 and the source electrode 4 are, of course, electrically insulated, but it is necessary to be careful not to increase the capacitance between them. Therefore, as shown in FIG. The wiring 6 is arranged so as to float above the source electrode 4. Such a structure is usually called an air bridge,
Since air has a smaller dielectric constant than an insulating film such as SiO ₂ , the capacitance can be reduced. The example shown in FIG. 9 is, for example, IEICE Technical Report vol.88 No.60 pp.39-
44 (1988), and according to such a configuration,
Even without using a gate with a T-shaped cross section, it is as good as 0.5 to 0.6 dB.
It has been shown that NF _min can be achieved.

As a method for reducing the gate resistance, a configuration as shown in Fig. 10 is also considered (European Patent 0203225A2, IEE Transactions on Electron Devices, ED-32, No. 12, December 1985). , 2754 ~ 2759
Page "Air Bridge Gate FET For GaAs Monolithic Circuit" (IEEE Transactions on Electron Devi
ces, Vol, ED−32, No12, December1985 pp.2745 ~ 2759, Airb
ridge Gate FET for GaAs Monolithic circuits ")).
9A is a plan view thereof, and FIG. 8B is a sectional view taken along line bb in FIG.

In this configuration, the gate wiring 6 adopts an air bridge structure based on the same idea as in FIG. 8, but a characteristic is that power supply is performed not in points but in the entire gate width. If such a configuration is adopted, Rg can be reduced to a value that can be practically ignored, and it is obvious that it is very advantageous in terms of low noise performance. However, since the gate electrode 6 and the source electrode 4 intersect with each other in a large area, the increase of the gate capacitance is extremely problematic even if the air bridge structure is adopted.

[Problems to be Solved by the Invention]

As described above, various methods have been tried to reduce the gate resistance to form a low noise FET, but the manufacturing method is very difficult from an industrial point of view, and the gate resistance is adversely affected. Performance improvement was insufficient due to the increase in capacity.

The present invention has been made to solve the above problems, and it is possible to increase the number of gate feeding points and reduce gate resistance without increasing a gate pad or a gate capacitance, and to provide a semiconductor device having excellent noise performance. An object of the present invention is to provide a structure and a method of manufacturing a semiconductor device using a control electrode having a plurality of feeding points.

[Means for solving the problem]

A semiconductor device according to the present invention includes a plurality of feeding points on a gate finger extending on a substrate of a field effect transistor and a portion of the gate finger on which air is interposed, and the adjacent feeding points are connected to each other. And a gate pad connected to the gate wiring for inputting an external signal, and the gate wiring does not intersect the source electrode in the range from the gate finger to the gate pad. Is.

Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a linear gate finger having a uniform width on a semiconductor substrate, a step of forming a thin insulating film so as to cover the gate finger, A step of forming a contact hole in the film to expose a part of the gate finger and using the exposed portion as a feeding point; a step of forming a contact pad so as to cover the contact hole; and an opening on the contact pad. The method includes a step of forming a resist layer having a portion, a step of forming a gate wiring connected to the contact pad on the resist layer, and a step of removing the resist layer.

[Action]

In the semiconductor device of the present invention, a plurality of feeding points on the gate finger extending on the substrate, and a gate wiring that is located at a portion of the gate finger on which air is interposed and connects the adjacent feeding points to each other. A gate pad that is connected to the gate wiring and inputs a signal from the outside, and the gate wiring does not intersect with the source electrode in the range from the gate finger to the gate pad. Eliminate the intersection of the source electrodes,
It is possible to reduce the gate resistance without increasing the gate capacitance, and it is possible to configure an FET having good noise performance.

Further, in the method for manufacturing a semiconductor device of the present invention,
Forming a linear gate finger having a uniform width on a semiconductor substrate; forming a thin insulating film so as to cover the gate finger; and forming a contact hole in the insulating film to form one of the gate fingers. Of the exposed portion and using the exposed portion as a feeding point, a step of forming a contact pad so as to cover the contact hole, a step of forming a resist layer having an opening on the contact pad, and the resist Since a step of forming a gate wiring connected to the contact pad on the layer and a step of removing the resist layer are included, a gate feeding point is formed in a region limited to the contact hole on the gate finger. Therefore, the size of the gate feeding point can be made as small as technically possible. In addition, since the region serving as the feeding point is not formed when the gate finger is formed, the gate finger has a pattern having a single width, and when the gate finger is formed in the recess portion of the substrate, the recess etching can be performed with good controllability. Furthermore, with such a single-width gate finger, the throughput of the EB direct writing process of the resist pattern for forming the gate finger is improved.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view and FIG.
Shows a schematic perspective view. Gate finger in the figure
There are five feeding points 5 on the 2a, and the feeding points 5 are connected to each other by the air bridges by the gate wirings 6 located at the positions on the gate finger 2a where the air is interposed. External gate pad 2b from the dot
It is configured to pull out to.

As described above, in this embodiment, the feeding points 5 of the gate finger 2a are connected by the gate wiring 6 through the air just above the gate finger 2a, and then a part of the gate wiring 6 is pulled out to the external gate pad 2b. Therefore, it is possible to eliminate the intersection between the gate wiring 6 and the source electrode 4 even when the number of feeding points is large, and it is possible to effectively reduce the gate resistance without increasing the gate capacitance C _gs. it can. For example, in the conventional configuration shown in FIG. 6, as the feeding point 5 increases, the gate wiring 6 and the source electrode 4 are
While the increase in the gate capacitance C _gs caused by the intersection of 15% of the total C _gs is 15% of the total C _gs , the increase of the gate capacitance C _gs is eliminated by eliminating the intersection of the gate wiring 6 and the source electrode 4. It can be set to 0%, which allows the minimum noise figure NF _min
Can be improved from 0.6 dB to 0.52 dB.

FIG. 2 shows an example of the semiconductor device according to the second embodiment of the present invention in which the connection to the gate pad is made from the end of the gate wiring. The same figure (a) is a top view and the same figure (b).
Shows the IIb-IIb cross section in FIG. The only difference from the first embodiment is the portion that is connected to the outside.

In the second embodiment, it is possible to form a wiring in which the gate wiring 6 and the source electrode 4 do not intersect at all when the pattern is viewed from directly above, and it is possible to suppress an increase in the gate capacitance even if the number of feeding points is increased. . Further, the cross-sectional area of the gate wiring 6 can be made much larger than the cross-sectional area of the gate finger 2a, which effectively reduces the Rg.

Further, FIG. 2 (c) is a schematic view showing an example of a IIc-IIc cross section of FIG. 2 (a). This configuration is source series resistance Rs
This is a device for reducing the noise, and the gate finger 2a is arranged close to the source electrode 4 as shown in the figure. For example, the source-gate distance L _sg is 1 μm and the gate length L is
_{The g} is 0.5 μm, and the drain-gate distance L _dg is about 2 μm.

Further, in such a structure, since the gate wiring 6 is formed close to the drain electrode 3 side, the distance between the gate wiring 6 and the source electrode 4 can be increased, and an increase in capacitance can be prevented. It is also possible.

The gate wiring 6 of this embodiment has a width of 3 μm and a height of 2 μm.
It is possible to easily form the wiring to this extent by the plating technique or the like as described above.

In addition, in the above-described first and second embodiments, the gate wiring 6 is led out to the gate pad 2b by the gate finger.
2a It is performed from the central portion or the end portion, but the extraction position is not limited to these for the purpose of the present invention, and the extraction electrode is not limited to one. Furthermore, as shown in FIG. 1 (b), the extraction electrode portion does not necessarily have to be wired in the air as shown in FIG. 1 (b).

Further, the above-described embodiments can be applied to all control electrode structures of field effect transistors such as HEMT and GaAs MESFET used in a high frequency region.

In addition, FIGS. 4A to 4E are process flow diagrams showing a method of forming a feeding point contact.

In the figure, 1 is a semiconductor substrate, and 12 is this semiconductor substrate 1.
The opening 13 is formed by the register pattern formed above. Reference numeral 14 is a gate finger formed by using the pattern 13, and 15 is a gate feeding point. 16 is an insulating film that opens the contact hole 17, 18 is a gate contact pad for connecting to the outside for inputting a signal to the gate finger 14, and 19 and 21 are gate wirings.

 Next, the manufacturing method of FIG. 4 will be described.

First, the resist film 12 is applied onto the semiconductor substrate 1, and the opening 3 is formed by using optical exposure, EB (electron beam) exposure, or the like (FIG. 4A).

Next, using this pattern 13, a gate electrode pattern is formed by a vapor deposition lift-off method. At this time, normally, the gate finger 14 is set to a width of 1 μm or less (preferably about 0.2 μm), and the gate feeding point 15 is set to a width of several μm (preferably about 5 μm) (FIG. 4 (b)). .

Next, after depositing an insulating film 16 on the entire surface, a contact hole 17 is provided on the gate feeding point 15 to expose the gate electrode layer (FIG. 4 (c)).

Further, a gate contact pad 18 is provided on the gate feeding point 15 and a contact hole is similarly opened (FIG. 4 (d)).

Further, a first resist is deposited to a film thickness of about 2 μm on the entire surface, holes are formed in the first resist on the contact holes 17 by photolithography, and a conductive layer such as Ti / Au is formed on the entire surface of the substrate by a method such as sputtering. 21 is further provided, a second resist is further deposited on the conductive layer 21, and the second resist in a region corresponding to the gate wiring formation portion is removed by exposure and development, and then an electric field is applied to the gate wiring formation portion. Au by plating method
Are deposited to form the gate wiring 19. After that, the second resist is removed by an organic solvent or the like, the conductive layer around the gate wiring 19 is removed by a dry etching method such as ion milling, and the second resist existing between the gate wiring 19 and the gate finger 14 is further removed by an organic solvent. The resist of No. 1 is removed, and the gate wiring 19 and 21 of the air bridge structure is provided on the gate feeding point 15.
Were connected (No. 4 (e)).

 However, the above manufacturing method has three problems.

First, in the step of forming the pillar 21 of the conductive layer that connects the gate wiring 19 and the gate feeding point 15, in forming the pillar 21, the thickness of the pillar 21 is equal to the height of the air bridge (about It is necessary to provide a first resist having a thickness of about 2 μm to 3 μm) and to make a hole on the contact hole 17 so as to penetrate the first resist. However, due to the relationship between the photolithographic alignment margin and the resolution. The diameter of the contact hole is usually required to be 5 μm or more. Then, the size of the contact hole diameter is directly reflected on the area occupied by the gate feeding point.

Generally, in the case where the gate feeding point 15 has to be located near the drain electrode or the source electrode in the structure of the transistor like this structure, the area of the feeding point 15 has a bad influence on the performance of the transistor. Influences the size of the parasitic capacitance.

Therefore, in the case where the area of the feeding point is as large as 5 μm or more as in the above structure, there is a problem that the parasitic capacitance increases and the transistor performance is significantly deteriorated.

Further, the width of the gate finger 14, that is, the gate length is designed to be as small as 0.5 μm or less in order to improve the performance of the transistor. At present, the EB exposure method is widely used for forming a gate electrode having a gate length of 0.5 μm or less. However, this is because the resist is exposed with an electron beam that is narrowed down to about 0.1 μm.
As shown in FIG. 7A, when forming the opening 13 whose drawing area is increasing at the gate feeding point portion in the middle, a large time loss is caused at the gate feeding point portion, resulting in a decrease in throughput. It was.

Further, although omitted in FIG. 4, before the formation of the gate electrode, a step called recess, that is, the substrate in the opening is slightly etched by etching in the state of FIG. It is widely practiced to form a gate electrode in the recess opening 20 of the substrate as shown in Fig. 2 and adjust the characteristics.However, during this recess etching, the etching rate is around the gate feeding point where the opening area changes. It was liable to fluctuate and the controllability of the characteristics deteriorated.

Therefore, a method for manufacturing a semiconductor device, which can suppress the increase in parasitic capacitance, which is the above-mentioned problem, can improve the throughput at the time of EB writing, and can make the recess uniform, is described below.

The manufacturing method according to the present invention forms the gate feeding point in a step different from the gate finger forming step,
The gate feeding point is formed in a region limited to the contact hole after the gate finger forming step.

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing respective main steps of a method of manufacturing a semiconductor device having a control electrode having a plurality of feeding points according to an embodiment of the present invention, in which 1 is a semiconductor substrate and 12
An opening 13 is formed in the resist pattern formed on the substrate 1 at a portion corresponding to a gate finger forming portion. Reference numeral 14 is a gate finger formed by using the pattern 13, and 16 is an insulating film for opening the contact hole 17. Further, 18 is a gate contact pad connected to the gate feeding point, and 19 and 21 are gate wirings connected to the gate feeding point 17 for inputting a signal from the outside.

 The manufacturing method of FIG. 3 will be described below.

First, the resist film 12 is applied on the semiconductor substrate 1, and the opening 3 is formed by using optical exposure or EB exposure (FIG. 3A). At this time, unlike the above-described manufacturing method shown in FIG. 4, the portion where the feeding point pad 18 is formed later is not particularly thick.

Next, a gate electrode pattern, that is, a gate finger is formed by vapor deposition lift-off method using this pattern 12 (FIG. 3 (b)). At this time, the gate feeding point pad is not formed in appearance.

Next, after forming the insulating film 6 on the entire surface, a contact hole 17 is opened in a portion where the gate feeding point pad is to be formed, and a part of the gate electrode is exposed. At this time, since there is no structural restriction, the size of the contact hole can be made as small as technically possible, and for example, a 1.5 μm square contact hole can be easily formed on the gate finger (third part). Figure (c)).

Next, a wiring metal 18 is provided at a portion which will be a gate feeding point opened by the contact hole 17, and an opening portion is similarly formed on the contact hole 17 (FIG. 3 (d)).

After the formation of the wiring metal 18, as described above, the first resist having an opening on the contact hole 17 is provided, and the conductive layer 21 such as Ti / Au is provided on the entire surface of the substrate by a method such as sputtering. A second resist is provided on the conductive layer 21, the second resist in the gate wiring formation portion is removed by exposure and development, and the removed portion is Au plated by a method such as electroplating.
Are deposited to form the gate wiring 19. After that, the second resist is removed with an organic solvent or the like, the conductive layer around the gate wiring 19 is removed by dry etching, and then the remaining first resist is removed with the organic solvent to obtain the gate feeding point 15 Air bridge structure gate wiring on top 19,21
To form.

The gate wiring thus formed is drawn out from the central feeding point portion and connected to the gate pad formed outside, whereby the structure shown in FIG. 1 is obtained.

According to the manufacturing method of this embodiment, since the gate finger formation and the gate contact pad formation are performed in separate steps, the EB direct writing has a single width as shown in FIG. Since it is only necessary to draw the pattern that it has and the drawing area does not increase unlike the conventional case, the throughput at the time of drawing can be greatly improved.

Further, since the area of the opening 13 does not change in the resist pattern 12, uneven etching is less likely to occur when etching for providing the recess opening in the substrate, and the recess can be formed with good controllability and reproducibility. Can be formed.

Further, in this embodiment, the size of the gate feeding point is determined by the size of the contact hole of the insulating film 6 formed in the step of FIG. 3C, and the size of this contact hole is the alignment margin and resolution of the photolithography. Since the film thickness of the insulating film 6 can be reduced to about 1.5 μm square,
The parasitic capacitance can be significantly reduced.

〔The invention's effect〕

As described above, according to the present invention, the gate feeding points are directly connected to each other on the gate finger by the aerial wiring, and the gate wiring which is the aerial wiring is in the range from the gate finger to the gate pad. Since it does not intersect with the source electrode, it is possible to reduce the gate resistance by increasing the feeding point without increasing the capacitance between the gate electrode and the source electrode by eliminating the intersection between the gate wiring and the source electrode. There is an effect that a low noise semiconductor element can be easily manufactured industrially.

Further, according to the present invention, since the gate finger formation and the gate contact pad formation are performed in separate steps, the throughput during EB direct writing can be significantly improved, and uneven etching during recess is less likely to occur. Has the effect of Further, as seen in the embodiment, the size of the gate feeding point can be reduced, so that the parasitic capacitance can be reduced, and high-performance transistors can be manufactured with a high yield.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and a perspective view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 (a).
(C) is a plan view and a sectional view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 3 shows a method of manufacturing a gate power supply contact according to an embodiment of the method of manufacturing the semiconductor device of the present invention. FIG. 4 is a perspective view of an essential part, FIG. 4 is a perspective view of an essential part showing a method of manufacturing a gate feeding contact corresponding to the conventional example of FIG. 3, and FIG. 5 is a view showing a state in which a recess is formed in the substrate of FIG. , FIG. 6 is a cross-sectional view of an essential part of a conventional basic FET, FIG. 7 is a cross-sectional view of an essential part of an FET having a conventional T-type gate, FIG. 8 is a plan view of a conventional FET, and FIG. a),
FIG. 10B is a plan view and a cross-sectional view of a conventional FET having a plurality of feeding points, and FIGS. 10A and 10B are plan views and cross-sectional views of other conventional semiconductor devices. In the figure, 1 is a semiconductor substrate, 2 is a gate electrode, and 2a, 14
Is a gate finger, 2b is a gate pad, 3 is a drain electrode, 4 is a source electrode, 5,15 are gate feeding points, 6,19,21
Is a gate wiring, 12 is a resist, 13 is an opening, 16 is an insulating film, 17 is a contact hole, and 18 is a gate contact pad. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A semiconductor device including a field effect transistor used in a high frequency band, comprising: a plurality of feeding points on a gate finger extending on a substrate of the field effect transistor; and a portion on the gate finger where air is interposed. Positioned gate wiring connecting the adjacent feeding points to each other, and a gate pad connected to the gate wiring and inputting an external signal, the gate wiring extending from the gate finger to the gate pad. A semiconductor device characterized by not intersecting with a source electrode in a range. 2. The semiconductor device according to claim 1, wherein the gate wiring on the gate finger is offset to the drain electrode side with respect to the gate finger. 3. A method of manufacturing a semiconductor device, comprising a step of connecting a gate wiring to a gate pad to a gate finger of a field effect transistor formed on a semiconductor substrate, wherein a linear gate having a uniform width on the semiconductor substrate. Forming a finger, forming a thin insulating film so as to cover the gate finger, forming a contact hole in the insulating film to expose a part of the gate finger, and using the exposed portion as a feeding point. A step of forming a contact pad so as to cover the contact hole, a step of forming a resist layer having an opening on the contact pad, and a step of forming a gate wiring connected to the contact pad on the resist layer. A method of manufacturing a semiconductor device, comprising: a forming step; and a step of removing the resist layer.