JPH04245682A - Field effect transistor - Google Patents

Abstract

PURPOSE:To minimize the loss in high frequency current in a gate bus line and hence provide high gain. CONSTITUTION:The fingers of each of electrodes 2, 3 and 4 for a gate, a source and a drain are installed to a semiconductor substrate in parallel to each other in a comb shape. A gate electrode bus line 2a is adapted to be thicker than a wiring film of the gate electrode 2, using a plated wiring layer. At the same time, the finger of the gate electrode 2 is connected with gate bus line 2a at a through hole in the thick direction of the semiconductor substrate. This construction makes it possible to minimize the resistant value of a field effect transistor and reduce its loss, and hence increase the maximum available gain as well.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave field effect transistor used in a monolithic microwave IC constructed on a semiconductor dielectric substrate, and more particularly to a field effect transistor with a high gain.

0002

2. Description of the Related Art Generally, a semiconductor device comprising a plurality of field effect transistors arranged in parallel employs a structure in which fingers of gate, source and drain electrodes are arranged in a comb-like shape.

For example, as shown in FIG. 6, a field effect transistor 1 has gate electrodes 2 arranged at predetermined intervals.
Source electrodes 3 and drain electrodes 4 are alternately arranged between the plurality of gate electrodes 2. Of these gate electrodes 2, source electrodes 3, and drain electrodes 4, the gate electrodes 2 and drain electrodes 4 in particular pass through the respective bus lines 2a and 4a and are gathered at the respective extraction electrodes 5 and 6, and are not shown in the drawings. Extended and connected to the circuit.

On the other hand, in the manufacturing process of field effect transistors, gate electrode wiring (mainly by sputtering etc.) for forming the gate electrode 2 is used as an electrical wiring means.
A plated wiring layer (mainly made of plated metal, several microns thick) is provided on the top layer of the semiconductor substrate, which can intersect three-dimensionally with this layer (several thousand angstroms thick). The gate bus line 2a uses the gate electrode wiring, the drain electrode 4 and the drain bus line 4a use a plating wiring layer because of the large current density, and the source extraction electrode 7 that intersects the drain bus line 4a uses the gate electrode wiring. ing.

[0005]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional field effect transistor, the gate electrode wiring is used as the gate bus line, and the thickness of this wiring is as thin as several thousand angstroms, and the electrical resistance is large. The drawback is that the loss of high-frequency current in this part is large, and the maximum available gain of the field-effect transistor cannot be fully exploited.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a field effect transistor that achieves high gain by reducing loss of high frequency current in a gate bus line.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the field effect transistor of the present invention is a field effect transistor in which fingers of gate, source, and drain electrodes are arranged side by side in a comb-like shape on a semiconductor substrate. , a drain lead electrode is arranged at one diagonal position of a virtual quadrilateral surrounding these electrodes, and the gate electrode is placed on the side of the virtual quadrilateral that is perpendicular to the electrode finger and does not include the drain bus line. The configuration is such that the gate bus line is thicker than the thickness of the gate bus line.

[0008] If necessary, the gate bus line is formed of a wiring metal provided on the uppermost layer of the semiconductor substrate.

Furthermore, if necessary, the fingers of the gate electrode and the gate bus line are connected through through holes in the thickness direction of the semiconductor substrate.

0010

[Operation] According to the field effect transistor having the above structure, since the thickness of the gate bus line is made thicker than that of the gate electrode, the electrical resistance is reduced accordingly, and the loss of high frequency current is reduced.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a field effect transistor according to an embodiment, and FIG. 2 is a sectional view thereof.

The field effect transistor 1 according to the embodiment is as follows:
The fingers of the gate electrode 2, source electrode 3, and drain electrode 4 are arranged in parallel in a comb tooth shape. The gate electrode 2 and the drain electrode 4 are connected to a gate bus line 2a and a drain bus line 4a, respectively, which are provided on sides of a virtual quadrilateral that are perpendicular to each electrode. The gate bus line 2a and the drain bus line 4a are collected at a gate extraction electrode 5 and a drain extraction electrode 6, respectively. Further, the source electrodes 3 are assembled into a source extraction electrode 7.

The gate electrode 2 is formed of a gate electrode wiring layer metal such as a sputtered gold film. Further, the gate bus line 2a is formed of a plating wiring layer such as gold plating provided on the uppermost layer of the semiconductor substrate 10, and is formed to be thicker than the gate electrode 2. The gate electrode 2 and the gate bus line 2a are connected through a through hole 8,
The gate lead electrode 5 (gate electrode lead pad) is reached.

The source electrode 3 is formed of a plated wiring layer,
As in the conventional example, a through hole is formed by a line (not shown) formed of a gate wiring layer crossing the lower part of the drain bus line 4a to pass through the drain bus line 4a and to the source electrode 7 formed of a plated wiring layer. 8.

Reference numeral 9 is an interlayer insulating film formed of a silicon oxide film or the like, and 10 is a semiconductor substrate of gallium arsenide or the like.

Now, FIG. 3 shows the results of a comparison of the maximum available gain between the conventional example shown in FIG. 6 and the field effect transistor in the embodiment shown in FIG. 1 by electronic computer simulation.

In this simulation, a 0.4 μm thick sputtered gold film was used as the gate electrode wiring layer metal, and a 2 μm thick gold plating was used as the plated wiring layer metal. Further, the width of the gate bus line 2a is 2 μm, and the width of the drain bus line 4a is 10 μm (unit gate width 20 μm).
0 μm, and the total gate width is 1000 μm (5 parallel connections of 200 μm).

In FIG. 3, curve (B) shows the case of the conventional example, and curve (A) shows the case of this embodiment. Curve (B) and curve (A), respectively 10 GHZ or less, 1
Below 2 GHz, the K factor, which indicates the operational stability of a field effect transistor, becomes less than 1, and the maximum available gain cannot be calculated, so in this case, the maximum stable gain when K = 1 is shown (Figure 3 middle dashed line).

In comparing the maximum available gain, the curve (A
), the resistance value of the gate bus line 2a is lower than that of curve (B) due to its increased cross-sectional area.
), it can be seen that the increase is 1.6 dB compared to 7.3 dB.

FIGS. 4 and 5 show a field effect transistor according to a second embodiment. In this case, a large number of gate lead-out electrodes 5 are arranged, and in this case, the maximum available gain is further increased because the phase shift of the gate input drive signal to each cell is reduced.

[0022]

Effects of the Invention As explained above, according to the field effect transistor of the present invention, a plated wiring layer is used for the gate electrode bus line, and the thickness thereof is made thicker than the gate wiring film, thereby reducing the resistance value and reducing the loss. The effect is that the maximum available gain of the field effect transistor can be increased.

As a result, it is possible to reduce the number of field effect transistors constituting the microwave radio amplifier and to reduce the chip size of the microwave monolithic integrated circuit, which has a great effect on cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA in FIG. 1;

FIG. 3 is a characteristic comparison graph of the maximum available gain between the embodiment of the present invention and the conventional example.

FIG. 4 is a plan view showing a field transistor according to a second embodiment of the present invention.

5 is a sectional view taken along line BB in FIG. 4. FIG.

FIG. 6 is a plan view showing an example of a conventional field effect transistor.

[Explanation of symbols]

1 Field effect transistor 2 Gate electrode 2a Gate bus line 3 Source electrode 4 Drain electrode 4a Drain bath line 5 Gate extraction electrode 6 Drain extraction electrode 7 Source extraction electrode 8 Through hole 9 Interlayer insulation film 10 Semiconductor substrate

Claims (3)

[Claims] Claim 1: In a field effect transistor in which fingers of gate, source, and drain electrodes are arranged side by side in a comb shape on a semiconductor substrate, a drain lead-out is provided at one diagonal position of a virtual quadrilateral surrounding these electrodes. A field effect transistor characterized in that an electrode is arranged, and a gate bus line thicker than the gate electrode is arranged on a side of the virtual quadrilateral that is perpendicular to the electrode finger and does not include the drain bus line. . 2. The field effect transistor according to claim 1, wherein the gate bus line is made of a wiring metal provided on the uppermost layer of the semiconductor substrate. 3. The field effect transistor according to claim 1, wherein the fingers of the gate electrode and the gate bus line are connected through a through hole in the thickness direction of the semiconductor substrate.