JPH08236685A - Lead frame structure of semiconductor package - Google Patents

Lead frame structure of semiconductor package

Info

Publication number
JPH08236685A
JPH08236685A JP7345711A JP34571195A JPH08236685A JP H08236685 A JPH08236685 A JP H08236685A JP 7345711 A JP7345711 A JP 7345711A JP 34571195 A JP34571195 A JP 34571195A JP H08236685 A JPH08236685 A JP H08236685A
Authority
JP
Japan
Prior art keywords
mounting plate
chip mounting
chip
lead frame
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7345711A
Other languages
Japanese (ja)
Other versions
JP2767404B2 (en
Inventor
In Gyu Han
Jeong Lee
Doo Hyun Park
Hee Yeoul Yoo
Youn Cheol Yoo
チョン イ
トゥ ヒョン パク
イン キュ ハン
ヨン チョル ユー
ヒ ヨール リュウ
Original Assignee
Anam Ind Co Inc
アナムインダストリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR2019940033994U priority Critical patent/KR200143924Y1/en
Priority to KR1019940037168A priority patent/KR100201062B1/en
Priority to KR1994U33994 priority
Priority to KR1994P37168 priority
Application filed by Anam Ind Co Inc, アナムインダストリアル株式会社 filed Critical Anam Ind Co Inc
Publication of JPH08236685A publication Critical patent/JPH08236685A/en
Application granted granted Critical
Publication of JP2767404B2 publication Critical patent/JP2767404B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To prevent the interface separating phenomenon generated from an adhering part with a semiconductor chip adhered to a chip mounting plate by reducing the area of the chip mounting plate compared with the area of a face on a semiconductor chip adhering side and providing a connecting part between tie-bars and the chip mounting plate. SOLUTION: This system is provided with a lead 8 positioned at a peripheral part, a chip mounting plate 3 adhered with a semiconductor chip C and tie-bars T1 to T4 supporting this plate 3. The chip C is mounted by adhering to a part of the plate 3 and a connecting part 4 connected to its outside with the plate 3 in a center by epoxy resin. The area of the plate 3 is particularly reduced compared with the area of the face on the adhering side of the semiconductor chip C. In addition a part 4 is provided between the tie-bars T1 to T4 and the chip mounting plate 3. Thereby the deformation of the plate 3 by thermal expansion is reduced to prevent interface separation between the plate 3 and the chip C.

Description

【発明の詳細な説明】Detailed Description of the Invention
【0001】[0001]
【発明の属する技術分野】本発明は半導体パッケージの
リードフレーム構造に関し、特に、半導体チップを搭載
するリードフレームのチップ搭載板を固定観念の四角板
体から逃れて体積や面積をより小さくした新しい形態の
チップ搭載板を提供することで、接着面積を少なくして
接着された半導体チップとチップ搭載板の熱膨張差によ
る体積変形を極小化した半導体パッケージのリードフレ
ーム構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame structure of a semiconductor package, and more particularly to a new form in which a chip mounting plate of a lead frame on which a semiconductor chip is mounted is escaped from a square plate body of a fixed idea to reduce its volume and area. The present invention relates to a lead frame structure of a semiconductor package in which the bonding area is reduced to minimize the volume deformation due to the difference in thermal expansion between the bonded semiconductor chip and the chip mounting plate.
【0002】[0002]
【従来の技術】一般に、半導体パッケージのリードフレ
ームは金属材で構成され、この金属材のリードフレーム
の周縁部はリードが配列され、そのリードフレームの内
部には半導体チップを搭載するチップ搭載板を備え、搭
載板に搭載される半導体チップに備えられたチップパッ
ドと前記各リードとの間には各々ワイヤーをボンディン
グさせ、それによって、半導体チップと各リードとの間
で電気的信号を伝達できるようにしたものである。前記
リードフレームのチップ搭載板に搭載され、そのリード
フレームと材質の異なる半導体チップと各リードとのワ
イヤーボンディング作業が完了した半導体パッケージ半
製品はパッケージモールディング工程で合成樹脂材であ
るコンパウンド、例えばエポキシ樹脂などでバッケージ
成形されることにより単一体の半導体パッヶージが完成
されるようにした。しかし、各工程を経ながら必要によ
って高温の作業工程条件で製造される従来の半導体パッ
ケージのリードフレームは図1に示すようにリードフレ
ームの内部に備えられたチップ搭載板3の面積が半導体
チップCの接着側の面全体面積を収容できるように広く
構成することによりチップ搭載板3にエポキシ樹脂Eで
接着された半導体チップC面とチップ搭載板3面との間
の接着面積が広くなっていた。
2. Description of the Related Art Generally, a lead frame of a semiconductor package is made of a metal material, and leads are arranged on the peripheral portion of the metal lead frame, and a chip mounting plate for mounting a semiconductor chip is provided inside the lead frame. A wire is bonded between each of the leads and the chip pad provided on the semiconductor chip mounted on the mounting plate, so that an electrical signal can be transmitted between the semiconductor chip and each lead. It is the one. The semiconductor package semi-finished product mounted on the chip mounting plate of the lead frame and completed the wire bonding work between the semiconductor chip of different material from the lead frame and each lead is a compound which is a synthetic resin material in the package molding process, for example, epoxy resin. A single-body semiconductor package is completed by forming a package with a package. However, as shown in FIG. 1, the lead frame of the conventional semiconductor package manufactured under high temperature working process conditions through each process has a chip mounting plate 3 provided inside the lead frame as shown in FIG. The bonding area between the surface of the semiconductor chip C bonded to the chip mounting board 3 with the epoxy resin E and the surface of the chip mounting board 3 is increased by widening so that the entire area of the bonding side surface of the chip mounting board 3 can be accommodated. .
【0003】各工程で要求される高温の温度条件で製造
される半導体パッケージは半導体チップCとチップ搭載
板3とが互いに異なる資材で構成されており、リードフ
レームのチップ搭載板3に接着された半導体チップCと
チップ搭載板3との間の熱膨張係数差によって、半導体
チップCによる金属材のチップ搭載板3の熱変形が次第
に深化される。そのため、チップ搭載板3に搭載された
半導体チップCの接着部で相互界面剥離が発生し、チッ
プ搭載板3がひどく変形されて半導体パッケージの動作
機能低下及び製品の品質に莫大な問題点を与えるという
欠点があった。
In the semiconductor package manufactured under the high temperature conditions required in each process, the semiconductor chip C and the chip mounting plate 3 are made of different materials and are bonded to the chip mounting plate 3 of the lead frame. Due to the difference in thermal expansion coefficient between the semiconductor chip C and the chip mounting plate 3, the thermal deformation of the metal chip mounting plate 3 by the semiconductor chip C is gradually deepened. As a result, mutual interface peeling occurs at the bonding portion of the semiconductor chip C mounted on the chip mounting plate 3, and the chip mounting plate 3 is severely deformed, resulting in a deterioration of the operation function of the semiconductor package and a huge problem in product quality. There was a drawback.
【0004】[0004]
【発明が解決しようとする課題】本発明は上記のような
従来の問題点を解決するためのもので、熱変形が激しい
金属材のリードフレーム内部中央に備えられたチップ搭
載板3の面積をなるべく小さく構成して、このチップ搭
載板3をリードフレームのタイバーTに連結されるよう
にすることである。すなわち、熱変形が比較的少ない半
導体チップCを前記チップ搭載板3に搭載した場合、半
導体チップCとの接着面積をより小さくして、半導体パ
ッケージの製造時に各工程で要求される高温の温度条件
下で熱膨張される金属材のリードフレームのチップ搭載
板3がひどく変形するのを防止し、チップ搭載板3に接
着された半導体チップCとの接着部から発生する界面剥
離現象を防止して製品の動作機能を向上させ、製品の品
質を高めるようにしたことを目的とする。
DISCLOSURE OF THE INVENTION The present invention is intended to solve the above-mentioned conventional problems, and the area of the chip mounting plate 3 provided in the center of the inside of the lead frame made of a metal material that is severely thermally deformed is reduced. The structure is made as small as possible so that the chip mounting plate 3 is connected to the tie bar T of the lead frame. That is, when the semiconductor chip C, which is relatively less thermally deformed, is mounted on the chip mounting plate 3, the bonding area with the semiconductor chip C is made smaller, and the high temperature temperature condition required in each process at the time of manufacturing the semiconductor package. It prevents the chip mounting plate 3 of the lead frame made of a metal material that is thermally expanded below from being severely deformed, and prevents the interfacial peeling phenomenon that occurs from the bonding portion with the semiconductor chip C bonded to the chip mounting plate 3. The purpose is to improve the operation function of the product and improve the quality of the product.
【0005】本発明の他の目的は、半導体チップCがエ
ポキシ樹脂Eにより接着されるリードフレームのチップ
搭載板3に熱変形を吸収するように連結部を構成してタ
イバーTに接続することによって、ワイヤーボンディン
グ工程及びパッケージモールディング工程時に高温によ
る熱膨張によって熱変形されるのを減らすことにより半
導体チップCが堅固で安定に接着されるようにすること
にある。
Another object of the present invention is to connect the semiconductor chip C to the tie bar T by forming a connecting portion on the chip mounting plate 3 of the lead frame bonded with the epoxy resin E so as to absorb thermal deformation. The purpose of the present invention is to firmly and stably bond the semiconductor chip C by reducing thermal deformation caused by thermal expansion due to high temperature during the wire bonding process and the package molding process.
【0006】[0006]
【課題を解決するための手段】本発明の半導体パッケー
ジのリードフレーム構造は、周縁部に位置するリード
と、半導体チップが接着されるチップ搭載板と、前記チ
ップ搭載板を支持するタイバーを有する半導体パッケー
ジのリードフレームにおいて、前記チップ搭載板の面積
を前記半導体チップの接着側の面の面積より小さく構成
し、前記タイバーと前記チップ搭載板との間に連結部を
具備したことを特徴とする。また、前記連結部は熱変形
を吸収することができるように所定位置に屈曲構造にし
たことを特徴とする。また、前記連結部には少くとも1
以上の孔を配設したことを特徴とする。
A lead frame structure of a semiconductor package according to the present invention is a semiconductor having leads located at a peripheral portion, a chip mounting plate to which a semiconductor chip is bonded, and a tie bar supporting the chip mounting plate. In the lead frame of the package, the area of the chip mounting plate is smaller than the area of the surface of the semiconductor chip on the bonding side, and a connecting portion is provided between the tie bar and the chip mounting plate. In addition, the connecting portion has a bending structure at a predetermined position so as to absorb thermal deformation. Also, there is at least 1 in the connecting portion.
The above-mentioned holes are provided.
【0007】また、周縁部に位置するリードと、半導体
チップが接着されるチップ搭載板と、前記チップ搭載板
の各角部に連結されたタイバーとを有する半導体パッケ
ージのリードフレームにおいて、前記チップ搭載板を各
タイバー先端に一体に連結させた複数個の支持部材で構
成し、この支持部材を互いに連結する細い緩衝部材を具
備したことを特徴とする。また、前記緩衝部材は各々の
支持部材の間に「コ」状に曲げて互いに連結したことを
特徴とする。また、前記緩衝部材はジグザグ状に曲げて
支持部材の間を連結したことを特徴とする。
Further, in a lead frame of a semiconductor package having a lead located at a peripheral portion, a chip mounting plate to which a semiconductor chip is bonded, and a tie bar connected to each corner of the chip mounting plate, the chip mounting is performed. The plate is composed of a plurality of supporting members integrally connected to the tip of each tie bar, and a thin cushioning member for connecting the supporting members to each other is provided. Further, the buffer member is bent in a "U" shape between the supporting members and connected to each other. Further, the buffer member is bent in a zigzag shape to connect the support members.
【0008】また、前記支持部材の一端を互いに連結し
て「X」状に構成し、前記支持部材の両辺に刻みを設
け、各支持部材の他端部を互いに連結する細い緩衝部材
を具備したことを特徴とする。また、周縁部に位置する
リードと、半導体チップが接着されるチップ搭載板と、
前記チップ搭載板を支持するタイバーを有する半導体パ
ッケージのリードフレームにおいて、前記チップ搭載板
の中央に開孔部を構成し、この開孔部の周辺にチップ搭
載板の接着部を構成することを特徴とする。また、前記
チップ搭載板を上下に分離して二つとして構成したこと
を特徴とする。また、周縁部に位置するリードと、半導
体チップが接着されるチップ搭載板と、前記チップ搭載
板を支持するタイバーを有する半導体パッケージのリー
ドフレームにおいて、前記チップ搭載板に少なくとも1
以上の空間部を構成したことを特徴とする。
Further, the support member is provided with a thin cushioning member which is connected to each other at one end thereof to form an "X" shape, indentations are provided on both sides of the support member, and the other ends of the respective support members are connected to each other. It is characterized by Further, a lead located on the peripheral portion, a chip mounting plate to which the semiconductor chip is bonded,
In a lead frame of a semiconductor package having a tie bar that supports the chip mounting plate, an opening portion is formed in the center of the chip mounting plate, and a bonding portion of the chip mounting plate is formed around the opening portion. And Also, the chip mounting plate is vertically separated to form two parts. Further, in a lead frame of a semiconductor package having a lead located at a peripheral portion, a chip mounting plate to which a semiconductor chip is adhered, and a tie bar supporting the chip mounting plate, at least 1 is mounted on the chip mounting plate.
It is characterized in that the above space portion is configured.
【0009】[0009]
【発明の実施の形態】以下に、添付図面を参照して本発
明を詳細に説明する。図2は本発明により構成された第
1実施例のリードフレーム1のチップ搭載板3の形状を
示す構造図面である。図2の破線で示すように、半導体
チップCはチップ搭載板3を中心としてチップ搭載板3
及びその外部に連結された連結部4の一部にエポキシ樹
脂で接着され搭載される。このように半導体チップCを
搭載したチップ搭載板3は半導体チップCとの接着面積
が半導体チップCの接着側の全面積の内一部だけ接着さ
れるため、高温条件で行われる半導体パッケージの製造
工程中ワイヤーボンディング工程やパッケージモールデ
ィング工程でチップ搭載板3に加わる熱による変形を最
小化することができる。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a structural drawing showing the shape of the chip mounting plate 3 of the lead frame 1 of the first embodiment constructed according to the present invention. As shown by the broken line in FIG. 2, the semiconductor chip C is centered on the chip mounting plate 3
And a part of the connecting portion 4 connected to the outside thereof is mounted by being bonded with an epoxy resin. As described above, since the bonding area of the chip mounting plate 3 on which the semiconductor chip C is mounted to the semiconductor chip C is bonded to only a part of the entire area on the bonding side of the semiconductor chip C, the semiconductor package manufactured under high temperature conditions is manufactured. It is possible to minimize the deformation due to heat applied to the chip mounting plate 3 in the wire bonding process or the package molding process during the process.
【0010】従って、熱変形の少ないすなわち熱膨張係
数の小さい半導体チップCを熱変形の大きいすなわち熱
膨張係数の大きい金属材のリードフレーム1のチップ搭
載板3に搭載しても半導体チップCとの接着面積が相対
的に小さくなって、その間の熱膨張係数差の影響を減ら
すことができるため、チップ搭載板3に搭載された半導
体チップCとチップ搭載板3との間で起きる界面剥離現
象を防止することができる。前記したリードフレーム1
のチップ搭載板3はその平面形状を円形、楕円形、四角
形又は多角形に構成して半導体チップCとの接着面積を
最小化することもできる。
Therefore, even if the semiconductor chip C having a small thermal deformation, that is, a small thermal expansion coefficient is mounted on the chip mounting plate 3 of the lead frame 1 of a metal material having a large thermal deformation, that is, a large thermal expansion coefficient, Since the bonding area becomes relatively small and the influence of the difference in thermal expansion coefficient between them can be reduced, the interface peeling phenomenon that occurs between the semiconductor chip C mounted on the chip mounting plate 3 and the chip mounting plate 3 can be prevented. Can be prevented. Lead frame 1 described above
The chip mounting plate 3 may have a plane shape of a circle, an ellipse, a quadrangle, or a polygon to minimize the adhesion area with the semiconductor chip C.
【0011】また、前記リードフレーム1のタイバーT
1〜T4とチップ搭載板3との間に設けられた連結部4
の幅Wを小さく構成し、連結部4には複数個の孔5を配
設して連結部4に加わる高熱による変形を最小化すると
同時に、チップ搭載板3の熱変形も防止することができ
る。また、チップ搭載板3に接着された半導体チップC
とのチップ搭載板3との間の非接着部の隙間にパッケー
ジモールド工程でパッケージモールドされるモールドコ
ンパウンド材が容易に充填されるようにして狭い隙間か
ら発生するモールドボイド(MOLD VOID)を防
止してチップ搭載板3と半導体チップCとが最高な状態
でパッケージモールドされるようにすることができる。
また、前記連結部4は所定位置で屈曲構造にして熱変形
を吸収し得るようにし、さらに前記連結部4に配設され
た複数個の孔5は円形や多角形に構成しても前記効果が
一層あげられる。
Further, the tie bar T of the lead frame 1
1 to T4 and the connecting portion 4 provided between the chip mounting plate 3
The width W of the chip mounting plate 3 is reduced, and a plurality of holes 5 are provided in the connecting portion 4 to minimize the deformation of the chip mounting plate 3 due to the high heat applied to the connecting portion 4. . In addition, the semiconductor chip C bonded to the chip mounting plate 3
A mold compound material to be package-molded in the package molding process is easily filled in a gap of a non-bonded portion between the chip mounting plate 3 and the chip mounting plate 3 to prevent a mold void (MOLD VOID) generated from a narrow gap. The chip mounting plate 3 and the semiconductor chip C can be package-molded in the best condition.
Further, even if the connecting portion 4 has a bent structure at a predetermined position so as to absorb thermal deformation, and the plurality of holes 5 arranged in the connecting portion 4 are formed in a circular shape or a polygonal shape, the above effect is obtained. Can be raised even more.
【0012】図3乃至図6はそれぞれ本発明により構成
された第2乃至第5実施例であり、そのリードフレーム
1のチップ搭載板3の構造を示す図面である。第2乃至
第5実施例では、タイバーT1〜T4に連結されて半導
体チップCを接着支持するチップ搭載板3の構成を複数
個の支持部材a1〜a10で構成し、これらの支持部材
a1〜a10を細い緩衝部材b1〜b9で互いに連結し
て熱的ストレスの吸収緩衝が行われるようにしたもので
ある。図3は第2実施例の基本構成図を示す図面であ
り、図に示すようにチップ搭載板3の支持部a1〜a4
はそれぞれタイバーT1〜T4を一端に一体に連結され
る。これらの支持部材a1〜a4の他端は細い緩衝部材
b1〜b4で互いに連結することにより各支持部材a1
〜a4の間には比較的大きい空間部S1〜S4が形成さ
れると共に、上記支持部材a1〜a4を連結する緩衝部
材b1〜b4によりチップ搭載板3の中央部位にも空間
部S5が形成される。
FIGS. 3 to 6 are drawings showing the structure of the chip mounting plate 3 of the lead frame 1 according to the second to fifth embodiments of the present invention, respectively. In the second to fifth embodiments, the chip mounting plate 3 that is connected to the tie bars T1 to T4 and adheres and supports the semiconductor chip C is composed of a plurality of supporting members a1 to a10. Are connected to each other by thin cushioning members b1 to b9 to absorb and absorb thermal stress. FIG. 3 is a diagram showing the basic configuration of the second embodiment. As shown in the drawing, the supporting portions a1 to a4 of the chip mounting plate 3 are shown.
Have tie bars T1 to T4 integrally connected at one end. The other ends of the supporting members a1 to a4 are connected to each other by thin buffering members b1 to b4, so that the supporting members a1 to
Spaces S1 to S4 are formed between a to a4, and a space S5 is formed in the central portion of the chip mounting plate 3 by the buffer members b1 to b4 connecting the supporting members a1 to a4. It
【0013】また、この第2実施例のチップ搭載板3の
構成はそれぞれのタイバーT1〜T4先端に連結構成さ
れた支持部材a1〜a4を細い緩衝部材b1〜b4で互
いに連結させるが、これに対して図4の第3実施例では
緩衝部材b1〜b4はさらにそれぞれ「コ」字状に曲げ
て連結することにより支持部材a1〜a4に伝達される
熱的ストレスを前記「コ」字状緩衝部材b1〜b4で全
て吸収するためチップ搭載板3全体の熱変形を防ぐこと
ができる。また、図5の第4実施例では、タイバーT1
〜T4と連結されるチップ搭載板3を2つの支持部材a
5,a6で構成し、これらの支持部材a5,a6をジグ
ザグ状に曲げて形成された細い緩衝部材b5で連結構成
してもチップ搭載板3に及ぶ熱的ストレスを吸収緩衝す
ることができる。
Further, in the structure of the chip mounting plate 3 of the second embodiment, the support members a1 to a4 connected to the tips of the tie bars T1 to T4 are connected to each other by the thin buffer members b1 to b4. On the other hand, in the third embodiment of FIG. 4, the cushioning members b1 to b4 are further bent and connected in a "U" shape so that the thermal stress transmitted to the support members a1 to a4 is buffered. Since all of the members b1 to b4 are absorbed, thermal deformation of the entire chip mounting plate 3 can be prevented. Further, in the fourth embodiment of FIG. 5, the tie bar T1
To the chip mounting plate 3 connected to T4, the two supporting members a
5, a6 and the supporting members a5, a6 are connected by a thin buffer member b5 formed by bending the supporting members a5, a6 in a zigzag manner, the thermal stress exerted on the chip mounting plate 3 can be absorbed and buffered.
【0014】さらに、また図6の第5実施例は、それぞ
れのタイバーT1〜T4先端に支持部材a7〜a10の
一端をそれぞれ連結し、該支持部材a7〜a10の他端
を「X」字状に中心で互いに連結するが、上記「X」字
状の支持部材a7〜a10の両側に刻みを備えた構成と
し、それぞれの支持部材a7〜a10の前記一端を細い
緩衝部材b6〜b9で連結させ半導体チップCとチップ
搭載板3との接触面積を最小化することができ、半導体
パッケージのモールド成形時にモールドコンパウンドと
の結合力を増加させチップ搭載板の熱変形によりパッケ
ージモールドコンパウンドとの界面剥離現象やクラック
現象を事前予防することができる。
Further, in the fifth embodiment of FIG. 6, one end of each of the supporting members a7 to a10 is connected to the tip of each tie bar T1 to T4, and the other end of each of the supporting members a7 to a10 is "X" shaped. Are connected to each other at the center, but the above-mentioned "X" -shaped support members a7 to a10 are provided with notches on both sides, and the one ends of the respective support members a7 to a10 are connected by thin buffer members b6 to b9. The contact area between the semiconductor chip C and the chip mounting plate 3 can be minimized, the coupling force with the mold compound is increased during the molding of the semiconductor package, and the interface peeling phenomenon between the chip mounting plate and the package molding compound is caused by the thermal deformation of the chip mounting plate. The crack phenomenon can be prevented in advance.
【0015】図7及び図8はそれぞれ本発明により構成
された第6,第7実施例であり、そのリードフレーム1
のチップ搭載板3の構成を示す図面である。図7は本発
明の第6実施例に関し、リードフレーム1の中央に正方
形或は長方形の四角形状の孔、すなわち開孔部を設けた
チップ搭載板3を示す。そのチップ搭載板3は左右両側
上下に配設された複数個のタイバーT1〜T4により前
記リードフレーム1に一体に構成される。すなわち、チ
ップ搭載板3の中央部に正方形或は長方形の四角形の開
孔部6が構成され、この開孔部6の周辺上面をチップ搭
載板3の接着部7にしてここにエポキシ樹脂を塗布して
半導体チップCを接着した後、半導体チップCに備えら
れたチップパッドと各リード8とをワイヤーで連結接続
する。
7 and 8 show the sixth and seventh embodiments of the present invention, respectively, and the lead frame 1 thereof.
3 is a drawing showing the configuration of the chip mounting plate 3 of FIG. FIG. 7 relates to a sixth embodiment of the present invention and shows a chip mounting plate 3 in which a square or rectangular quadrangular hole, that is, an opening portion is provided in the center of a lead frame 1. The chip mounting plate 3 is integrally formed with the lead frame 1 by a plurality of tie bars T1 to T4 arranged on both left and right sides. That is, a square or rectangular quadrangular opening 6 is formed in the central portion of the chip mounting plate 3, and the peripheral upper surface of the opening 6 is used as an adhesive portion 7 of the chip mounting plate 3 and epoxy resin is applied thereto. Then, after the semiconductor chip C is bonded, the chip pads provided on the semiconductor chip C and the leads 8 are connected and connected by wires.
【0016】このように、ワイヤーで半導体チップCと
各リードセ8とを連結接続する半導体パッケージの製造
工程をワイヤーボンディング工程と呼び、ワイヤーボン
ディング時に加わる高温(200℃〜240℃)により
半導体チップCとチップ搭載板3とは互いに異なる熱膨
張変形が発生する。この際、半導体チップCとチップ搭
載板3との接着部7での熱膨張差による変形をチップ搭
載板3の中央部に形成された開孔部6により減少させ
る。即ち、上記開孔部6の面積が大きいほどチップ搭載
板3の面積が縮小されることにより接着部7の接着面積
が少なくなって熱膨張差による変形を最大限防止するも
のである。
The manufacturing process of the semiconductor package in which the semiconductor chip C and each lead 8 are connected and connected by the wire as described above is called a wire bonding process, and the semiconductor chip C is connected to the semiconductor chip C due to the high temperature (200 ° C. to 240 ° C.) applied during wire bonding. Thermal expansion deformation different from that of the chip mounting plate 3 occurs. At this time, the deformation due to the difference in thermal expansion in the bonding portion 7 between the semiconductor chip C and the chip mounting plate 3 is reduced by the opening 6 formed in the central portion of the chip mounting plate 3. That is, as the area of the opening 6 is larger, the area of the chip mounting plate 3 is reduced, so that the bonding area of the bonding portion 7 is reduced and deformation due to the difference in thermal expansion is prevented to the maximum extent.
【0017】また、チップ搭載板3の接着部7上に搭載
された半導体チップCに備えられたチップパッドと各リ
ード8とをワイヤーで連結するワイヤーボンディング作
業後、半導体チップCの外的な力と腐食と熱等により損
傷を防止すると共に電気的特性と機械的特性の安定性を
寄与するために高温(175℃)で加熱させた半導体パ
ッケージの半製品に合成樹脂材のコンパウンドモールド
材、例えばエポキシ樹脂などを注入させ一定の大きさの
パッケージを有するようにモールディング工程を行えば
モールディング工程時に加わる高温により半導体チップ
Cとチップ搭載板3とは再び熱膨張することになる。こ
の際、前述したチップ搭載板3の中央に構成された開孔
部6により接着部7の面積が縮小されていることによっ
てチップ搭載板3と半導体チップCとの接着部の変形を
防止してその接着状態を堅固にしたものとなる。このよ
うなチップ搭載板3の他の実施例として図8に第7実施
例を示す。添付の図8に示すようにチップ搭載板3を上
下に分離して半導体チップCとの接着面積をより縮小し
てその接着状態をより堅固にすることでワイヤーボンデ
ィング工程とパッケージモールディング工程時に加わる
高温によるチップ搭載板3の変形を最大限防止したもの
である。
After the wire bonding work for connecting the leads 8 and the chip pads provided on the semiconductor chip C mounted on the bonding portion 7 of the chip mounting plate 3 with wires, the external force of the semiconductor chip C is applied. In order to prevent damage due to corrosion and heat, and to contribute to the stability of electrical and mechanical properties, semi-finished products of semiconductor packages heated at high temperature (175 ° C.) are compound mold materials of synthetic resin materials, for example, If a molding process is performed by injecting an epoxy resin or the like so as to have a package of a certain size, the semiconductor chip C and the chip mounting plate 3 will be thermally expanded again due to the high temperature applied during the molding process. At this time, since the area of the adhesive portion 7 is reduced by the opening 6 formed in the center of the chip mounting plate 3 described above, deformation of the adhesive portion between the chip mounting plate 3 and the semiconductor chip C is prevented. The adhered state will be solid. FIG. 8 shows a seventh embodiment as another embodiment of such a chip mounting plate 3. As shown in FIG. 8 attached, by separating the chip mounting plate 3 into upper and lower parts to further reduce the bonding area with the semiconductor chip C and make the bonding state more firm, the high temperature applied during the wire bonding process and the package molding process. The chip mounting plate 3 is prevented from being deformed to a maximum extent.
【0018】図9,図10はそれぞれ本発明により構成
された第8,第9実施例であり、そのリードフレーム1
のチップ搭載板3の形状を示す図面である。図9は本発
明の第8実施例であり、半導体チップCが接着された半
導体パッケージリードフレーム1のチップ搭載板3の構
造であり、リードフレーム1の上下部にタイバーTを形
成してチップ搭載板3を支持し、このチップ搭載板3の
左右両側に一定部分を除去して互いに対向する空間部1
1を構成するため、チップ搭載板3の面積を縮小して半
導体チップCとチップ搭載板3との接着面積を最小化し
た状態を示す図面である。上記チップ搭載板3の左右両
側に互いに対向するよわうに形成された空間部11の形
状は円形或は三角形にしてもよい。
FIGS. 9 and 10 show an eighth and a ninth embodiments, respectively, constructed according to the present invention, and a lead frame 1 thereof.
3 is a view showing the shape of the chip mounting plate 3 of FIG. FIG. 9 shows an eighth embodiment of the present invention, which is a structure of a chip mounting plate 3 of a semiconductor package lead frame 1 to which a semiconductor chip C is adhered, and a tie bar T is formed on the upper and lower parts of the lead frame 1 to mount the chip. A space portion 1 that supports the plate 3 and removes certain parts on the left and right sides of the chip mounting plate 3 to face each other.
2 is a view showing a state in which the area of the chip mounting plate 3 is reduced to configure the No. 1 and the bonding area between the semiconductor chip C and the chip mounting plate 3 is minimized. The shape of the space portions 11 formed so as to face each other on the left and right sides of the chip mounting plate 3 may be circular or triangular.
【0019】図10は本発明の第9実施例を示すもので
あり、そのリードフレーム1のチップ搭載板3に関し、
半導体チップCとチップ搭載板3との接着面積を縮小す
るためにチップ搭載板3の表面に単数個または複数個の
空間部10を有するように構成した。このような空間部
10は長方形にすることもでき、三角形、円形、或はそ
の他の形状に形成することもできる。
FIG. 10 shows a ninth embodiment of the present invention, which relates to the chip mounting plate 3 of the lead frame 1,
In order to reduce the bonding area between the semiconductor chip C and the chip mounting plate 3, the surface of the chip mounting plate 3 has a single or a plurality of spaces 10. The space 10 may have a rectangular shape, a triangular shape, a circular shape, or another shape.
【0020】[0020]
【発明の効果】以上の説明のように、本発明の半導体パ
ーッケージリードフレームのチップ搭載板構造によれ
ば、熱膨張によるチップ搭載板の熱変形を減少させるた
めに半導体チップと接着されるチップ搭載板の体積をよ
り小さくして半導体チップとチップ搭載板とが堅固に付
着状態を維持することでチップ搭載板と半導体チップと
の間の界面剥離を防止し、パッケージの信頼性を向上す
ることができる等の効果がある。
As described above, according to the chip mounting plate structure of the semiconductor package lead frame of the present invention, the chip mounting bonded to the semiconductor chip in order to reduce the thermal deformation of the chip mounting plate due to the thermal expansion. By reducing the volume of the plate and keeping the semiconductor chip and the chip mounting plate firmly adhered to each other, it is possible to prevent interface separation between the chip mounting plate and the semiconductor chip and improve the package reliability. There are effects such as being able to.
【図面の簡単な説明】[Brief description of drawings]
【図1】従来技術が使用する半導体パッケージのリード
フレームのチップ搭載板と半導体チップとの関係を示す
図である。
FIG. 1 is a diagram showing a relationship between a chip mounting plate of a lead frame of a semiconductor package used in a conventional technique and a semiconductor chip.
【図2】本発明による構成された第1実施例の半導体パ
ッケージのリードフレームを示す図面である。
FIG. 2 is a view showing a lead frame of a semiconductor package of a first embodiment constructed according to the present invention.
【図3】本発明により構成された第2実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 3 is a view showing a lead frame chip mounting plate of a semiconductor package of a second embodiment constructed according to the present invention.
【図4】本発明により構成された第3実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 4 is a view showing a lead frame chip mounting plate of a semiconductor package of a third embodiment constructed according to the present invention.
【図5】本発明により構成された第4実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 5 is a view showing a lead frame chip mounting plate of a semiconductor package of a fourth embodiment constructed according to the present invention.
【図6】本発明により構成された第5実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 6 is a view showing a lead frame chip mounting plate of a semiconductor package of a fifth embodiment constructed according to the present invention.
【図7】本発明により構成された第6実施例の半導体パ
ッケージのリードフレームを示す図面である。
FIG. 7 is a drawing showing a lead frame of a semiconductor package according to a sixth exemplary embodiment of the present invention.
【図8】本発明により構成された第7実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 8 is a view showing a lead frame chip mounting plate of a semiconductor package of a seventh embodiment constructed according to the present invention.
【図9】本発明により構成された第8実施例の半導体パ
ッケージのリードフレームチップ搭載板を示す図面であ
る。
FIG. 9 is a view showing a lead frame chip mounting plate of a semiconductor package of an eighth embodiment constructed according to the present invention.
【図10】 本発明により構成された第9実施例の半導
体パッケージのリードフレームチップ搭載板を示す図面
である。
FIG. 10 is a view showing a lead frame chip mounting plate of a semiconductor package of a ninth embodiment constructed according to the present invention.
【符号の説明】[Explanation of symbols]
1 リードフレーム 3 チップ搭載板 4 連結部材 5 孔 6 開孔部 7 接着部 8 リード 10,11 空間部 a1〜a10 支持部材 b1〜b9 緩衝部材 C 半導体チップ E エポキシ樹脂 S1〜S5 空間部 T,T1〜T4 タイバー DESCRIPTION OF SYMBOLS 1 Lead frame 3 Chip mounting plate 4 Connecting member 5 Hole 6 Opening part 7 Adhesive part 8 Leads 10, 11 Space part a1-a10 Supporting member b1-b9 Buffer member C Semiconductor chip E Epoxy resin S1-S5 Space part T, T1 ~ T4 tie bar
───────────────────────────────────────────────────── フロントページの続き (72)発明者 パク トゥ ヒョン 大韓民国ソウル特別市ヨーントゥンポク− トリム1トン76−19 (72)発明者 ハン イン キュ 大韓民国ソウル特別市ソントンクーソンス ウトン1カ276−14 (72)発明者 ユー ヨン チョル 大韓民国ソウル特別市ソントンクーモチン トン199−112 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Pak To Hyun Seoul Special City, Republic of Korea Yoon Tung Bok-Trim 1 ton 76-19 (72) Inventor Han Yin Kyu Song Tong Kwong Soo Won 1 Car 276-14 (72) ) Inventor Yu Yong Chul Song Tong Kumok Ching Tong 199-112 Seoul, Republic of Korea

Claims (10)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 周縁部に位置するリードと、半導体チッ
    プが接着されるチップ搭載板と、前記チップ搭載板を支
    持するタイバーを有する半導体パッケージのリードフレ
    ームにおいて、 前記チップ搭載板の面積を前記半導体チップの接着側の
    面の面積より小さく構成し、前記タイバーと前記チップ
    搭載板との間に連結部を具備したことを特徴とする半導
    体パッケージのリードフレーム構造。
    1. A lead frame of a semiconductor package having a lead located at a peripheral portion, a chip mounting plate to which a semiconductor chip is bonded, and a tie bar supporting the chip mounting plate, wherein an area of the chip mounting plate is set to the semiconductor. A lead frame structure for a semiconductor package, which is formed to have a smaller area than the surface of the chip on the bonding side, and is provided with a connecting portion between the tie bar and the chip mounting plate.
  2. 【請求項2】 前記連結部は熱変形を吸収することがで
    きるように所定位置に屈曲構造にしたことを特徴とする
    請求項1記載の半導体パッケージのリードフレーム構
    造。
    2. The lead frame structure for a semiconductor package according to claim 1, wherein the connecting portion has a bent structure at a predetermined position so as to absorb thermal deformation.
  3. 【請求項3】 前記連結部には少くとも1以上の孔を配
    設したことを特徴とする請求項1または2記載の半導体
    パッケージのリードフレーム構造。
    3. The lead frame structure for a semiconductor package according to claim 1, wherein at least one hole is provided in the connecting portion.
  4. 【請求項4】 周縁部に位置するリードと、半導体チッ
    プが接着されるチップ搭載板と、前記チップ搭載板の各
    角部に連結されたタイバーとを有する半導体パッケージ
    のリードフレームにおいて、 前記チップ搭載板を各タイバー先端に一体に連結させた
    複数個の支持部材で構成し、この支持部材を互いに連結
    する細い緩衝部材を具備したことを特徴とする半導体パ
    ッケージのリードフレーム構造。
    4. A lead frame of a semiconductor package, comprising: a lead located at a peripheral portion; a chip mounting plate to which a semiconductor chip is bonded; and a tie bar connected to each corner of the chip mounting plate. A lead frame structure for a semiconductor package, comprising a plurality of supporting members integrally connected to the tip of each tie bar, and a thin buffer member connecting the supporting members to each other.
  5. 【請求項5】 前記緩衝部材は各々の支持部材の間に
    「コ」状に曲げて互いに連結したことを特徴とする請求
    項4記載の半導体パッケージのリードフレーム構造。
    5. The lead frame structure of a semiconductor package as claimed in claim 4, wherein the buffer member is bent into a "U" shape between the supporting members and connected to each other.
  6. 【請求項6】 前記緩衝部材はジグザグ状に曲げて支持
    部材の間を連結したことを特徴とする請求項4記載の半
    導体パッケージのリードフレーム構造。
    6. The lead frame structure of a semiconductor package according to claim 4, wherein the buffer member is bent in a zigzag shape to connect the support members.
  7. 【請求項7】 前記支持部材の一端を互いに連結して
    「X」状に構成し、前記支持部材の両辺に刻みを設け、
    各支持部材の他端部を互いに連結する細い緩衝部材を具
    備したことを特徴とする請求項4記載の半導体パッケー
    ジのリードフレーム構造。
    7. One end of the support member is connected to each other to form an “X” shape, and notches are provided on both sides of the support member,
    The lead frame structure for a semiconductor package according to claim 4, further comprising a thin buffer member that connects the other ends of the respective support members to each other.
  8. 【請求項8】 周縁部に位置するリードと、半導体チッ
    プが接着されるチップ搭載板と、前記チップ搭載板を支
    持するタイバーを有する半導体パッケージのリードフレ
    ームにおいて、 前記チップ搭載板の中央に開孔部を構成し、この開孔部
    の周辺にチップ搭載板の接着部を構成することを特徴と
    する半導体パッケージのリードフレーム構造。
    8. A lead frame of a semiconductor package having a lead located at a peripheral portion, a chip mounting plate to which a semiconductor chip is bonded, and a tie bar supporting the chip mounting plate, wherein an opening is provided in the center of the chip mounting plate. A lead frame structure of a semiconductor package, characterized in that a chip mounting plate is bonded to the periphery of the opening.
  9. 【請求項9】 前記チップ搭載板を上下に分離して二つ
    として構成したことを特徴とする請求項8記載の半導体
    パッケージのリードフレーム構造。
    9. The lead frame structure of a semiconductor package according to claim 8, wherein the chip mounting plate is vertically separated into two parts.
  10. 【請求項10】 周縁部に位置するリードと、半導体チ
    ップが接着されるチップ搭載板と、前記チップ搭載板を
    支持するタイバーを有する半導体パッケージのリードフ
    レームにおいて、 前記チップ搭載板に少なくとも1以上の空間部を構成し
    たことを特徴とする半導体パッケージのリードフレーム
    構造。
    10. A lead frame of a semiconductor package having a lead located at a peripheral portion, a chip mounting plate to which a semiconductor chip is bonded, and a tie bar supporting the chip mounting plate, wherein at least one or more chip mounting plates are provided. A lead frame structure for a semiconductor package, characterized in that a space portion is formed.
JP7345711A 1994-12-14 1995-12-08 Lead frame structure of semiconductor package Expired - Fee Related JP2767404B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR2019940033994U KR200143924Y1 (en) 1994-12-14 1994-12-14 Pad structure of leadframe
KR1019940037168A KR100201062B1 (en) 1994-12-27 1994-12-27 Leadframe die structure of semiconductor package
KR1994U33994 1994-12-27
KR1994P37168 1994-12-27

Publications (2)

Publication Number Publication Date
JPH08236685A true JPH08236685A (en) 1996-09-13
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JP2010109234A (en) * 2008-10-31 2010-05-13 Renesas Technology Corp Semiconductor device

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US5661338A (en) 1997-08-26

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