JPH08236684A - Manufacture of lead frame and semiconductor employing it - Google Patents

Manufacture of lead frame and semiconductor employing it

Info

Publication number
JPH08236684A
JPH08236684A JP11623795A JP11623795A JPH08236684A JP H08236684 A JPH08236684 A JP H08236684A JP 11623795 A JP11623795 A JP 11623795A JP 11623795 A JP11623795 A JP 11623795A JP H08236684 A JPH08236684 A JP H08236684A
Authority
JP
Japan
Prior art keywords
pad
hole
chip
tape
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11623795A
Other languages
Japanese (ja)
Other versions
JP3069629B2 (en
Inventor
Saburo Tanabe
三郎 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP11623795A priority Critical patent/JP3069629B2/en
Publication of JPH08236684A publication Critical patent/JPH08236684A/en
Application granted granted Critical
Publication of JP3069629B2 publication Critical patent/JP3069629B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE: To eliminate the gap by previously applying a thermoplastic tape to a pad and punching the thermoplastic tape and the pad simultaneously thereby ensuring the positional accuracy between the tape for bonding an IC chip and a pad through hole. CONSTITUTION: A thermoplastic tape 3 and a pad are punched simultaneously such that a predetermined shape is obtained without limiting to one direction on the surface and rear thus preventing the positional shift between a through hole 4 of the thermoplastic tape 3 and a through hole 2 of the pad 1. Consequently, peel off of an IC chip and cracking of package can be prevented. Furthermore, sealing material is fed through the through hole 2 of the pad 1 at the time of packaging thus bonding the pad 1 and the IC chip 5 rigidly. With such structure, sufficient durability can be held even when the pad 1 is subjected to thermal stress.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、所定の貫通孔を有する
半導体チップ搭載部を備えたリードフレームの製造方法
と、これを用いた半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a lead frame having a semiconductor chip mounting portion having a predetermined through hole, and a semiconductor device using the same.

【0002】[0002]

【従来の技術】通常、半導体装置(IC)は、リードフ
レームのICチップ搭載部(以下 パッドという)にI
Cチップを固着搭載し、ICチップの各電極と対応する
インナーリード部とをボンディングワイヤーにより接続
させて樹脂またはセラミック等の封止材料によってイン
ナーリード以内をパッケージングし、当該パッケージか
ら突出するアウターリードを所望の形状に成形して製造
される。
2. Description of the Related Art Generally, a semiconductor device (IC) is mounted on an IC chip mounting portion (hereinafter referred to as a pad) of a lead frame.
The C chip is fixedly mounted, each electrode of the IC chip and the corresponding inner lead part are connected by a bonding wire, and the inside of the inner lead is packaged with a sealing material such as resin or ceramic, and the outer lead protruding from the package. Is molded into a desired shape.

【0003】しかしながら、上記のような構成の半導体
装置においては、ICチップ、リードフレーム、封止樹
脂など各材質によって熱膨張係数が異なるため、ダイボ
ンディング工程あるいは基板実装時などに加わる熱スト
レスにより、ICチップとパッド、またはパッドと封止
樹脂の各材質界面に剥離を生じさせており、半導体装置
の信頼性を著しく低下させている。
However, in the semiconductor device having the above-mentioned structure, the thermal expansion coefficient is different depending on each material such as the IC chip, the lead frame and the sealing resin, so that the thermal stress applied during the die bonding process or mounting on the substrate causes Peeling occurs at the material interface between the IC chip and the pad, or the pad and the sealing resin, which significantly reduces the reliability of the semiconductor device.

【0004】近年ではICチップメモリーの高集積化に
伴う、ICチップの大型化が進むなか、一方では半導体
パッケージ全体の小型化、薄型化も要求され、上記問題
の発生もより顕著になっている。
[0004] In recent years, as IC chips have become more highly integrated and the size of IC chips has increased, on the other hand, there has been a demand for downsizing and thinning of the entire semiconductor package, and the occurrence of the above problems has become more prominent. .

【0005】係ることから従来では、例えばリードフレ
ームのパッド部に数箇所の貫通孔あるいはスリットを設
けることにより、前記パッドに歪解放性を持たせて熱ス
トレスを緩和させ、ICチップとパッド界面の剥離を防
止する方法が提案されており、前述した問題に対し一定
の作用効果が認められる。
For this reason, conventionally, for example, by providing through holes or slits at several positions in the pad portion of the lead frame, the pad has a strain releasability to relieve thermal stress, and the interface between the IC chip and the pad is reduced. A method for preventing peeling has been proposed, and a certain action and effect are recognized for the above-mentioned problems.

【0006】[0006]

【この発明が解決しようとする課題】ここで、所定の貫
通孔を有するパッドへのICチップの固着に関して、熱
可塑性テープを使用した例を図3に示す。従来、パッド
1の貫通孔2および熱可塑性テープ3の貫通孔4は、そ
れぞれ別々に打ち抜かれた後、前記パッド1の貫通孔2
および熱可塑性テープ3の貫通孔4の孔形状および孔寸
法を同一とするよう位置を合わせ張り付けられていた。
しかし、当該張り付けでは、前記パッド貫通孔2と前記
熱可塑性テープ貫通孔4の正確な位置合わせが困難なた
め、張り付け位置に微妙なズレが生じ、そのままICチ
ップ5を固着した場合、前記ICチップ5と前記パッド
1間に前記パッド貫通孔2と前記熱可塑性テープ貫通孔
4の差異により隙間10を発生させてしまう。この隙間
10は微小な領域であり、パッケージングに係る封止樹
脂注入の際、封止樹脂が隙間10領域に入り込めずに残
留気泡となる。よって加熱加圧時に気泡が膨張してIC
チップの剥離、またはパッケージへのクラックなどを誘
発させる原因となっている。
FIG. 3 shows an example in which a thermoplastic tape is used for fixing an IC chip to a pad having a predetermined through hole. Conventionally, the through hole 2 of the pad 1 and the through hole 4 of the thermoplastic tape 3 are punched separately, and then the through hole 2 of the pad 1 is formed.
Further, the through holes 4 of the thermoplastic tape 3 were aligned and bonded so that the hole shape and the hole size were the same.
However, in the pasting, it is difficult to accurately align the pad through hole 2 and the thermoplastic tape through hole 4 with each other, so that a slight deviation occurs in the pasting position. A gap 10 is generated between the pad 5 and the pad 1 due to the difference between the pad through hole 2 and the thermoplastic tape through hole 4. The gap 10 is a minute region, and when the sealing resin is injected for packaging, the sealing resin cannot enter the region of the gap 10 and becomes a residual bubble. Therefore, air bubbles expand during heating and pressurization and IC
This is a cause of chip peeling or cracking of the package.

【0007】また、他のICチップ固着方法として、ペ
ースト材を用い熱硬化させることによってICチップを
パッドに固着させる方法も提案されているが、ダイボン
ディング工程時の加熱加圧により、ペースト材よりガス
が発生し発泡現象が起き、ICチップがパッドのマウン
ト位置より不規律方向に移動する問題があり好ましくな
い。以上のことからも従来技術では半導体装置の十分な
信頼性が確保できない。本発明では前述してきた問題点
を解消するため、ICチップ固着用のテープとパッド貫
通孔との位置精度を確保でき、前記隙間のないリードフ
レームの製造方法と、これを用いた半導体装置の提供を
目的とする。
As another IC chip fixing method, a method of fixing the IC chip to the pad by thermosetting using a paste material has been proposed. However, the IC chip is fixed to the pad by heat and pressure during the die bonding process. There is a problem that gas is generated and a foaming phenomenon occurs, and the IC chip moves in an irregular direction from the mounting position of the pad, which is not preferable. From the above, the conventional technique cannot ensure sufficient reliability of the semiconductor device. In the present invention, in order to solve the problems described above, it is possible to secure the positional accuracy of the tape for fixing the IC chip and the pad through hole, and to provide a method for manufacturing a lead frame without the above gap, and a semiconductor device using the same. With the goal.

【0008】[0008]

【課題を解決するための手段】上記目的を達成する本発
明の特徴とするところは、先に外径抜きのみを行った熱
可塑性テープ等のテープ状の接着材を、あらかじめパッ
ドに張り付けておき、その後、前記テープ状の接着材と
前記パッドとを同時に打ち抜くことにより、所定の貫通
孔を有するパッド形状を備えたリードフレームの製造方
法と、これを用いた半導体装置にある。
To achieve the above object, the present invention is characterized in that a tape-like adhesive material such as a thermoplastic tape whose outer diameter has been removed is attached to a pad in advance. Then, there is a method of manufacturing a lead frame having a pad shape having a predetermined through hole by simultaneously punching out the tape-shaped adhesive material and the pad, and a semiconductor device using the same.

【0009】[0009]

【作用】本発明は、あらかじめ外径抜きのみを行ったテ
ープ状の接着材をパッドに張り付けた後、同時に打ち抜
きを行うため、パッドの貫通孔寸法とテープの貫通孔寸
法とが正確な同一寸法であり、気泡となる隙間部分の発
生を防止できる。
In the present invention, since the tape-shaped adhesive material, which has only the outer diameter removed in advance, is attached to the pad and punched simultaneously, the pad through-hole size and the tape through-hole size are exactly the same. Therefore, it is possible to prevent the formation of a gap portion that becomes a bubble.

【0010】前記隙間部分の発生を防止できることか
ら、封止樹脂の完全な充填が可能となるため、気泡にか
かるICチップとパッド、パッドと封止樹脂界面におけ
る剥離、パッケージクラック等が発生しない。
Since it is possible to prevent the formation of the gap portion, it is possible to completely fill the sealing resin, and therefore, the IC chip and the pad, the peeling at the interface between the pad and the sealing resin, the package crack, and the like caused by air bubbles do not occur.

【0011】また、パッド貫通孔に入り込んだ封止材料
とパッド、ならびにICチップとの密着性が向上するた
め、パッドの熱ストレスによる変形に対しても強固な状
態を保持することができ、半導体装置の信頼性を大きく
向上させる。
Further, since the adhesiveness between the encapsulating material that has entered the pad through hole, the pad, and the IC chip is improved, it is possible to maintain a strong state against deformation of the pad due to thermal stress. Greatly improves the reliability of the device.

【0012】[0012]

【実施例】以下、本発明の一実施例を図面に基づいて説
明する。図1は本発明に係るリードフレームのパッド部
分拡大図であって、リードフレームの材質は鉄ニッケル
あるいは銅を使用している。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged view of a pad portion of a lead frame according to the present invention. The material of the lead frame is iron nickel or copper.

【0013】1はパッド、2はパッドの貫通孔である
が、本発明は当該貫通孔の所定数および形状に限ること
なく、その個数および形状は任意にできる。該貫通孔は
パッドにかかる応力や熱ストレスを解放する。また、封
止材料との密着性を高める等、有用である。
Although 1 is a pad and 2 is a through hole of the pad, the present invention is not limited to the predetermined number and shape of the through holes, and the number and shape can be arbitrary. The through holes relieve the stress and heat stress applied to the pad. In addition, it is useful, for example, to improve the adhesiveness with the sealing material.

【0014】3は熱可塑性テープあるいは熱硬化性テー
プ等のテープ状の接着材であり、前記熱可塑性、熱硬化
性テープ外径はICチップサイズ端より外側に出す方が
好ましい。
Reference numeral 3 denotes a tape-shaped adhesive such as a thermoplastic tape or a thermosetting tape, and it is preferable that the outer diameter of the thermoplastic or thermosetting tape is outside the end of the IC chip size.

【0015】また、本発明では熱可塑性テープ3と前記
パッド1とを表裏の一方方向に限定することなく、所定
の形状を得るべくして同時に打ち抜くことにより、前記
熱可塑性テープ3の貫通孔4位置と前記パッド1の貫通
孔2位置とにズレを生じることがないため、ICチップ
の剥離、パッケージへのクラック等が発生しない。
Further, in the present invention, the thermoplastic tape 3 and the pad 1 are not limited to one direction of the front and back sides, but are punched at the same time to obtain a predetermined shape, so that the through hole 4 of the thermoplastic tape 3 is formed. Since there is no deviation between the position and the position of the through hole 2 of the pad 1, peeling of the IC chip, cracking of the package, etc. do not occur.

【0016】また、パッケージングの際には、前記パッ
ドの貫通孔2より封止材料が入り込み、前記パッド1お
よび前記ICチップ5とを強固に密着させるため、熱ス
トレスによる前記パッド1への応力発生に対しても十分
な耐久性を保持している。
During packaging, the sealing material enters through the through holes 2 of the pad and firmly adheres the pad 1 and the IC chip 5 to each other, so that the stress applied to the pad 1 due to thermal stress. It has sufficient durability against occurrence.

【0017】図2は本発明に係る半導体装置であって、
前記ICチップ5の回路端子と、パッド1の外周に設け
られた各インナーリード6先端とを、電気導通を目的と
する金属の細線7によって接続されている。8は本発明
に係る半導体装置のパッケージであり、前記ICチップ
5を固着保持した前記パッド1と前記インナーリード6
以内を樹脂あるいはセラミック等の封止材料によりパッ
ケージして、当該パッケージ8より突出したアウターリ
ード9を所望の形状に成形を行ったものである。
FIG. 2 shows a semiconductor device according to the present invention,
The circuit terminal of the IC chip 5 and the tips of the inner leads 6 provided on the outer periphery of the pad 1 are connected by a thin metal wire 7 for the purpose of electrical conduction. Reference numeral 8 denotes a semiconductor device package according to the present invention, which includes the pad 1 on which the IC chip 5 is fixedly held and the inner lead 6
The inside is packaged with a sealing material such as resin or ceramic, and the outer leads 9 protruding from the package 8 are molded into a desired shape.

【0018】[0018]

【発明の効果】以上のように本発明によれば、パッケー
ジ内に係る封止材料の未充填部分の発生を防止すること
により、高密度を得た薄型かつ信頼性の優れた半導体装
置の提供が可能となる。
As described above, according to the present invention, it is possible to provide a thin and highly reliable semiconductor device having a high density by preventing the unfilled portion of the sealing material in the package from being generated. Is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例のリードフレームのパッド部分拡
大斜視図
FIG. 1 is an enlarged perspective view of a pad portion of a lead frame according to an embodiment of the present invention.

【図2】本発明実施例の半導体装置断面図FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図3】従来技術を示す半導体装置断面図FIG. 3 is a sectional view of a semiconductor device showing a conventional technique.

【符号の説明】[Explanation of symbols]

1、パッド 2、パッド孔 3、熱可塑性テープ 4、熱可塑性テープ孔 5、ICチップ 6、インナーリード 7、ボンディングワイヤー 8、パッケージ 9、アウターリード 10、気泡 1, pad 2, pad hole 3, thermoplastic tape 4, thermoplastic tape hole 5, IC chip 6, inner lead 7, bonding wire 8, package 9, outer lead 10, air bubble

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップと半導体チップ搭載部とを
固着させるテープ状の(熱可塑性)接着材を、あらかじ
め前記半導体チップ搭載部に張り付けておき、前記(熱
可塑性)接着材と前記半導体チップ搭載部とを同時に打
ち抜き、所定の貫通孔を有する半導体チップ搭載部を備
えたリードフレームの製造方法。
1. A tape-shaped (thermoplastic) adhesive material for fixing a semiconductor chip and a semiconductor chip mounting portion to the semiconductor chip mounting portion in advance, and the (thermoplastic) adhesive material and the semiconductor chip mounting portion. A method of manufacturing a lead frame including a semiconductor chip mounting portion having a predetermined through hole by punching the same at the same time.
【請求項2】 所定形状の貫通孔が、張り付けられたテ
ープ状の接着材と同時に打ち抜き形成された半導体チッ
プ搭載部に、半導体チップが前記接着材を介して固着搭
載され、該半導体チップと半導体チップ搭載部外周に設
けられたインナーリードとがボンディングワイヤーで接
続され、前記インナーリード以内を封止材料でパッケー
ジした半導体装置。
2. A semiconductor chip mounting portion, in which a through-hole having a predetermined shape is punched and formed simultaneously with a tape-shaped adhesive material adhered, the semiconductor chip is fixedly mounted via the adhesive material, and the semiconductor chip and the semiconductor are mounted. A semiconductor device in which an inner lead provided on the outer periphery of a chip mounting portion is connected by a bonding wire, and the inside of the inner lead is packaged with a sealing material.
JP11623795A 1995-02-24 1995-02-24 Lead frame manufacturing method and semiconductor device using the same Expired - Fee Related JP3069629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11623795A JP3069629B2 (en) 1995-02-24 1995-02-24 Lead frame manufacturing method and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11623795A JP3069629B2 (en) 1995-02-24 1995-02-24 Lead frame manufacturing method and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JPH08236684A true JPH08236684A (en) 1996-09-13
JP3069629B2 JP3069629B2 (en) 2000-07-24

Family

ID=14682210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11623795A Expired - Fee Related JP3069629B2 (en) 1995-02-24 1995-02-24 Lead frame manufacturing method and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP3069629B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260367A (en) * 2009-06-29 2009-11-05 Renesas Technology Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260367A (en) * 2009-06-29 2009-11-05 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JP3069629B2 (en) 2000-07-24

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