JP3069629B2 - Lead frame manufacturing method and semiconductor device using the same - Google Patents
Lead frame manufacturing method and semiconductor device using the sameInfo
- Publication number
- JP3069629B2 JP3069629B2 JP11623795A JP11623795A JP3069629B2 JP 3069629 B2 JP3069629 B2 JP 3069629B2 JP 11623795 A JP11623795 A JP 11623795A JP 11623795 A JP11623795 A JP 11623795A JP 3069629 B2 JP3069629 B2 JP 3069629B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- hole
- semiconductor device
- chip
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は、所定の貫通孔を有する
半導体チップ搭載部を備えたリードフレームの製造方法
と、これを用いた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lead frame having a semiconductor chip mounting portion having a predetermined through hole, and a semiconductor device using the same.
【０００２】[0002]
【従来の技術】通常、半導体装置（ＩＣ）は、リードフ
レームのＩＣチップ搭載部（以下 パッドという）にＩ
Ｃチップを固着搭載し、ＩＣチップの各電極と対応する
インナーリード部とをボンディングワイヤーにより接続
させて樹脂またはセラミック等の封止材料によってイン
ナーリード以内をパッケージングし、当該パッケージか
ら突出するアウターリードを所望の形状に成形して製造
される。2. Description of the Related Art Normally, a semiconductor device (IC) is mounted on an IC chip mounting portion (hereinafter referred to as a pad) of a lead frame.
A C chip is fixedly mounted, each electrode of the IC chip is connected to the corresponding inner lead portion by a bonding wire, and the inner lead is packaged with a sealing material such as resin or ceramic, and the outer lead protruding from the package. Is formed into a desired shape.
【０００３】しかしながら、上記のような構成の半導体
装置においては、ＩＣチップ、リードフレーム、封止樹
脂など各材質によって熱膨張係数が異なるため、ダイボ
ンディング工程あるいは基板実装時などに加わる熱スト
レスにより、ＩＣチップとパッド、またはパッドと封止
樹脂の各材質界面に剥離を生じさせており、半導体装置
の信頼性を著しく低下させている。However, in the semiconductor device having the above-described structure, the thermal expansion coefficient differs depending on each material such as an IC chip, a lead frame, and a sealing resin. Peeling occurs at each material interface between the IC chip and the pad or between the pad and the sealing resin, which significantly reduces the reliability of the semiconductor device.
【０００４】近年ではＩＣチップメモリーの高集積化に
伴う、ＩＣチップの大型化が進むなか、一方では半導体
パッケージ全体の小型化、薄型化も要求され、上記問題
の発生もより顕著になっている。[0004] In recent years, as the size of IC chips has increased with the increase in the degree of integration of IC chip memories, on the other hand, the size and thickness of the entire semiconductor package have also been required, and the above-mentioned problems have become more noticeable. .
【０００５】係ることから従来では、例えばリードフレ
ームのパッド部に数箇所の貫通孔あるいはスリットを設
けることにより、前記パッドに歪解放性を持たせて熱ス
トレスを緩和させ、ＩＣチップとパッド界面の剥離を防
止する方法が提案されており、前述した問題に対し一定
の作用効果が認められる。For this reason, conventionally, for example, by providing several through holes or slits in a pad portion of a lead frame, the pad is provided with a strain releasing property to relieve thermal stress, and an interface between the IC chip and the pad is provided. A method for preventing peeling has been proposed, and a certain effect is recognized for the above-mentioned problem.
【０００６】[0006]
【この発明が解決しようとする課題】ここで、所定の貫
通孔を有するパッドへのＩＣチップの固着に関して、熱
可塑性テープを使用した例を図３に示す。従来、パッド
１の貫通孔２および熱可塑性テープ３の貫通孔４は、そ
れぞれ別々に打ち抜かれた後、前記パッド１の貫通孔２
および熱可塑性テープ３の貫通孔４の孔形状および孔寸
法を同一とするよう位置を合わせ張り付けられていた。
しかし、当該張り付けでは、前記パッド貫通孔２と前記
熱可塑性テープ貫通孔４の正確な位置合わせが困難なた
め、張り付け位置に微妙なズレが生じ、そのままＩＣチ
ップ５を固着した場合、前記ＩＣチップ５と前記パッド
１間に前記パッド貫通孔２と前記熱可塑性テープ貫通孔
４の差異により隙間１０を発生させてしまう。この隙間
１０は微小な領域であり、パッケージングに係る封止樹
脂注入の際、封止樹脂が隙間１０領域に入り込めずに残
留気泡となる。よって加熱加圧時に気泡が膨張してＩＣ
チップの剥離、またはパッケージへのクラックなどを誘
発させる原因となっている。FIG. 3 shows an example in which a thermoplastic tape is used for fixing an IC chip to a pad having a predetermined through hole. Conventionally, the through-hole 2 of the pad 1 and the through-hole 4 of the thermoplastic tape 3 are punched separately,
In addition, the holes were aligned and adhered so that the hole shape and hole size of the through holes 4 of the thermoplastic tape 3 were the same.
However, it is difficult to accurately align the pad through-hole 2 and the thermoplastic tape through-hole 4 with the pasting, so that a slight displacement occurs in the pasting position. A gap 10 is generated between the pad 5 and the pad 1 due to the difference between the pad through hole 2 and the thermoplastic tape through hole 4. The gap 10 is a minute area, and when the sealing resin is injected for packaging, the sealing resin cannot enter the gap 10 area and becomes a residual bubble. Therefore, the bubbles expand when heated and pressurized and IC
This causes chip peeling or cracks in the package.
【０００７】また、他のＩＣチップ固着方法として、ペ
ースト材を用い熱硬化させることによってＩＣチップを
パッドに固着させる方法も提案されているが、ダイボン
ディング工程時の加熱加圧により、ペースト材よりガス
が発生し発泡現象が起き、ＩＣチップがパッドのマウン
ト位置より不規律方向に移動する問題があり好ましくな
い。以上のことからも従来技術では半導体装置の十分な
信頼性が確保できない。本発明では前述してきた問題点
を解消するため、ＩＣチップ固着用のテープとパッド貫
通孔との位置精度を確保でき、前記隙間のないリードフ
レームの製造方法と、これを用いた半導体装置の提供を
目的とする。As another IC chip fixing method, a method of fixing an IC chip to a pad by thermosetting using a paste material has also been proposed. Gas is generated and a foaming phenomenon occurs, and there is a problem that the IC chip moves in an irregular direction from the mounting position of the pad, which is not preferable. From the above, sufficient reliability of the semiconductor device cannot be ensured by the conventional technology. In the present invention, in order to solve the above-mentioned problems, it is possible to secure the positional accuracy between the IC chip fixing tape and the pad through-hole, and to provide a method for manufacturing a lead frame having no gap and a semiconductor device using the same. With the goal.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成する本発
明の特徴とするところは、先に外径抜きのみを行った熱
可塑性テープ等のテープ状の接着材を、あらかじめパッ
ドに張り付けておき、その後、前記テープ状の接着材と
前記パッドとを同時に打ち抜くことにより、所定の貫通
孔を有するパッド形状を備えたリードフレームの製造方
法と、これを用いた半導体装置にある。A feature of the present invention that achieves the above object is that a tape-like adhesive material such as a thermoplastic tape whose outer diameter has been previously removed only is previously attached to a pad. Then, a method of manufacturing a lead frame having a pad shape having a predetermined through hole by simultaneously punching out the tape-shaped adhesive and the pad, and a semiconductor device using the same.
【０００９】[0009]
【作用】本発明は、あらかじめ外径抜きのみを行ったテ
ープ状の接着材をパッドに張り付けた後、同時に打ち抜
きを行うため、パッドの貫通孔寸法とテープの貫通孔寸
法とが正確な同一寸法であり、気泡となる隙間部分の発
生を防止できる。According to the present invention, since a tape-shaped adhesive material whose only outer diameter has been removed in advance is pasted on the pad and then punched out at the same time, the through-hole dimensions of the pad and the tape are exactly the same. Therefore, the generation of the gap portion which becomes the bubble can be prevented.
【００１０】前記隙間部分の発生を防止できることか
ら、封止樹脂の完全な充填が可能となるため、気泡にか
かるＩＣチップとパッド、パッドと封止樹脂界面におけ
る剥離、パッケージクラック等が発生しない。Since the generation of the gap can be prevented, the sealing resin can be completely filled, so that there is no occurrence of peeling, package cracks, etc. at the interface between the IC chip and the pad, the pad and the sealing resin.
【００１１】また、パッド貫通孔に入り込んだ封止材料
とパッド、ならびにＩＣチップとの密着性が向上するた
め、パッドの熱ストレスによる変形に対しても強固な状
態を保持することができ、半導体装置の信頼性を大きく
向上させる。In addition, since the adhesion between the sealing material and the pad and the IC chip that have entered the through hole of the pad and the IC chip are improved, the pad can be kept strong against deformation due to thermal stress. It greatly improves the reliability of the device.
【００１２】[0012]
【実施例】以下、本発明の一実施例を図面に基づいて説
明する。図１は本発明に係るリードフレームのパッド部
分拡大図であって、リードフレームの材質は鉄ニッケル
あるいは銅を使用している。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged view of a pad portion of a lead frame according to the present invention, and the material of the lead frame is iron nickel or copper.
【００１３】１はパッド、２はパッドの貫通孔である
が、本発明は当該貫通孔の所定数および形状に限ること
なく、その個数および形状は任意にできる。該貫通孔は
パッドにかかる応力や熱ストレスを解放する。また、封
止材料との密着性を高める等、有用である。Reference numeral 1 denotes a pad, and 2 denotes a through hole of the pad. In the present invention, the number and shape of the through hole are not limited to a predetermined number and shape, and the number and shape can be arbitrarily set. The through holes release stress and thermal stress applied to the pad. It is also useful, for example, to enhance the adhesion to the sealing material.
【００１４】３は熱可塑性テープあるいは熱硬化性テー
プ等のテープ状の接着材であり、前記熱可塑性、熱硬化
性テープ外径はＩＣチップサイズ端より外側に出す方が
好ましい。Reference numeral 3 denotes a tape-like adhesive such as a thermoplastic tape or a thermosetting tape, and it is preferable that the outer diameter of the thermoplastic or thermosetting tape be outside the IC chip size end.
【００１５】また、本発明では熱可塑性テープ３と前記
パッド１とを表裏の一方方向に限定することなく、所定
の形状を得るべくして同時に打ち抜くことにより、前記
熱可塑性テープ３の貫通孔４位置と前記パッド１の貫通
孔２位置とにズレを生じることがないため、ＩＣチップ
の剥離、パッケージへのクラック等が発生しない。In the present invention, the thermoplastic tape 3 and the pad 1 are punched out simultaneously to obtain a predetermined shape without being limited to one direction of the front and back, so that the through holes 4 of the thermoplastic tape 3 are formed. Since there is no deviation between the position and the position of the through hole 2 of the pad 1, peeling of the IC chip and cracking of the package do not occur.
【００１６】また、パッケージングの際には、前記パッ
ドの貫通孔２より封止材料が入り込み、前記パッド１お
よび前記ＩＣチップ５とを強固に密着させるため、熱ス
トレスによる前記パッド１への応力発生に対しても十分
な耐久性を保持している。Also, at the time of packaging, a sealing material enters through the through hole 2 of the pad, and the pad 1 and the IC chip 5 are firmly adhered to each other. It has sufficient durability against occurrence.
【００１７】図２は本発明に係る半導体装置であって、
前記ＩＣチップ５の回路端子と、パッド１の外周に設け
られた各インナーリード６先端とを、電気導通を目的と
する金属の細線７によって接続されている。８は本発明
に係る半導体装置のパッケージであり、前記ＩＣチップ
５を固着保持した前記パッド１と前記インナーリード６
以内を樹脂あるいはセラミック等の封止材料によりパッ
ケージして、当該パッケージ８より突出したアウターリ
ード９を所望の形状に成形を行ったものである。FIG. 2 shows a semiconductor device according to the present invention.
The circuit terminals of the IC chip 5 and the tips of the inner leads 6 provided on the outer periphery of the pad 1 are connected by a thin metal wire 7 for electrical conduction. Reference numeral 8 denotes a package of the semiconductor device according to the present invention, wherein the pad 1 holding the IC chip 5 and the inner lead 6 are fixed.
The inside is packaged with a sealing material such as resin or ceramic, and the outer leads 9 protruding from the package 8 are formed into a desired shape.
【００１８】[0018]
【発明の効果】以上のように本発明によれば、パッケー
ジ内に係る封止材料の未充填部分の発生を防止すること
により、高密度を得た薄型かつ信頼性の優れた半導体装
置の提供が可能となる。As described above, according to the present invention, a thin and highly reliable semiconductor device having a high density can be provided by preventing generation of an unfilled portion of a sealing material in a package. Becomes possible.
【図１】本発明実施例のリードフレームのパッド部分拡
大斜視図FIG. 1 is an enlarged perspective view of a pad portion of a lead frame according to an embodiment of the present invention.
【図２】本発明実施例の半導体装置断面図FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図３】従来技術を示す半導体装置断面図FIG. 3 is a sectional view of a semiconductor device showing a conventional technique.
１、パッド ２、パッド孔 ３、熱可塑性テープ ４、熱可塑性テープ孔 ５、ＩＣチップ ６、インナーリード ７、ボンディングワイヤー ８、パッケージ ９、アウターリード １０、気泡 1, pad 2, pad hole 3, thermoplastic tape 4, thermoplastic tape hole 5, IC chip 6, inner lead 7, bonding wire 8, package 9, outer lead 10, air bubble
Claims (2)
固着させるテープ状の（熱可塑性）接着材を、あらかじ
め前記半導体チップ搭載部に張り付けておき、前記（熱
可塑性）接着材と前記半導体チップ搭載部とを同時に打
ち抜き、所定の貫通孔を有する半導体チップ搭載部を備
えたリードフレームの製造方法。1. A tape-shaped (thermoplastic) adhesive material for fixing a semiconductor chip and a semiconductor chip mounting portion is attached to the semiconductor chip mounting portion in advance, and the (thermoplastic) adhesive material and the semiconductor chip mounting portion are attached. And a lead frame provided with a semiconductor chip mounting portion having a predetermined through hole.
ープ状の接着材と同時に打ち抜き形成された半導体チッ
プ搭載部に、半導体チップが前記接着材を介して固着搭
載され、該半導体チップと半導体チップ搭載部外周に設
けられたインナーリードとがボンディングワイヤーで接
続され、前記インナーリード以内を封止材料でパッケー
ジした半導体装置。2. A semiconductor chip is fixedly mounted on a semiconductor chip mounting portion formed by punching out a through hole of a predetermined shape at the same time as a tape-shaped adhesive material adhered thereto, via said adhesive material. A semiconductor device in which an inner lead provided on an outer periphery of a chip mounting portion is connected by a bonding wire, and a portion inside the inner lead is packaged with a sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11623795A JP3069629B2 (en) | 1995-02-24 | 1995-02-24 | Lead frame manufacturing method and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11623795A JP3069629B2 (en) | 1995-02-24 | 1995-02-24 | Lead frame manufacturing method and semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236684A JPH08236684A (en) | 1996-09-13 |
| JP3069629B2 true JP3069629B2 (en) | 2000-07-24 |
Family
ID=14682210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11623795A Expired - Fee Related JP3069629B2 (en) | 1995-02-24 | 1995-02-24 | Lead frame manufacturing method and semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3069629B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5167203B2 (en) * | 2009-06-29 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1995
- 1995-02-24 JP JP11623795A patent/JP3069629B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08236684A (en) | 1996-09-13 |
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