JPH08236260A - Chip-type absorber and manufacture thereof - Google Patents

Chip-type absorber and manufacture thereof

Info

Publication number
JPH08236260A
JPH08236260A JP3860695A JP3860695A JPH08236260A JP H08236260 A JPH08236260 A JP H08236260A JP 3860695 A JP3860695 A JP 3860695A JP 3860695 A JP3860695 A JP 3860695A JP H08236260 A JPH08236260 A JP H08236260A
Authority
JP
Japan
Prior art keywords
substrate
chip body
chip
bonded
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3860695A
Other languages
Japanese (ja)
Other versions
JP3265898B2 (en
Inventor
Tsunetaro Nose
恒太郎 能勢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP03860695A priority Critical patent/JP3265898B2/en
Publication of JPH08236260A publication Critical patent/JPH08236260A/en
Application granted granted Critical
Publication of JP3265898B2 publication Critical patent/JP3265898B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Thermistors And Varistors (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE: To excellently absorb instantaneous surge voltage and adjust discharge starting voltage and response voltage to be desired values by installing a pair of opposed electrodes having a micro gap in the conjunction interface of a joined chip body and forming a recessed part to be filled with an inert gas in the chip body. CONSTITUTION: A chip-type surge absorber 10 is made of a joined chip body 13 composed of insulated first and second chip bodies 11, 12 and having electrodes 16, 17 which are on the opposite each other, form a gap 14 between them, and are connected with terminal electrodes 18, 19. In the chip body 12, a recessed part 12a facing to the gap 14 is formed and an inert gas is sealed in the recessed part 12a. With this structure, surge absorbers can be miniaturized and manufactured at high productivity and moreover the absorbers can excellently absorb instantaneous surge voltage e.g. lightening surge, of which discharge starting voltage and response voltage can be controlled to be desiring values by easily adjusting the length of the gap 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電話機、ファクシミリ、
電話交換機、モデム等の通信機器用の電子機器に印加さ
れるサージ電圧を吸収する、プリント回路基板に表面実
装可能なチップ型サージアブソーバに関する。更に詳し
くは、マイクロギャップを有する一対の対向電極が不活
性ガスとともに封止(hermetic seal)されたチップ型
サージアブソーバに関するものである。
The present invention relates to a telephone, a facsimile,
The present invention relates to a chip type surge absorber that can be surface-mounted on a printed circuit board and absorbs a surge voltage applied to an electronic device for a communication device such as a telephone exchange and a modem. More specifically, the present invention relates to a chip type surge absorber in which a pair of counter electrodes having a micro gap are hermetically sealed together with an inert gas.

【0002】[0002]

【従来の技術】従来、ハーメチックシールしたマイクロ
ギャップ式サージアブソーバとして、図8及び図9に示
すようなサージアブソーバ9a及び9bが知られてい
る。2つのサージアブソーバ9a及び9bに内蔵される
ギャップ式サージ吸収素子1は、導電性皮膜1aで被包
した円柱状のセラミック素体1bの中央に円周方向に皮
膜1aを2分割する幅数10μmのマイクロギャップ1
cを形成し、このセラミック素体1bの両端に一対のキ
ャップ電極1d,1eを冠着して作られる。マイクロギ
ャップ1cにより2分割した皮膜間に電気的絶縁が図ら
れる。図8に示すように、サージアブソーバ9aは、サ
ージ吸収素子1を絶縁性を保つ管4内に収容してサージ
吸収素子1の両端に一対の封止電極2,3を配置し、こ
れらの封止電極2,3をキャップ電極1d,1eに電気
的に接続し同時に管4の内部にArガスのような不活性
ガス5を封入して作られる。封止電極2,3にはそれぞ
れリード線6,7が接続される。
2. Description of the Related Art Conventionally, as hermetically sealed microgap type surge absorbers, surge absorbers 9a and 9b as shown in FIGS. 8 and 9 have been known. The gap type surge absorbing element 1 built in the two surge absorbers 9a and 9b has a width of 10 μm which divides the coating film 1a into two in the center of the cylindrical ceramic body 1b covered with the conductive coating film 1a. The microgap 1
c is formed, and a pair of cap electrodes 1d and 1e are attached to both ends of the ceramic body 1b. Electrical insulation is achieved between the films divided into two by the microgap 1c. As shown in FIG. 8, the surge absorber 9a accommodates the surge absorbing element 1 in a tube 4 having an insulating property, arranges a pair of sealing electrodes 2 and 3 at both ends of the surge absorbing element 1, and seals them. The stop electrodes 2 and 3 are electrically connected to the cap electrodes 1d and 1e, and at the same time, an inert gas 5 such as Ar gas is sealed inside the tube 4. Lead wires 6 and 7 are connected to the sealing electrodes 2 and 3, respectively.

【0003】図9に示すように、サージアブソーバ9b
は、ギャップ式サージ吸収素子1をその両端のキャップ
電極1d,1eに接続したリード線6,7とともにガラ
ス管8で封止して作られる。ガラス管8にはArガスの
ような不活性ガス5が封入される。上記サージアブソー
バ9a又は9bでは雷サージ等に起因してリード線6,
7に異常電圧が印加すると、最初に円柱状のセラミック
素体1bを被包する導電性皮膜1aに沿ってグロー放電
が起こり、最終的に一対のキャップ電極1d,1e間で
のアーク放電に移行してサージ電圧を吸収する。
As shown in FIG. 9, a surge absorber 9b is provided.
Is made by sealing the gap type surge absorbing element 1 with the glass tubes 8 together with the lead wires 6 and 7 connected to the cap electrodes 1d and 1e at both ends thereof. The glass tube 8 is filled with an inert gas 5 such as Ar gas. In the above surge absorber 9a or 9b, the lead wires 6, 6
When an abnormal voltage is applied to 7, glow discharge first occurs along the conductive film 1a enclosing the cylindrical ceramic body 1b, and finally an arc discharge occurs between the pair of cap electrodes 1d and 1e. And absorb the surge voltage.

【0004】上記サージアブソーバ9a又は9bは、電
子機器の一対の入力線路にこの電子機器に並列に接続さ
れ、電子機器の使用電圧より高い電圧で動作するように
構成される。即ち、上記サージアブソーバはその放電開
始電圧より低い電圧では抵抗値の高い抵抗体であるが、
印加電圧がその放電開始電圧以上のときには数10Ω以
下の抵抗値の低い抵抗体になる。電子機器に雷サージ等
の数kV〜数10kVのサージ電圧が瞬間的に印加され
ると、上記サージアブソーバが放電し、このサージ電圧
を吸収して電子機器を保護するようになっている。電子
機器の前段にこの種のサージアブソーバを設けないと、
異常電圧(サージ)が電子機器内に侵入し、絶縁破壊等
を起こさせ、電子機器の動作不良等を発生させる。
The surge absorber 9a or 9b is connected to a pair of input lines of an electronic device in parallel with the electronic device and is configured to operate at a voltage higher than the operating voltage of the electronic device. That is, although the surge absorber is a resistor having a high resistance value at a voltage lower than its discharge starting voltage,
When the applied voltage is equal to or higher than the discharge start voltage, the resistance element has a low resistance value of several tens Ω or less. When a surge voltage such as a lightning surge of several kV to several tens of kV is momentarily applied to the electronic device, the surge absorber is discharged, and the surge voltage is absorbed to protect the electronic device. If you do not install this type of surge absorber in front of the electronic device,
Abnormal voltage (surge) penetrates into electronic devices, causing dielectric breakdown and other malfunctions of electronic devices.

【0005】[0005]

【発明が解決しようとする課題】しかし、上記サージア
ブソーバ9a及び9bは形状が円筒になるためにチップ
化が非常に困難であって、プリント回路基板の表面に実
装できない欠点があった。またサージ吸収素子1を絶縁
管4やガラス管8で封止するため、形状が大きくなる不
具合があった。更にカッタやレーザビームで導電性皮膜
1aでカットすることにより、マイクロギャップ1cを
形成するため、放電開始電圧、応答電圧等を所望の値に
調整することが比較的困難であって、量産しにくい問題
点があった。
However, since the surge absorbers 9a and 9b have a cylindrical shape, it is very difficult to form a chip, and there is a drawback that they cannot be mounted on the surface of a printed circuit board. Further, since the surge absorbing element 1 is sealed with the insulating tube 4 and the glass tube 8, there is a problem that the shape becomes large. Further, since the microgap 1c is formed by cutting the conductive film 1a with a cutter or a laser beam, it is relatively difficult to adjust the discharge start voltage, the response voltage, etc. to desired values, and mass production is difficult. There was a problem.

【0006】本発明の目的は、雷サージのような瞬間的
なサージ電圧を吸収することに加えて、マイクロギャッ
プの調整が容易で放電開始電圧、応答電圧を所望の値に
調整し得るチップ型サージアブソーバを提供することに
ある。本発明の別の目的は、プリント回路基板に表面実
装可能であって、製造が簡単で、小型化し易く量産性に
優れたチップ型サージアブソーバを提供することにあ
る。
The object of the present invention is to absorb a momentary surge voltage such as a lightning surge, to easily adjust the microgap, and to adjust the discharge start voltage and the response voltage to desired values. It is to provide a surge absorber. Another object of the present invention is to provide a chip type surge absorber that can be surface-mounted on a printed circuit board, is easy to manufacture, is easy to miniaturize, and is excellent in mass productivity.

【0007】[0007]

【課題を解決するための手段】図1、図2、図5及び図
7に示すように、本発明のチップ型サージアブソーバ1
0、20及び40は、絶縁性のある第1チップ体11と
絶縁性のある第2チップ体12とが一体的に接合された
接合チップ体13と、この接合チップ体13の接合界面
にマイクロギャップ14を有するように形成された一対
の対向電極16,17と、これらの対向電極16,17
にそれぞれ接続され接合チップ体13の外面両端部に設
けられた一対の端子電極18,19と、第2チップ体1
2のマイクロギャップ14に臨む位置に形成され内部に
不活性ガスが封入された凹部12aとを備えたものであ
る。図6に示すように、本発明の別のチップ型サージア
ブソーバ30では、不活性ガスが封入された凹部11a
が第1チップ体11に形成される。
As shown in FIGS. 1, 2, 5, and 7, a chip type surge absorber 1 of the present invention is provided.
Nos. 0, 20 and 40 are bonded chip bodies 13 in which a first chip body 11 having an insulating property and a second chip body 12 having an insulating property are integrally bonded, and a bonding interface of the bonded chip body 13 has a micro structure. A pair of counter electrodes 16 and 17 formed so as to have a gap 14, and these counter electrodes 16 and 17
A pair of terminal electrodes 18 and 19 which are connected to each other and are provided at both ends of the outer surface of the bonded chip body 13, and the second chip body 1.
The second concave portion 12a is formed at a position facing the micro gap 14 and has an inert gas filled therein. As shown in FIG. 6, in another chip-type surge absorber 30 of the present invention, a recess 11a in which an inert gas is filled is provided.
Are formed on the first chip body 11.

【0008】図4(a)〜(h)に示すように、本発明
のチップ型サージアブソーバ10の製造方法は、絶縁性
のある第2基板22の表面に間隔tをあけて複数の凹部
12aを形成する工程と、第1基板21に凹部12aの
間隔tに相応する間隔tで複数対の貫通孔21a,21
aを形成する工程と、これらの貫通孔21a,21aに
導電性材料25を充填する工程と、第1基板21の表面
に貫通孔21a,21aを被覆しそれぞれマイクロギャ
ップ14を有するように複数の第1電極パターン26を
形成する工程と、第1基板21の裏面に貫通孔21a,
21aを含む孔周辺部を被覆するように間隔をあけて複
数の第2電極パターン27を形成する工程と、電極パタ
ーン26,27をそれぞれ形成した第1基板21と凹部
12aを形成した第2基板22を凹部12aとマイクロ
ギャップ14が対向するように不活性ガス雰囲気中で一
体的に接合する工程と、接合した両基板21,22を凹
部12a毎にダイシングして第1チップ体11と第2チ
ップ体12からなる接合チップ体13を作製することに
より接合チップ体13の接合界面に一対の対向電極1
6,17と接合チップ体13の外面両端部に一対の対向
電極16,17にそれぞれ接続された一対の端子電極1
8,19とを形成する工程とを含む方法である。
As shown in FIGS. 4 (a) to 4 (h), in the method of manufacturing the chip type surge absorber 10 of the present invention, a plurality of recesses 12a are formed on the surface of the second substrate 22 having an insulating property at intervals t. And forming a plurality of pairs of through holes 21a, 21 in the first substrate 21 at intervals t corresponding to the intervals t of the recesses 12a.
a, a step of filling the through holes 21a, 21a with the conductive material 25, and a step of covering the through holes 21a, 21a on the surface of the first substrate 21 to form a plurality of micro gaps 14 respectively. The step of forming the first electrode pattern 26, and the through holes 21a,
21a, a step of forming a plurality of second electrode patterns 27 at intervals so as to cover the peripheral portion of the hole, and a first substrate 21 on which the electrode patterns 26 and 27 are formed and a second substrate on which the recess 12a is formed. 22 is integrally bonded in an inert gas atmosphere so that the recess 12a and the microgap 14 face each other, and the bonded substrates 21 and 22 are diced for each recess 12a to form the first chip body 11 and the second chip body 2. By manufacturing the bonded tip body 13 composed of the chip body 12, the pair of opposed electrodes 1 is formed at the bonded interface of the bonded tip body 13.
6, 17 and the pair of terminal electrodes 1 respectively connected to the pair of counter electrodes 16 and 17 at both ends of the outer surface of the bonded chip body 13.
8 and 19 are formed.

【0009】図示しないが、図5に示したチップ型サー
ジアブソーバ20の製造方法は、第2基板22に複数の
凹部12aと複数対の貫通孔22a,22aを形成し、
第2基板22から作られた第2チップ体12の外面両端
部に一対の端子電極18,19を形成する方法である。
また図示しないが、図6に示したチップ型サージアブソ
ーバ30の製造方法は、第1基板21に複数の凹部11
aと複数対の貫通孔21a,21aを形成し、第1基板
21から作られた第1チップ体11の外面両端部に一対
の端子電極18,19を形成する方法である。
Although not shown, in the method of manufacturing the chip type surge absorber 20 shown in FIG. 5, a plurality of recesses 12a and a plurality of pairs of through holes 22a, 22a are formed in the second substrate 22,
This is a method of forming a pair of terminal electrodes 18 and 19 on both ends of the outer surface of the second chip body 12 made of the second substrate 22.
Although not shown, the method of manufacturing the chip type surge absorber 30 shown in FIG.
a and a plurality of pairs of through holes 21a, 21a are formed, and a pair of terminal electrodes 18, 19 are formed at both ends of the outer surface of the first chip body 11 made of the first substrate 21.

【0010】以下、本発明を詳述する。 (a) 第1基板及び第2基板 本発明の第1チップ体11及び第2チップ体12をそれ
ぞれ作り出す第1基板21及び第2基板は絶縁性のある
基板である。これらの基板としては、絶縁性ガラス基
板、アルミナ、ムライト等の絶縁性セラミック基板、又
はシリコンウェーハが例示される。このシリコンウェー
ハはドーパントを実質的に含まない抵抗率が1000〜
10000cmΩのものが選ばれる。このシリコンウェ
ーハを用いれば既存の半導体チップの製造装置を利用し
て安価にチップ型サージアブソーバを作製することがで
きる。第1基板及び第2基板のいずれか一方又は双方に
上記例示した基板が用いられる。第1基板及び第2基板
は一方又は双方が透明又は半透明体からなることが、サ
ージアブソーバの放電状況をサージアブソーバの外部か
ら観察できるので、好ましい。この透明体としてはガラ
ス基板の他、PLZT、透明アルミナのような可視光線
を透過するセラミック焼結体から作られたセラミック基
板が挙げられる。
The present invention will be described in detail below. (a) First Substrate and Second Substrate The first substrate 21 and the second substrate that respectively produce the first chip body 11 and the second chip body 12 of the present invention are substrates having an insulating property. Examples of these substrates include an insulating glass substrate, an insulating ceramic substrate such as alumina and mullite, or a silicon wafer. This silicon wafer has a resistivity of substantially 1000
One having a resistance of 10,000 cmΩ is selected. If this silicon wafer is used, a chip-type surge absorber can be manufactured at low cost by using an existing semiconductor chip manufacturing apparatus. The above-exemplified substrate is used for either or both of the first substrate and the second substrate. It is preferable that one or both of the first substrate and the second substrate are made of a transparent or semi-transparent material because the discharge state of the surge absorber can be observed from the outside of the surge absorber. Examples of this transparent body include a glass substrate, and a ceramic substrate made of a ceramic sintered body that transmits visible light, such as PLZT and transparent alumina.

【0011】(b) 凹部及び貫通孔 基板の凹部11a,12a及び貫通孔21a,22a
は、凹部や貫通孔を形成しようとする部分を残してそれ
以外をマスキングした後、スパッタリング、レーザ光等
のドライエッチングにより形成するか、或いは凹部や貫
通孔を形成しようとする部分を残してそれ以外をレジス
ト膜で被覆した後、基板を浸食するエッチャントにより
ウエットエッチングにより形成する。また基板がシリコ
ンウェーハの場合、凹部や貫通孔を同様にレーザドリル
もしくはケミカル(化学)エッチング、又はこれらを複
合することにより形成することができる。これらの凹部
及び貫通孔は、図1や図5に示す接合チップ体13が得
られるように、基板に所定の間隔で複数個形成される。
即ち第1基板と第2基板を接合したときに1個の凹部を
中心にしてこの凹部を一対の貫通孔が挟むように形成さ
れる(図4(a)〜(g))。
(B) Recesses and through holes Recesses 11a, 12a and through holes 21a, 22a of the substrate
Is formed by dry etching such as sputtering or laser light after masking the other portions where the recesses and the through holes are to be formed, or leaving the portions where the recesses and the through holes are to be formed. After the others are covered with a resist film, they are formed by wet etching with an etchant that corrodes the substrate. When the substrate is a silicon wafer, the recess and the through hole can be similarly formed by laser drilling, chemical etching, or a combination thereof. A plurality of these recesses and through holes are formed at predetermined intervals on the substrate so that the bonded chip body 13 shown in FIGS. 1 and 5 can be obtained.
That is, when the first substrate and the second substrate are joined together, a pair of through-holes are formed so as to sandwich this recess centering on one recess (FIGS. 4A to 4G).

【0012】(c) 第1電極パターン及び第2電極パター
ン 第1電極パターン26及び第2電極パターン27はA
u,Ag,Ag/Pd,Cu等を含む導電性ペーストを
スクリーン印刷等によりコーティングする厚膜形成法に
より、又はこれらの金属をスパッタリング法、蒸着法、
イオンプレーティング法、めっき法、CVD法等の薄膜
形成法により形成する。後述するはんだバンプ18b及
び19bは電極パターン形成後に形成することもでき
る。一対の対向電極16及び17となる第1電極パター
ンは図2に破線で示されるパターンに限らず、上記厚膜
又は薄膜形成法により、図3(a)〜(f)に示すよう
な種々の電極パターンが形成される。これらの電極1
6,17の間に形成されるマイクロギャップ14のギャ
ップ幅w(図3(a))はギャップの形状に応じてまた
所望の放電開始電圧、応答電圧の値に応じて0.1μm
〜1000μmの範囲から決められる。図2ではギャッ
プ14の形状、即ちギャップを形成する電極16及び1
7の対向する各端部の形状は、平坦である。図3(a)
では山形であり、図3(b)では櫛形であり、図3
(c)では3本のヤリ形であり、図3(d)は図3
(b)と図3(c)の複合形である。また図3(e)に
示す例では小さい円形の電極16をマイクロギャップ1
4を介して帯状の電極17が包囲するように設けられ
る。この場合、図示しないが電極16に接続される貫通
孔21aが凹部に臨むので、凹部の気密を保つため、凹
部に対向する基板は2枚以上積層する。図3(e)の例
では電極16,17間にサージ電圧が印加されたときに
小円形の電極16の周囲で均等に放電するため、局所的
に高電圧が印加されず電極パターンの破壊が防止され
る。図3(f)に示す例では図3(b)の櫛形の各先端
を鈍らせることにより電極16,17間の対向距離を長
くして、局部高電圧による電極破壊を防止する。
(C) First electrode pattern and second electrode pattern The first electrode pattern 26 and the second electrode pattern 27 are A
By a thick film forming method of coating a conductive paste containing u, Ag, Ag / Pd, Cu, etc. by screen printing or the like, or by sputtering these metals, a vapor deposition method,
It is formed by a thin film forming method such as an ion plating method, a plating method, or a CVD method. The solder bumps 18b and 19b, which will be described later, can be formed after the electrode pattern is formed. The first electrode pattern serving as the pair of counter electrodes 16 and 17 is not limited to the pattern shown by the broken line in FIG. 2, but various types as shown in FIGS. 3 (a) to 3 (f) can be obtained by the thick film or thin film forming method. An electrode pattern is formed. These electrodes 1
The gap width w (FIG. 3A) of the microgap 14 formed between 6 and 17 is 0.1 μm depending on the shape of the gap and the desired discharge start voltage and the value of the response voltage.
˜1000 μm range. In FIG. 2, the shape of the gap 14, that is, the electrodes 16 and 1 that form the gap.
The shape of each of the opposing ends of 7 is flat. FIG. 3 (a)
3 is a mountain shape, and FIG. 3 (b) is a comb shape.
3 (c) shows three twisted shapes, and FIG. 3 (d) shows FIG.
It is a composite form of (b) and FIG. 3 (c). Further, in the example shown in FIG. 3E, the small circular electrode 16 is connected to the microgap 1
The strip-shaped electrode 17 is provided so as to surround the electrode 4. In this case, although not shown, since the through hole 21a connected to the electrode 16 faces the recess, two or more substrates facing the recess are stacked in order to keep the recess airtight. In the example of FIG. 3 (e), when a surge voltage is applied between the electrodes 16 and 17, the electrodes are discharged evenly around the small circular electrode 16, so that a high voltage is not applied locally and the electrode pattern is destroyed. To be prevented. In the example shown in FIG. 3 (f), the opposing ends between the electrodes 16 and 17 are lengthened by blunting the comb-shaped tips in FIG. 3 (b) to prevent electrode breakdown due to local high voltage.

【0013】(d) 基板の接合と不活性ガスの封入 第1基板21及び第2基板22の接合は、先ずマイクロ
ギャップ14が凹部11a又は12aの中心に位置する
ように位置決めして行われる。接合方法としては、第一
の方法では第1電極パターンをAu導体で作り、同時に
気密封止するために両基板の接合面をメタライズした
後、両基板を400℃程度の温度で熱圧着する。第二の
方法では基板にガラス基板を用いる場合、両基板を重ね
合わせた後、これをカーボンヒータにより熱軟化させる
ことにより接合する。また第三の方法では両基板をエポ
キシ系接着剤、はんだ、ろう材等により接合する。凹部
に不活性ガスを封入するため、接合時の雰囲気は不活性
ガス雰囲気で行われる。この凹部に封入される不活性ガ
スは、He,Ne,Ar,Kr,Xe,N2及びCO2
スからなる群から1種又は2種以上選ばれたガスであ
る。
(D) Bonding of Substrate and Encapsulation of Inert Gas The bonding of the first substrate 21 and the second substrate 22 is performed by positioning the microgap 14 at the center of the recess 11a or 12a. As the bonding method, in the first method, the first electrode pattern is made of an Au conductor, and at the same time, the bonding surfaces of both substrates are metallized for hermetic sealing, and then both substrates are thermocompression bonded at a temperature of about 400 ° C. In the second method, when a glass substrate is used as the substrate, both substrates are superposed and then joined by being thermally softened by a carbon heater. Further, in the third method, both substrates are joined with an epoxy adhesive, solder, brazing material or the like. Since the inert gas is filled in the recesses, the atmosphere at the time of bonding is an inert gas atmosphere. The inert gas filled in the recess is a gas selected from the group consisting of He, Ne, Ar, Kr, Xe, N 2 and CO 2 gas, or two or more kinds thereof.

【0014】(e) チップ化と端子電極の形成 接合した両基板は、凹部が中央に位置するようにかつ凹
部を形成した間隔でダイヤモンドブレードによりダイシ
ングしてチップ化される。得られた接合チップ体13は
直方体を形成する。このチップ化により第2電極パター
ンから作り出される一対の端子電極18及び19は、図
4に示した第2電極パターン27から作られた電極層1
8a及び19aのみで形成してもよいが、図1、図2、
図5及び図6に示すように電極層18a及び19aの上
にSn又はSn/Pbからなるはんだバンプ18b及び
19bを設けてこれらにより形成してもよい。前述した
ようにこれらのはんだバンプは第2電極パターンを形成
した直後にダイシングする前に形成しておいてもよい。
また図7に示すようにはんだバンプの代わりにリード線
18c及び19cを電極層18a及び19aにはんだ付
けしてこれらにより一対の端子電極18及び19を形成
することによりチップ型サージアブソーバ40を得るこ
ともできる。
(E) Chip Formation and Formation of Terminal Electrodes Both the bonded substrates are made into chips by dicing with a diamond blade so that the recesses are located at the center and at intervals where the recesses are formed. The obtained bonded tip body 13 forms a rectangular parallelepiped. The pair of terminal electrodes 18 and 19 formed from the second electrode pattern by this chip formation is the electrode layer 1 formed from the second electrode pattern 27 shown in FIG.
Although it may be formed by only 8a and 19a,
As shown in FIGS. 5 and 6, solder bumps 18b and 19b made of Sn or Sn / Pb may be provided on the electrode layers 18a and 19a to form the bumps. As described above, these solder bumps may be formed immediately after forming the second electrode pattern and before dicing.
Further, as shown in FIG. 7, lead wires 18c and 19c are soldered to the electrode layers 18a and 19a instead of the solder bumps to form a pair of terminal electrodes 18 and 19 to obtain a chip type surge absorber 40. You can also

【0015】[0015]

【作用】本発明のチップ型サージアブソーバ10〜40
は一対の端子電極18及び19が接続された線路に継続
して過電圧又は過電流が侵入すると、凹部14内に位置
する対向電極16及び17のマイクロギャップ間で放電
を生じる。この放電の発熱による対向電極の損傷程度が
甚だしくなり、ギャップ間隔が広がる。この結果、サー
ジアブソーバ10〜40は致命的な熱損傷になり得る前
にその抵抗値は高まって放電開始電圧及び放電維持電圧
が過電圧より高くなり、放電は停止する。
Operation: Chip type surge absorber 10-40 of the present invention
When an overvoltage or an overcurrent continuously enters the line to which the pair of terminal electrodes 18 and 19 are connected, a discharge is generated between the micro gaps of the counter electrodes 16 and 17 located in the recess 14. The degree of damage to the counter electrode due to the heat generated by this discharge becomes severe, and the gap distance increases. As a result, before the surge absorbers 10 to 40 can be fatally damaged by heat, their resistance values increase, the discharge start voltage and the discharge sustaining voltage become higher than the overvoltage, and the discharge is stopped.

【0016】[0016]

【実施例】次に、本発明の実施例を比較例とともに図面
に基づいて詳しく説明する。 <実施例1>図1及び図2に示すギャップ式のチップ型
サージアブソーバ10を図4に基づいて製造した。先
ず、絶縁性のある厚さ0.6mmのシリコンウェーハ2
2の表面にt=1.57mmの等間隔で複数の凹部12
aを形成した。この間隔tmmが接合チップ体13の長
さに相応する。具体的には図4(a)及び(b)に示す
ようにシリコンウェーハ22の表面に凹部を形成しよう
とする部分に窓孔28aが明けられたマスク28をウェ
ーハ22の表面を被覆し、ドライエッチングした。図4
(a)において、t1は0.5mm、t2は1.07mm
である。一方、絶縁性のある厚さ0.2mmのガラス基
板21にt=1.57mmの間隔で複数対の貫通孔21
aを形成した。具体的には図4(c)及び(d)に示す
ように貫通孔を形成しようとする部分にレーザドリルと
ケミカルエッチングを行うことにより直径0.2mmの
貫通孔21aをあけた。図4(c)において、29はレ
ジスト膜、29aはその孔であり、t3は0.61m
m、t4は0.96mmである。
Embodiments of the present invention will now be described in detail with reference to the drawings together with comparative examples. Example 1 A gap type chip type surge absorber 10 shown in FIGS. 1 and 2 was manufactured based on FIG. First, an insulating silicon wafer having a thickness of 0.6 mm 2
2 has a plurality of concave portions 12 at equal intervals of t = 1.57 mm.
a was formed. This interval tmm corresponds to the length of the bonded tip body 13. Specifically, as shown in FIGS. 4A and 4B, a mask 28 in which a window hole 28a is formed in a portion where a concave portion is to be formed on the surface of the silicon wafer 22 is coated on the surface of the wafer 22 and a dry process is performed. Etched. FIG.
In (a), t 1 is 0.5 mm and t 2 is 1.07 mm
Is. On the other hand, a plurality of pairs of through holes 21 are formed in the insulating glass substrate 21 having a thickness of 0.2 mm at an interval of t = 1.57 mm.
a was formed. Specifically, as shown in FIGS. 4C and 4D, a laser drill and chemical etching were performed on the portion where the through hole is to be formed, thereby forming a through hole 21a having a diameter of 0.2 mm. In FIG. 4C, 29 is a resist film, 29a is its hole, and t 3 is 0.61 m.
m and t 4 are 0.96 mm.

【0017】図4(e)に示すように、複数の貫通孔2
1aに導電性材料であるAgポリイミド接着剤ペースト
25を厚膜技術で充填印刷し、180℃30分で硬化し
た。次いでガラス基板21の表面にそれぞれ幅10μm
のマイクロギャップ14を有するように複数の第1電極
パターン26を形成した。これは薄膜技術で導体膜を形
成した後、フォトエッチングでパターンニングすること
により行った。図4(f)に示すように、ガラス基板2
1を裏返して、基板21の裏面に貫通孔21aを含む孔
周辺部を被覆するように間隔をあけて第1電極パターン
と同じ方法で複数の第2電極パターン27を形成した。
次いで、図4(g)に示すように電極パターン26,2
7をそれぞれ形成したガラス基板21と凹部12aを形
成したシリコンウェーハ22を凹部12aとマイクロギ
ャップ14が対向するようにArガスからなる不活性ガ
ス雰囲気中で一体的に接合した。接合にはエポキシ系接
着剤を用いた。これにより凹部12内にArガスが封入
された。図4(g)の破線に示すように、接合したガラ
ス基板21とシリコンウェーハ22を凹部12a毎にダ
イシングした。
As shown in FIG. 4 (e), a plurality of through holes 2
An Ag polyimide adhesive paste 25, which is a conductive material, was filled and printed on 1a by a thick film technique and cured at 180 ° C. for 30 minutes. Then, on the surface of the glass substrate 21, a width of 10 μm
A plurality of first electrode patterns 26 were formed so as to have the micro gaps 14 of. This was done by forming a conductor film by thin film technology and then patterning by photoetching. As shown in FIG. 4F, the glass substrate 2
1 was turned upside down, and a plurality of second electrode patterns 27 were formed on the back surface of the substrate 21 at intervals so as to cover the hole peripheral portion including the through holes 21a in the same manner as the first electrode pattern.
Then, as shown in FIG.
The glass substrate 21 on which No. 7 was formed and the silicon wafer 22 on which the recess 12a was formed were integrally bonded in an inert gas atmosphere of Ar gas so that the recess 12a and the microgap 14 faced each other. An epoxy adhesive was used for joining. As a result, Ar gas was enclosed in the recess 12. As shown by the broken line in FIG. 4 (g), the bonded glass substrate 21 and silicon wafer 22 were diced for each recess 12a.

【0018】図4(h)及び図1に示すように、このダ
イシングにより第1チップ体11と第2チップ体12か
らなる接合チップ体13を作製した。第2電極パターン
27により形成した電極層18a,19a(図2)の上
にははんだバンプ18b,19bをそれぞれ形成した。
これにより接合チップ体13の接合界面に一対の対向電
極16,17と、第1チップ体11の外面両端部に電極
層18a,19aとはんだバンプ18b,19bからな
る一対の端子電極18,19とを形成した。一対の端子
電極18,19は貫通孔に充填された導電性材料を介し
て一対の対向電極16,17にそれぞれ接続された。こ
のチップ型サージアブソーバ10は長さが約1.42m
m、幅が約1.42mm、高さが約0.8mmであっ
た。
As shown in FIGS. 4 (h) and 1, a bonded chip body 13 composed of a first chip body 11 and a second chip body 12 was produced by this dicing. Solder bumps 18b and 19b were respectively formed on the electrode layers 18a and 19a (FIG. 2) formed by the second electrode pattern 27.
As a result, a pair of opposing electrodes 16 and 17 are provided at the joining interface of the joining chip body 13, and a pair of terminal electrodes 18 and 19 including the electrode layers 18a and 19a and solder bumps 18b and 19b are provided at both ends of the outer surface of the first chip body 11. Was formed. The pair of terminal electrodes 18 and 19 were connected to the pair of opposing electrodes 16 and 17, respectively, through a conductive material filled in the through holes. This tip type surge absorber 10 has a length of about 1.42 m.
m, the width was about 1.42 mm, and the height was about 0.8 mm.

【0019】<実施例2>図3(a)に示すギャップ幅
wが10μmの電極パターンにより一対の対向電極1
6,17を形成した以外は、実施例1と同一にしてチッ
プ型サージアブソーバを作製した。
<Embodiment 2> A pair of counter electrodes 1 having an electrode pattern having a gap width w of 10 μm shown in FIG.
A chip type surge absorber was produced in the same manner as in Example 1 except that Nos. 6 and 17 were formed.

【0020】<実施例3>図3(b)に示すギャップ幅
wが10μmの電極パターンにより一対の対向電極1
6,17を形成した以外は、実施例1と同一にしてチッ
プ型サージアブソーバを作製した。
<Embodiment 3> A pair of counter electrodes 1 having an electrode pattern having a gap width w of 10 μm shown in FIG. 3B.
A chip type surge absorber was produced in the same manner as in Example 1 except that Nos. 6 and 17 were formed.

【0021】<比較例1>図8に示すギャップ式サージ
アブソーバ9aを比較例1とした。このサージアブソー
バ9aは導電性皮膜1aで被包した円柱状のセラミック
素体1bの中央に円周方向に皮膜1aを2分割する幅3
0μmのマイクロギャップ1cを形成し、このセラミッ
ク素体1bの両端に一対のキャップ電極1d,1eを冠
着して作られた。サージアブソーバ9aは、サージ吸収
素子1を絶縁性を保つ管4内に収容してサージ吸収素子
1の両端に一対の封止電極2,3を配置し、これらの封
止電極2,3をキャップ電極1d,1eに電気的に接続
し同時に管4の内部にArガス5を800Torrの圧
力で封入して作られた。封止電極2,3にはそれぞれリ
ード線6,7が接続された。
<Comparative Example 1> The gap type surge absorber 9a shown in FIG. The surge absorber 9a has a width 3 that divides the coating 1a into two in the circumferential direction at the center of a cylindrical ceramic body 1b covered with a conductive coating 1a.
A microgap 1c of 0 μm was formed, and a pair of cap electrodes 1d and 1e were capped on both ends of this ceramic body 1b. The surge absorber 9a accommodates the surge absorbing element 1 in a tube 4 that maintains insulation, arranges a pair of sealing electrodes 2 and 3 at both ends of the surge absorbing element 1, and caps these sealing electrodes 2 and 3. It was made by electrically connecting to the electrodes 1d and 1e and at the same time enclosing Ar gas 5 inside the tube 4 at a pressure of 800 Torr. Lead wires 6 and 7 were connected to the sealing electrodes 2 and 3, respectively.

【0022】<比較試験と評価>実施例1〜3と比較例
1のサージアブソーバについて、それぞれ放電開始電
圧、(1.2×50)μsec10kVサージ電圧に
対する応答電圧、絶縁抵抗及び静電容量を測定し、
過電圧・過電流の印加試験及びサージ耐量試験を行
った。過電圧・過電流の印加試験はAC600V−3
00mAの過電圧・過電流を5分間印加した。またサ
ージ耐量試験は(8×20)μsecサージにて耐え得
る電流値を測定した。その結果を表1に示す。
<Comparative Test and Evaluation> With respect to the surge absorbers of Examples 1 to 3 and Comparative Example 1, the discharge start voltage, the response voltage to the (1.2 × 50) μsec 10 kV surge voltage, the insulation resistance and the capacitance were measured. Then
An overvoltage / overcurrent application test and a surge withstand test were performed. Overvoltage / overcurrent application test is AC600V-3
An overvoltage / overcurrent of 00 mA was applied for 5 minutes. In the surge withstand test, a current value which can withstand a (8 × 20) μsec surge was measured. Table 1 shows the results.

【0023】[0023]

【表1】 [Table 1]

【0024】表1から明らかなように、実施例1〜実施
例3のチップ型サージアブソーバは従来のサージアブソ
ーバ9aと比べて放電性能は同等であった。特にギャッ
プ幅及びギャップ形状を変えることにより、放電開始電
圧及び応答電圧を変えることができた。
As is clear from Table 1, the chip type surge absorbers of Examples 1 to 3 had the same discharge performance as the conventional surge absorber 9a. In particular, the discharge start voltage and the response voltage could be changed by changing the gap width and the gap shape.

【0025】[0025]

【発明の効果】以上述べたように、本発明によれば、雷
サージのような瞬間的なサージ電圧を吸収することに加
えて、継続的な過電圧又は過電流の侵入があった場合に
は導電性セラミック薄膜の導電性皮膜が熱損傷して、ギ
ャップ間隔が広がることにより放電開始電圧及び放電維
持電圧が上昇し、サージアブソーバの異常発熱のみなら
ず、電子機器及びこの機器を搭載するプリント基板の熱
的損傷、発火等を防止することができる。また本発明の
サージアブソーバは従来のような円筒状の絶縁管でない
ため、チップ化が容易で小型化でき、占有スペースが僅
かで済み、組立が簡便で量産性に優れる。これによりプ
リント回路基板の表面に容易に実装することができる。
更にマイクロギャップをレーザ光やダイヤモンドブレー
ドで形成する従来法と比べて、本発明では薄膜又は厚膜
形成技術により形成するため、ギャップ形成時間を短縮
できるだけでなく、ギャップ幅及びギャップ形状を所望
の放電特性に応じて容易に最適なものにすることができ
る。
As described above, according to the present invention, in addition to absorbing a momentary surge voltage such as a lightning surge, when there is a continuous overvoltage or overcurrent intrusion, The conductive film of the conductive ceramic thin film is thermally damaged and the gap interval is widened to increase the discharge start voltage and the discharge sustaining voltage, which causes not only abnormal heat generation of the surge absorber but also electronic equipment and a printed circuit board on which the equipment is mounted. It is possible to prevent thermal damage, ignition, etc. Further, since the surge absorber of the present invention is not a conventional cylindrical insulating tube, it can be easily made into a chip, can be miniaturized, occupies a small space, is easy to assemble, and is excellent in mass productivity. This allows easy mounting on the surface of the printed circuit board.
Further, compared with the conventional method of forming a microgap with a laser beam or a diamond blade, in the present invention, since it is formed by a thin film or thick film forming technique, not only can the gap forming time be shortened, but the gap width and the gap shape can be changed to a desired discharge. It can be easily optimized depending on the characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のチップ型サージアブソーバの図2のA
−A線断面図。
FIG. 1A of FIG. 2 of the chip type surge absorber of the present invention
-A line sectional view.

【図2】その平面図。FIG. 2 is a plan view thereof.

【図3】本発明の種々のギャップの形状を示す一対の対
向電極の平面図。
FIG. 3 is a plan view of a pair of counter electrodes showing various gap shapes according to the present invention.

【図4】図1及び図2のチップ型サージアブソーバの製
造方法を示す断面図。
FIG. 4 is a cross-sectional view showing a method of manufacturing the chip type surge absorber shown in FIGS. 1 and 2.

【図5】本発明の別のチップ型サージアブソーバを示す
図1に対応する断面図。
5 is a sectional view corresponding to FIG. 1, showing another chip type surge absorber of the present invention.

【図6】本発明の更に別のチップ型サージアブソーバを
示す図1に対応する断面図。
FIG. 6 is a cross-sectional view corresponding to FIG. 1, showing still another chip type surge absorber of the present invention.

【図7】本発明の更にまた別のチップ型サージアブソー
バを示す図1に対応する断面図。
FIG. 7 is a cross-sectional view corresponding to FIG. 1, showing still another chip type surge absorber of the present invention.

【図8】従来例のギャップ式サージアブソーバの中央縦
断面図。
FIG. 8 is a central longitudinal cross-sectional view of a gap type surge absorber of a conventional example.

【図9】別の従来例のギャップ式サージアブソーバの中
央縦断面図。
FIG. 9 is a central longitudinal sectional view of another conventional gap type surge absorber.

【符号の説明】[Explanation of symbols]

10,20,30,40 チップ型サージアブソーバ 11 第1チップ体 11a,12a 凹部 12 第2チップ体 13 接合チップ体 14 マイクロギャップ 16,17 対向電極 18,19 端子電極 21 ガラス基板(第1基板) 21a,22a 貫通孔 22 シリコンウェーハ(第2基板) 25 導電性材料 26 第1電極パターン 27 第2電極パターン 10, 20, 30, 40 Chip type surge absorber 11 First chip body 11a, 12a Recessed portion 12 Second chip body 13 Bonded chip body 14 Microgap 16,17 Counter electrode 18,19 Terminal electrode 21 Glass substrate (first substrate) 21a, 22a Through hole 22 Silicon wafer (second substrate) 25 Conductive material 26 First electrode pattern 27 Second electrode pattern

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性のある第1チップ体(11)と絶縁性
のある第2チップ体(12)とが一体的に接合された接合チ
ップ体(13)と、 前記接合チップ体(13)の接合界面にマイクロギャップ(1
4)を有するように形成された一対の対向電極(16,17)
と、 前記一対の対向電極(16,17)にそれぞれ接続され前記接
合チップ体(13)の外面両端部に設けられた一対の端子電
極(18,19)と、 前記第1チップ体(11)又は前記第2チップ体(12)の前記
マイクロギャップ(14)に臨む位置に形成され内部に不活
性ガスが封入された凹部(11a又は12a)とを備えたチップ
型サージアブソーバ。
1. A bonded chip body (13) in which an insulative first chip body (11) and an insulative second chip body (12) are integrally bonded, and the bonded chip body (13). ) Micro-gap (1
4) a pair of counter electrodes (16, 17) formed to have
A pair of terminal electrodes (18, 19) respectively connected to the pair of opposing electrodes (16, 17) and provided at both ends of the outer surface of the bonded tip body (13); and the first chip body (11) Alternatively, a chip type surge absorber having a recess (11a or 12a) formed in a position facing the micro gap (14) of the second chip body (12) and having an inert gas filled therein.
【請求項2】 第1チップ体(11)及び第2チップ体(12)
のいずれか一方又は双方が透明又は半透明のチップ体か
らなる請求項1記載のチップ型サージアブソーバ。
2. A first chip body (11) and a second chip body (12)
2. The chip type surge absorber according to claim 1, wherein either one or both of them is a transparent or semi-transparent chip body.
【請求項3】 絶縁性のある第1基板(21)又は絶縁性の
ある第2基板(22)のいずれか一方の基板の表面に間隔
(t)をあけて複数の凹部(11a又は12a)を形成する工程
と、 前記第1基板(21)又は第2基板(22)のいずれか他方の基
板に前記凹部(11a又は12a)の間隔(t)に相応する間隔(t)
で複数対の貫通孔(21a,21a又は22a,22a)を形成する工程
と、 前記貫通孔(21a,21a又は22a,22a)に導電性材料(25)を充
填する工程と、 前記第1基板(21)又は第2基板(22)のいずれか他方の基
板の表面に前記貫通孔(21a,21a又は22a,22a)を被覆しそ
れぞれマイクロギャップ(14)を有するように複数の第1
電極パターン(26)を形成する工程と、 前記他方の基板の裏面に前記貫通孔(21a,21a又は22a,22
a)を含む孔周辺部を被覆するように間隔をあけて複数の
第2電極パターン(27)を形成する工程と、 前記凹部(12a)と第1電極パターン(26)と第2電極パタ
ーン(27)をそれぞれ形成した第1基板(21)及び第2基板
(22)を前記凹部(11a又は12a)と前記マイクロギャップ(1
4)が対向するように不活性ガス雰囲気中で一体的に接合
する工程と、 前記接合した両基板(21,22)を前記凹部(11a又は12a)毎
にダイシングして第1チップ体(11)と第2チップ体(12)
からなる接合チップ体(13)を作製することにより前記接
合チップ体(13)の接合界面に一対の対向電極(16,17)と
前記第1チップ体(11)の外面両端部に前記一対の対向電
極(16,17)にそれぞれ接続された一対の端子電極(18,19)
とを形成する工程とを含むチップ型サージアブソーバの
製造方法。
3. A gap is provided on the surface of either one of the insulating first substrate (21) and the insulating second substrate (22).
(t) to form a plurality of recesses (11a or 12a), and the gap between the recesses (11a or 12a) in the other substrate of the first substrate (21) or the second substrate (22) interval (t) corresponding to (t)
A step of forming a plurality of pairs of through holes (21a, 21a or 22a, 22a), the step of filling the through holes (21a, 21a or 22a, 22a) with a conductive material (25), the first substrate (21) or the second substrate (22), the surface of the other substrate is covered with the through-holes (21a, 21a or 22a, 22a) and has a plurality of first gaps (14) each having a microgap (14).
Step of forming an electrode pattern (26), the through hole (21a, 21a or 22a, 22 in the back surface of the other substrate
a) forming a plurality of second electrode patterns (27) at intervals so as to cover the periphery of the hole including a), the recess (12a), the first electrode pattern (26), and the second electrode pattern (26). First substrate (21) and second substrate respectively formed with (27)
(22) the recess (11a or 12a) and the micro gap (1
4) are integrally bonded in an inert gas atmosphere so that they face each other, and the bonded both substrates (21, 22) are diced for each recess (11a or 12a) to form a first chip body (11). ) And the second chip body (12)
By forming a bonded chip body (13) made of the above, a pair of opposed electrodes (16, 17) are provided at the bonded interface of the bonded chip body (13) and the pair of opposed electrodes are provided at both ends of the outer surface of the first chip body (11). A pair of terminal electrodes (18, 19) respectively connected to the counter electrodes (16, 17)
And a method of manufacturing a chip type surge absorber, the method comprising:
【請求項4】 絶縁性のある第1基板又は絶縁性のある
第2基板のいずれか一方の基板の表面に間隔をあけて複
数の凹部を形成する工程と、 前記凹部を挟むように前記一方の基板に間隔をあけて複
数対の貫通孔を形成する工程と、 前記貫通孔に導電性材料を充填する工程と、 前記第1基板又は第2基板のいずれか他方の基板の表面
に前記凹部の間隔に相応する間隔でマイクロギャップを
有するように複数の第1電極パターンをそれぞれ形成す
る工程と、 前記他方の基板の裏面に前記貫通孔を含む孔周辺部を被
覆するように間隔をあけて複数の第2電極パターンを形
成する工程と、 前記凹部と第1電極パターンと第2電極パターンをそれ
ぞれ形成した第1基板及び第2基板を前記凹部と前記マ
イクロギャップが対向するように不活性ガス雰囲気中で
一体的に接合する工程と、 前記接合した両基板を前記凹部毎にダイシングして第1
チップ体(11)と第2チップ体(12)からなる接合チップ体
(13)を作製することにより前記接合チップ体(13)の接合
界面に一対の対向電極(16,17)と前記第2チップ体(12)
の外面両端部に前記一対の対向電極(16,17)にそれぞれ
接続された一対の端子電極(18,19)とを形成する工程と
を含むチップ型サージアブソーバの製造方法。
4. A step of forming a plurality of recesses at intervals on the surface of either one of the first substrate having an insulating property and the second substrate having an insulating property, and the one so as to sandwich the recesses. Forming a plurality of pairs of through holes on the substrate at intervals, filling the through holes with a conductive material, and forming the recess on the surface of the other substrate of the first substrate or the second substrate. Forming a plurality of first electrode patterns so as to have a microgap at an interval corresponding to the interval, and providing an interval on the back surface of the other substrate so as to cover the hole peripheral part including the through hole. A step of forming a plurality of second electrode patterns, and an inert gas so that the concave portion and the microgap face the first substrate and the second substrate on which the concave portion, the first electrode pattern and the second electrode pattern are formed, respectively. Atmosphere A step of integrally joined at medium, the by dicing the two substrates described above bonded to each of the recesses 1
Bonded chip body consisting of chip body (11) and second chip body (12)
By manufacturing (13), a pair of counter electrodes (16, 17) and the second chip body (12) are formed at the joint interface of the joint tip body (13).
Forming a pair of terminal electrodes (18, 19) respectively connected to the pair of counter electrodes (16, 17) on both ends of the outer surface of the chip type surge absorber.
【請求項5】 第1基板(21)及び第2基板(22)のいずれ
か一方又は双方が透明又は半透明の基板からなる請求項
3又は4記載のチップ型サージアブソーバ。
5. The chip type surge absorber according to claim 3, wherein one or both of the first substrate (21) and the second substrate (22) are transparent or semitransparent substrates.
JP03860695A 1995-02-27 1995-02-27 Manufacturing method of chip type surge absorber Expired - Fee Related JP3265898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03860695A JP3265898B2 (en) 1995-02-27 1995-02-27 Manufacturing method of chip type surge absorber

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03860695A JP3265898B2 (en) 1995-02-27 1995-02-27 Manufacturing method of chip type surge absorber

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2001077909A Division JP3489627B2 (en) 2001-03-19 2001-03-19 Chip type surge absorber

Publications (2)

Publication Number Publication Date
JPH08236260A true JPH08236260A (en) 1996-09-13
JP3265898B2 JP3265898B2 (en) 2002-03-18

Family

ID=12529936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03860695A Expired - Fee Related JP3265898B2 (en) 1995-02-27 1995-02-27 Manufacturing method of chip type surge absorber

Country Status (1)

Country Link
JP (1) JP3265898B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048626A (en) * 2005-08-10 2007-02-22 Murata Mfg Co Ltd Chip type lightning arrester and its manufacturing method
JP2008041883A (en) * 2006-08-04 2008-02-21 Iriso Denshi Kogyo Kk Overvoltage protection element
JP2008085957A (en) * 2006-09-29 2008-04-10 Nippon Dempa Kogyo Co Ltd Tuning fork type crystal vibrator element
JP2008085743A (en) * 2006-09-28 2008-04-10 Nippon Dempa Kogyo Co Ltd Crystal vibrator, and oscillating device
WO2008146514A1 (en) * 2007-05-28 2008-12-04 Murata Manufacturing Co., Ltd. Esd protection device
JP2009016616A (en) * 2007-07-05 2009-01-22 Tdk Corp Surge absorbing element, and light emitting device
WO2009136535A1 (en) * 2008-05-08 2009-11-12 株式会社 村田製作所 Substrate incorporating esd protection function
JP2010108746A (en) * 2008-10-30 2010-05-13 Panasonic Corp Antistatic component, and method of manufacturing the same
US7733620B2 (en) * 2006-07-19 2010-06-08 Ta-I Technology Co., Ltd Chip scale gas discharge protective device and fabrication method of the same
JP2011187439A (en) * 2010-02-15 2011-09-22 Murata Mfg Co Ltd Esd protection device
JP2011243896A (en) * 2010-05-21 2011-12-01 Murata Mfg Co Ltd Ceramic multilayer substrate and electronic module
JP2015167215A (en) * 2014-03-04 2015-09-24 Koa株式会社 Chip resistor and method of manufacturing the same
KR20170137110A (en) * 2015-03-17 2017-12-12 본스인코오포레이티드 Flat gas discharge tube devices and methods
JP2019208202A (en) * 2018-03-30 2019-12-05 ザ・ボーイング・カンパニーTheBoeing Company Microplasma limiter for rf, and microwave circuit protection

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048626A (en) * 2005-08-10 2007-02-22 Murata Mfg Co Ltd Chip type lightning arrester and its manufacturing method
US7733620B2 (en) * 2006-07-19 2010-06-08 Ta-I Technology Co., Ltd Chip scale gas discharge protective device and fabrication method of the same
JP2008041883A (en) * 2006-08-04 2008-02-21 Iriso Denshi Kogyo Kk Overvoltage protection element
JP2008085743A (en) * 2006-09-28 2008-04-10 Nippon Dempa Kogyo Co Ltd Crystal vibrator, and oscillating device
JP4618440B2 (en) * 2006-09-28 2011-01-26 日本電波工業株式会社 Crystal resonator element and vibration device
JP2008085957A (en) * 2006-09-29 2008-04-10 Nippon Dempa Kogyo Co Ltd Tuning fork type crystal vibrator element
WO2008146514A1 (en) * 2007-05-28 2008-12-04 Murata Manufacturing Co., Ltd. Esd protection device
KR101027092B1 (en) * 2007-05-28 2011-04-05 가부시키가이샤 무라타 세이사쿠쇼 ??? protection device
US7633735B2 (en) 2007-05-28 2009-12-15 Murata Manufacturing Co., Ltd. ESD protection device
JP2009016616A (en) * 2007-07-05 2009-01-22 Tdk Corp Surge absorbing element, and light emitting device
WO2009136535A1 (en) * 2008-05-08 2009-11-12 株式会社 村田製作所 Substrate incorporating esd protection function
JP5093345B2 (en) * 2008-05-08 2012-12-12 株式会社村田製作所 Board with built-in ESD protection function
US8693157B2 (en) 2008-05-08 2014-04-08 Murata Manufacturing Co., Ltd. Substrate including an ESD protection function
JP2010108746A (en) * 2008-10-30 2010-05-13 Panasonic Corp Antistatic component, and method of manufacturing the same
JP2011187439A (en) * 2010-02-15 2011-09-22 Murata Mfg Co Ltd Esd protection device
JP2011243896A (en) * 2010-05-21 2011-12-01 Murata Mfg Co Ltd Ceramic multilayer substrate and electronic module
JP2015167215A (en) * 2014-03-04 2015-09-24 Koa株式会社 Chip resistor and method of manufacturing the same
KR20170137110A (en) * 2015-03-17 2017-12-12 본스인코오포레이티드 Flat gas discharge tube devices and methods
JP2018512709A (en) * 2015-03-17 2018-05-17 ボーンズ、インコーポレイテッド Flat type gas discharge tube device and method
JP2019208202A (en) * 2018-03-30 2019-12-05 ザ・ボーイング・カンパニーTheBoeing Company Microplasma limiter for rf, and microwave circuit protection

Also Published As

Publication number Publication date
JP3265898B2 (en) 2002-03-18

Similar Documents

Publication Publication Date Title
JP3265898B2 (en) Manufacturing method of chip type surge absorber
US7804164B2 (en) Subminiature electronic device having hermetic cavity and method of manufacturing the same
JP3439746B2 (en) Surface mount type surge absorbing element and method of manufacturing the same
JP3489627B2 (en) Chip type surge absorber
US6606230B2 (en) Chip-type surge absorber and method for producing the same
JP2007317541A (en) Surge suppressor
WO1999043061A1 (en) Surge absorber
JP3303025B2 (en) Chip type micro gap type surge absorber
JPH09266053A (en) Chip type surge absorber and its manufacture
JP2004014437A (en) Chip type surge absorber and its manufacturing method
JP2001160502A (en) Surge absorbing device and its manufacturing method
JP3508574B2 (en) Chip type surge absorber
JP4239422B2 (en) surge absorber
JP4161696B2 (en) Chip-type surge absorber and manufacturing method thereof
JP2000173743A (en) Chip-type surge absorber and its manufacture
JP4123981B2 (en) Chip-type surge absorber and manufacturing method thereof
JP4239420B2 (en) Surge absorber and manufacturing method thereof
JP3777886B2 (en) Chip type surge absorber (1)
JP3777885B2 (en) Chip type surge absorber (2)
JPH0370407B2 (en)
JPH1069960A (en) Surge absorber
JP3464143B2 (en) Electronic component storage package
JP2001006840A (en) Surge absorption element and its manufacture
JPH11238820A (en) Package for accommodating electronic component
JP2000003775A (en) Chip type surge absorber and manufacture thereof

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20011204

LAPS Cancellation because of no payment of annual fees