JPH08224339A - Data transmitting device of pachinko machine - Google Patents

Abstract

PURPOSE: To eliminate the process of setting the wait time in the processing time in data transfer process on the main control part side, allow smooth performance of the data transfer, start the displaying motion of a figure displaying device with no lag from the generation of a specific playing condition, and exclude noise intrusion in the data transfer. CONSTITUTION: The data transfer device of pachinko machine is furnished with a main control part 1, a sub-control part 6 to make display drive control of a figure displaying device in conformity to the control signal given by the main control part 1, and a unidirectional data transferring means 40 which is interposed between the main control part 1 and sub-control part 6, admits transfer of command data only from the main 1 to sub control part 6, and prohibits input of data signal from the sub 6 to the main control part 1, thereby, transfer of the command data is conducted only in the direction from the main 1 to sub control part 6. Therein necessity for changing over from signal transmission to reception or vice versa is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data in a pachinko machine for transmitting control command data transmitted from the main control section to the sub control section in a main control section and a sub control section provided in the pachinko machine. The present invention relates to a transmission device.

[0002]

2. Description of the Related Art In a pachinko gaming machine, for example, a symbol display device is provided, and a complicated display operation is performed on the display screen, or several kinds of display screens are switched according to a game mode. By doing so, the player's various tastes are satisfied. In such a pachinko gaming machine, it is possible to control all the drive control elements arranged in the pachinko machine only with the main control section for performing control related to the entire pachinko game of the pachinko machine. Since it is difficult because the processing timing and memory storage capacity are limited, a dedicated sub-control unit is provided for each drive control element, and control command data consisting of control signals and output data is sent from the main control unit. The data is transferred to the sub control unit, and the drive control element is controlled and driven by the sub control unit according to the control command data.

The command data for control transferred from the main control unit is set to a plurality of status data and a pattern display device showing a game situation in a pachinko machine, for example, when the sub control unit is a symbol display device. It is each data etc. which show the kind and display position of the symbol displayed on each symbol display part.

Further, the status data is, for example, in a pachinko machine, waiting for a game before the game is started, during a game, waiting for a symbol change before the start of a symbol change, during a symbol change, and displaying a plurality of symbols. The game state (hereinafter, reach) in which the combination of the symbols stopped in the other symbol display units is the big hit, leaving one symbol display unit being changed among the parts, and the jackpot in the symbol display unit is Big hit operation information that shows the contents of big hit operation such as opening and closing operation of the prize winning device arranged to give a profit to the player only during the big hit when it occurs, the number of winnings to the prize winning device In addition, the contents include the number of times of opening and closing operations of the winning device.

In this way, the control command data transferred from the main control unit to the sub control unit is changed, for example, when the number of symbol display units is increased or the display is switched depending on the gaming situation of the pachinko machine. The amount of command data will inevitably increase.

In the conventional transmission of command data between the main control unit and the sub-control unit, as shown in the timing chart of FIG. 18, the transmission of the command data from the main control unit, which is the transmitting side, is transmitted as a WR signal. And output
Data transfer is performed by the handshake method, which notifies the sub-control unit side on the receiving side, and the receiving side outputs a READY signal to notify the main control unit side that command data has been received. Therefore, in the processing time in the data transfer processing on the main control unit side, a waiting time is set after the WR signal is output and before the input of the READY signal transmitted from the sub control unit is detected.

However, as the display drive processing executed in the symbol display device becomes more complicated as described above,
Since the amount of command data increases, it is necessary to set the waiting time longer. Also, if the input of the READY signal transmitted from the sub-control unit is not detected, the next command data is not transferred, so the amount of command data that can be transferred within a fixed time decreases, so the display operation of the symbol display device is reduced. In some cases, the occurrence of a specific game state may be delayed. Furthermore, since transmission / reception switching operation is performed, noise may intrude during switching.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to allow a data transfer to be smoothly performed without the need to set a waiting time in the processing time in the data transfer processing on the main control section side, and a symbol display device can be provided. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transmission device in a pachinko machine in which the display operation of (1) is activated without delaying the occurrence of a specific game state, and intrusion of noise can be eliminated in data transfer.

[0009]

In order to solve the above-mentioned problems, a data transmission device in a pachinko machine of the present invention includes a main control unit for performing control relating to the entire pachinko game of the pachinko machine, and the pachinko machine. Along with the symbol display device provided, between the main control unit and the sub-control unit, and a sub-control unit for display drive control of the symbol display device according to a control signal from the main control unit. One-way data transfer means is provided which is intervening and allows command data to be transferred only from the main control unit to the sub control unit, and prohibits data signal input from the sub control unit to the main control unit. And

[0010]

The main control unit controls the entire pachinko game of the pachinko machine and transfers command data for instructing the sub controller to display the symbols according to the game mode through the one-way data transfer means. To do. The sub-control unit provided in the symbol display device included in the pachinko machine controls the display drive of the symbol display device according to the control signal from the main control unit, that is, according to the command data. The one-way data transfer means enables transfer of command data only from the main control unit to the sub control unit, and prohibits data signal input from the sub control unit to the main control unit. Since the command data can be transferred only from the main control unit to the sub control unit by the one-way data transfer unit, it is not necessary to set a waiting time in the processing time in the data transfer process on the main control unit side. The data transfer can be smoothly performed, and the display operation of the symbol display device can be activated without delaying the occurrence of a specific game state. Further, since the transmission / reception switching operation is not performed, noise can be eliminated in data transfer.

Since the data signal input from the sub control unit to the main control unit is prohibited by the one-way data transfer means, input of an illegal signal from the sub control unit to the main control unit via the symbol display device is prevented, It is prevented that the player is in the winning state even if the winning is not established.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a data transmission device in a pachinko machine according to an embodiment. The main control unit 1 for controlling the entire pachinko game of the pachinko machine is a main CPU 2 as a control processing executing means.
And a ROM 3 in which a control program relating to the entire pachinko game to be executed by the main CPU 2 is stored,
The RAM 4 is readable and writable at any time, and the communication interface 5 is used by the main CPU 2 to perform data communication with peripheral devices. In addition,
A power supply (not shown) for the main CPU 2 and a clock circuit (not shown) that defines a processing cycle of the main CPU 2 are connected to the main CPU 2.

The sub-control unit 6 shown in FIG. 1 is provided on the side of the symbol display device 7 shown in FIG. 2 provided in the pachinko machine,
A sub CPU 8 as a process execution means for performing display drive control of each display drive means of the symbol display device 7 according to a control signal and command data from the main control unit 1, and a sub CPU.
8, a ROM 9 in which a control program for display driving of each display driving means and a control program for data communication with the main control unit 1 are stored, a RAM 10 that can be read and written at any time, and a control signal is output. The output port 11 for doing, and the common 1 output circuit 12 to the common 4 output circuit 15 for driving the display of the special symbol display portion 17 which constitutes a part of each display driving means.
And an LED signal output circuit 16. In addition,
A power supply (not shown) for the sub CPU 8 and a clock circuit (not shown) that defines a processing cycle of the sub CPU 8 are connected to the sub CPU 8.

In FIG. 1, the sub CPU of the sub controller 6
8 is communicatively connected to the main CPU 2 via the communication interface 5 of the main control unit 1 and the one-way data transfer means 40, control signals and command data are transferred only from the main CPU 2 to the sub CPU 8, and from the sub CPU 8 to the main CPU 2. The input of the data signal is prohibited. The one-way data transfer means 40 is
For example, it is configured by a transistor array. The data transmission line is composed of 8 signal lines, and
Bit data is transmitted in parallel.

The special symbol display section 17 has 14 rows vertically and 32 rows horizontally.
The special symbol display portion 17 is composed of dot matrix LEDs arranged in rows, and the special symbol display portion 17 is further divided into left, middle and right special symbol display portions 17a, 17b and 17c. Output port 1 of sub CPU 8 in sub control unit 6
1, the common 1 output circuit 12 to the common 4 output circuit 15 and the LED signal output circuit 16 are connected, and the special symbol display unit 17 is the common 1 output circuit 12 to the common 4 output circuit 15 and the LED signal output. By connecting to the circuit 16 and switching the output of each common 1 output circuit 12 to common 4 output circuit 15 and the output of the LED signal output circuit 16 by the control output from the sub CPU 8, the left, middle and right special symbol display portions 17a , 17b, 17c
It is configured to display and drive the design.

FIG. 2 is a front view showing the game board 18 provided in the pachinko machine of the embodiment with a part thereof omitted. A symbol display device 7 provided with a special symbol display portion 17 is arranged in the approximate center of the game board surface, and below the symbol display device 7, a starting opening for starting the variation of the symbol in the special symbol display portion 17. An ordinary electric accessory 20 having 19 is provided, gates 21 and 22 are provided respectively on the left and right sides of the ordinary electric accessory 20, and an opening / closing operation is performed by a solenoid (not shown) at the bottom of the game board 18 surface. A winning device unit 24 having a special winning opening 23 is arranged.

The symbol display device 7 has a display device main body 25.
In the center of the left, middle, right special symbol display portions 17a, 17b,
The special symbol display unit 17 configured by 17c is provided, and on the upper side of the special symbol display unit 17, the special symbol memory number display for displaying up to four winning memory states in the starting opening 19 of the ordinary electric accessory 20 is displayed. LED 26 is provided, and the display device main body 2
On the upper part of 5, a normal symbol display 28 having left and right ordinary symbol display portions 27a and 27b constituted by two 7-segments is arranged, and on the upper part of the ordinary symbol display 28, to the gates 21 and 22. An ordinary symbol memory number display LED 29 for displaying the passing memory of the game ball up to 4 times is provided.

In the center of the winning device unit 24,
The movable door 30 is pivotally supported at its lower end side so that the movable door 30 is opened when the movable door 30 is moved by its solenoid with its upper end side facing forward.
A special area 31, which is a special winning area, is provided, and a large winning opening winning number display LED 32 for displaying the number of winning balls to the special winning opening 23 is provided on the right side inside the big winning opening 23. On the left side of the inside of 23, the opening number display LED for displaying the number of times the special winning opening 23 is opened by the opening operation of the movable door 30.
33 are provided.

Incidentally, the back of the ordinary electric accessory 20, the back of the special winning opening 23, the specific region 31, and the left and right gates 21 and 22.
In the back, there are provided a winning opening winning detection switch SW1, a special winning opening winning detection switch SW2, a specific area passage detecting switch SW3 and a gate passage detecting switch SW4 as winning detecting means and game ball detecting means, respectively. Further, as in the conventional case, on the surface of the game board 18, there are arranged display lamps for decoration which are normally driven to be driven according to the winning opening and the game situation, but they are not shown.

FIG. 3 is a block diagram showing the connection of each display means in the sub-control unit 8, and the sub-control unit 8 has the left, middle and right special symbol display units 17a, 17 shown in FIG.
In addition to b and 17c, through the respective display drive circuits 34 to 39, a normal symbol display 28 having left and right normal symbol display portions 27a and 27b, a normal symbol memory number display LED 29, a special winning opening winning number display LED 32, and The number-of-opening display LEDs 33 are respectively connected, and the respective display means are configured to be driven by the sub CPU 8 individually or simultaneously.

Next, an outline of the pachinko game on the surface of the game board 18 shown in FIG. 2 will be described. When the game ball wins the starting opening 19, the symbol variation of the special symbol display portion 17 of the symbol display device 7 is started. When a game ball is won in the starting opening 19, the main controller 1 of FIG. 3 stores the value of the random number for jackpot determination. The winning of the game ball to the starting opening 19 during the change of the special symbol display portion 17 is stored up to four times, and the number of the memory is displayed by the special symbol memory number display LED 26 being turned on.

The symbol variation of the special symbol display portion 17 is stopped and displayed in the order of the left special symbol display portion 17a, the right special symbol display portion 17c, and the middle special symbol display portion 17b after the symbol variation is started. The types of symbols displayed on each special symbol display portion 17a, 17c, 17b are as shown in Table 1 and Table 2, and in the main control unit 1, each special symbol display portion 17
a, 17c, 17b, each special symbol data corresponding to the symbol to be displayed is created, the left special symbol, the right special symbol, the special symbol data in which all the special symbols are the same symbol, and the left special symbol and the right symbol Reach design data that matches the special design and differs only in the middle special design, and is divided into left special design, right special design, and dislocation special design data in which all of the middle special designs are different, and each special design data is separated. I remember.

[0023]

[Table 1]

[0024]

[Table 2] The main control unit 1, each special symbol display unit 17a, 17c,
When performing the stop display of the symbol of 17b, by determining whether the value of the jackpot determination random number is for the jackpot, whether it is only for the reach, or whether it is out, Jackpot special symbol data, which is stored by dividing each special symbol data to be stopped and displayed,
Select from reach symbol data and out-of-match special symbol data. In addition, the symbol selected in the special symbol display portion 17 is displayed.

When a big hit occurs in the special symbol display portion 17, a special game state that is particularly advantageous to the player is given, and the movable door 30 of the prize display unit 24 in FIG. 2 is opened by the solenoid for a predetermined time, Big prize hole 23
Is released. When a game ball is placed in the special winning opening 23, the number of winning balls in the special winning opening 23 is displayed by the special winning opening winning number display LED 32. The winning of the game balls into the special winning opening 23 is a fixed number, for example, 10 during a predetermined opening time.
Up to the number of pieces, the movable door 30 is closed by the tenth prize, and the big winning opening 23 is closed.

During opening of the special winning opening 23, the big winning opening 2
The game ball winning 3 is the specific area 31 in the special winning opening 23.
After passing, the game ball passing to the specific area 31 is stored in the main control unit 1, and after the special winning opening 23 is closed, the special winning opening 23 is opened again for a predetermined time. This prize hole 23
The number of open times is counted by the main control unit 1 and is displayed by the open count display LED 33 as a number. In addition, the number of times of opening the special winning opening 23 is up to 16 times, and with the closing of the special winning opening 23 for the 16th time, the special game state which is particularly advantageous to the player is finished.

Further, the gates 21 and 22 of FIG. 2 are starting gates for starting symbol fluctuation of the normal symbol display 28 of the symbol display device 7, and the game ball passes through one of the gates 21 and 22. Then, the left normal symbol display unit 27 and the right normal symbol display unit 27b of the normal symbol display unit 28 start symbol fluctuation. The passage of the game ball to the gates 21 and 22 during the change of the normal symbol display 28 is stored up to four times, and the number of the memory is displayed by the normal symbol memory number display LED 29 being turned on.

The symbol fluctuation of the normal symbol display unit 28 is stopped and displayed in the order of the left normal symbol display section 27a and the right normal symbol display section 27b after the start of the symbol fluctuation. Each normal symbol display section 27
The types of symbols displayed on a and 27b are as shown in Table 3.

[0029]

[Table 3] When the left normal symbol and the right special symbol stopped and displayed in the normal symbol display 28 become the same symbol, the winning symbol is won, the starting opening 19 of the ordinary electric accessory 20 is driven to open for a predetermined time, and a game ball to the starting opening 19 The winning probability of is increased.

Each data relating to the pachinko game on the game board 18 is individually stored in the main control unit 1, and the main control unit 1 as shown in FIG. 1 and FIG.
Control signals and command data are transferred to the sub-control unit 6 according to each data. The sub controller 6 is the main controller 1
It receives the control signal and command data from, and drives the respective display means to display according to the control signal and the command data.

Next, the transfer of command data from the main controller 1 to the sub controller 6 will be described. As shown in FIG. 4, the command data sent from the main control unit 1 to the sub control unit 6 consists of 12 COM1 to COM12 as a whole, and each COM1 to COM12 has a size of 1 byte (8 bits). That is, the total command data is 12 bytes.

From the main control unit 1 to the sub control unit 6, as shown in Table 4, command data having a size of 12 bytes as a whole are COM1 to COM3 and COM4 to C.
OM6, COM7 to COM9, COM10 to COM12
In this order, 3 bytes are divided into 4 times and transferred.

[0033]

[Table 4] FIG. 5 shows the transfer format of each time, and the size of the transfer data transferred at one time is 4 bytes. In the first byte of the transfer data of each time, for example,
A header indicating the transfer order is added as in the second time, and 3 bytes of the divided command data transferred each time are added to the last 3 bytes of the transfer data.

Next, the contents of each of COM1 to COM12 will be sequentially described. Since the contents of COM1 are as shown in Table 5, a detailed description thereof will be omitted, but the normal reach shown in Table 1 is a mode in which a big hit occurs at a normal probability, and the super reach has a slightly higher probability than a normal reach. The special reach is a mode in which a big hit occurs with a higher probability than the super reach. COM1 is mainly flags and status data indicating the gaming state of the pachinko machine.

[0035]

[Table 5] In COM2, 7 bits to 4 bits are numerical data representing the number of times the special winning opening 23 is opened, and 3 bits to 0 bits are numerical data representing the number of winnings to the special winning opening 23.

In COM3, 7 bits to 4 bits are numerical data representing the number of memories relating to normal symbols, and 3 bits to.
0 bit is numerical data representing the number of memories related to special symbols.

COM4 is the symbol data (0
~ 13), and COM5 is numerical data representing the display position data (0 to 29) of the left special symbol. Also, COM6 is the stop data (0
Numerical data representing 5).

COM7 is the symbol data (0
~ 13), and COM8 is numerical data representing the display position data (0 to 29) of the right special symbol. Also, COM9 is the stop data (0
Numerical data representing 5).

COM10 is numerical data representing the symbol data (0 to 14) of the medium special symbol, and COM11 is
It is numerical data representing the display position data (0 to 29) of the medium special symbol.

COM12 is checksum data for data check for checking the entire transferred command data against the command data before transfer.
It is addition data obtained by adding M1 to COM11.

FIG. 6 shows the main controller 1 to the sub controller 6
7 is a timing chart showing the transfer timing of command data to the sub-control unit 6 divided into 4 by 3 bytes every 2 ms from the main control unit 1 to the sub-control unit 6.

FIG. 7 is a timing chart showing the transfer timing of the divided command data from the main control unit 1 to the sub control unit 6 at each time. The operation of the main controller 1 in FIG. 1 will be described. First, the main CPU 2 outputs an interrupt signal to the sub CPU 8 via the communication interface 5 and the one-way data transfer means 40. When the interrupt signal is input to the sub CPU 8, the sub CPU 8 temporarily suspends the display drive process of the special symbol display unit 17, and shifts to the process of inputting command data from the main control unit 1 side.

At the same time as the interrupt signal, the main CPU 2
As shown in FIG. 7, the CE signal (chip select) is set to the low level and the divided command data for one time is transferred. That is, the transfer data as shown in FIG. 5 is serially transferred in the order of the header, COM1, COM2, and COM3, and in parallel with the divided command data to be serially transferred, the WR corresponding to the header is provided at intervals of 30 μs.
A signal (write signal) is output for 25 μs, then 3
The WR signal is output for 25 μs corresponding to COM1 at an interval of 0 μs, and again at an interval of 30 μs, C
The WR signal is output for 25 μs corresponding to OM2, and the WR signal is output for 25 μs corresponding to COM3 at intervals of 30 μs.

2 ms after the end of the first transfer of the divided command data, the second transfer of the divided command data is performed in the same manner as described above, and the divided command data of COM4 to COM6 is transferred from the main control unit 1. 2 ms after the transfer of the second division command data to the sub control unit 6 is completed, the division command data from COM7 to COM9 is transferred from the main control unit 1 to the sub control unit 6
2 ms after the transfer of the third divided command data is completed, the divided command data of COM10 to COM12 is transferred from the main control unit 1 to the sub control unit 6, and the transfer of the entire command data is completed. Will be done.

Next, the command data division transfer processing by the main CPU 2 in the main control unit 1 will be described with reference to the flow charts of FIGS. 8 to 13, which are part of the control program stored in the ROM 3. The main CPU 2 repeats the divided transfer processing in a predetermined processing cycle substantially in parallel with each processing related to a pachinko game (not shown).

When the main CPU 2 starts the divided transfer processing, first, the value of the processing time setting timer Tm for setting the processing cycle of 1 ms which is the basic cycle of the divided transfer processing as shown in the timing chart of FIG. It is determined whether or not is 0 (step a1). Since the value of the processing time setting timer Tm is 0 due to the initialization processing (not shown) immediately after the power is turned on, the main CPU 2 shifts to step a2.

Main CPU 2 which has moved to step a2
Then, it is determined whether or not the value of the processing flag F1 related to the divided transfer processing is 0, which defines unprocessed (step a2). Similarly to the above, the value of the processing flag F1 is also 0 due to the initialization processing immediately after the power is turned on, so the main CPU 2 shifts to step a3.

When the process proceeds to step a3, the main CPU 2 first sets the process flag F1 to 1 and stores the start of the divided transfer process (step a3), and the initial start of a new divided transfer process of steps a4 to a6. Move on to processing for condition set.

At step a4, the main CPU 2
6 clears the value of the number counter C1 which counts the number of times of transfer of command data divided, for example, the first time, the second time ... As shown in FIG.
4) Next, the checksum register chR that is used additively for calculating the checksum is cleared to 0 (step a5), and then each command, that is, COM1 to CO
The initial value 1 is set in the index register i used as the index of M12 (step a6), and the process shifts to the initial condition setting at each time of steps a7 to a14.

When the main CPU 2 proceeds to step a7, first, the initial condition setting identification flag F2 is set to 1 and the start of processing of initial condition setting in each data transfer shown in FIG. 7 is stored. Next, the main CPU 2 sets the interrupt signal output flag (step a8), and CE
The signal output flag is set (step a9), the WR signal output flag is cleared (step a10), and step a
Go to 11.

At step a11, the main CPU 2
Indicates that the WR signal switching timer WRT in which the switching timing time (30 μs and 25 μs) of the WR signal shown in the timing chart of FIG.
Set the signal off time of 30 μs (step a
11), the process proceeds to step a12.

Upon proceeding to step a12, the main CPU 2 sets a header (a value representing the first time in this case) corresponding to the divided command data to be transferred this time in the output buffer OUT having a size of 1 byte ( Step a1
2), an initial value 1 is set in a set number counter C2 that counts the number of times the data set in the output buffer OUT is set within the time of 250 μs shown in the timing chart of FIG. 7 (step a13), and the timing chart of FIG. The output completion flag that is set at the time of switching the ON signal of the WR signal to the OFF signal that is output in the fourth time is cleared (step a14), and the process for setting the initial condition in each time is finished and step a1
Go to 5.

At step a15, output processing is performed, and the interrupt signal C and C set at steps a8, a9, a10 and a12, respectively.
The OFF signal of the E signal and the WR signal and the value of the output buffer OUT are output from the output port (not shown) of the main CPU 2, and these control signals and transfer data are transmitted via the communication interface 5 and the one-way data transfer means 40. Is input to an input port (not shown) of the sub CPU 8. As a result, when the interrupt signal is input, the sub CPU 8 suspends the display driving process for each display unit shown in FIG. 3 and shifts to the input process of the data transferred from the main CPU 2.

After the processing of step a15, the main CPU 2
Moves to step a16 and performs timer subtraction processing.
In the timer subtraction processing, each value is decremented by 1 only when the processing time setting timer Tm and the WR signal switching timer WRT are not 0. Main CP
After finishing the processing of step a16, the U2 finishes the divided transfer processing of this cycle. Note that the main CPU 2 thereafter shifts to each process related to the pachinko game.

In the division transfer processing of the next cycle, the value of the processing time setting timer Tm remains 0, and the processing flag F
As a result of the value of 1 being 1, the main CPU 2 shifts to step a17 after determining steps a1 and a2, and determines whether the value of the initial condition setting identification flag F2 is 0 or not. As a result of the initial condition setting identification flag F2 being set to 1 by the process of step a7 of the cycle, the main CPU 2 determines that it is false, and proceeds to step a18.

When the main CPU 2 proceeds to step a18, it clears the interrupt signal output flag (step a
18) Then, the process proceeds to step a19, it is determined whether or not the value of the WR signal switching timer WRT is 0, and W
Immediately after the R signal switching timer WRT has been set, it is determined to be false, the output of the interrupt signal is turned off by performing the output processing of step a15, the process proceeds to step a16, and the timer subtraction processing is performed. The division transfer processing is completed.

In the processing of the next cycle and thereafter, the main CP
U2 waits until the off time (30 μs) of the WR signal set in the WR signal switching timer WRT elapses.
The output processing of step a1, step a2, step a17, step a18, step a19 and step a15 and the timer subtraction processing of step a16 (hereinafter referred to as processing loop A) are repeated in a processing cycle.

The off time of the WR signal (30 μs)
Is passed, the value of the WR signal switching timer WRT becomes 0.
Then, the main CPU 2 determines that the step a19 is true, then proceeds to the step a20, and determines whether or not the WR signal output flag is set. At the time when the off time (30 μs) of the WR signal has elapsed, the main CPU 2 shifts to step a21 because the WR signal output flag is cleared in step a10.

Next, the main CPU 2 determines whether or not the output completion flag is set (step a).
21), since the output completion flag has been cleared in step a14, it is determined to be false, and the process proceeds to step a22. The main CPU 2 sets the WR signal output flag (step a22), then sets the WR signal on-time (25 μs) in the WR signal switching timer WRT (step a23), and performs the output processing of step a15 and the timer of step a16. Subtraction processing is performed, and the division transfer processing of this cycle is completed.

As a result of the output processing in step a15, the WR signal regarding the header is input to the sub CPU 8, and the sub CPU 8 reads the header.

In the processing of the next period and thereafter, as shown in the timing chart of FIG.
The processing loop A is repeated at the processing cycle until the ON time of the signal (25 μs) elapses.

The on-time of the WR signal (25 μs)
Is passed, the value of the WR signal switching timer WRT becomes 0.
Then, the main CPU 2 determines, after the determination in step a19,
The process proceeds to step a20, and it is determined whether or not the WR signal output flag is set.

At the time when the ON time (25 μs) of the WR signal has elapsed, the WR signal output flag is set in step a22, so the main CPU 2 executes step a.
24, the WR signal output flag is cleared (step a24), then the WR signal switching timer WRT is set to the off time (30 μs) of the WR signal again (step a25), and the process proceeds to step a26.

When the main CPU 2 proceeds to step a26, it determines whether or not the data set number counter C2 has reached 4, but it is determined to be false because the current value of the set number counter C2 is 1 (step a26). ), Then the value of index register i for COM is 11
However, since the value of the index register i is the initial value 1, it is determined to be false (step a2).
7), and proceeds to step a28.

At step a28, the COM corresponding to the current value of the index register i is output buffer OU.
Set to T. That is, in this case, since the value of the index register i is 1, the output buffer OUT
COM (1) is set to (step a28). Then, in step a29, the checksum register c
The value of COM (i) is additionally stored in hR (step a2).
9). In this case, checksum register chR
The value of COM (1) is added to and stored.

Then, the main CPU 2 increments the current value of the index register i by 1 (step a3).
0) and COM (i) are set in the output buffer OUT, the value (current value 1) of the set number counter C2 is incremented by 1 (step a31), the output process of step a15 and the timer of step a16 are performed. Subtraction processing is performed, and the division transfer processing of this cycle is completed. As a result of performing the processing of step a24 and step a28 and the output processing of step a15,
At the same time when the output of the WR signal is turned off, the content of the transfer data is switched from the header to COM1.

Up to this point, the output operation processing has been performed for one piece of data having a size of 1 byte at the transfer timing of the divided command data from the main controller 1 to the sub controller 6 at each time in FIG.

After the next cycle, the main CPU 2 executes the above-mentioned processing loop A according to the off time and the on time of the WR signal which are alternately set in the WR signal switching timer WRT.
Processing, step a1, step a2, step a
17 to step a20, step a21 to step a23, step a15 and step a16, and step a1 and step a2, step a17 to step a20, step a24 to step a2.
7, step a28 to step a31, step a1
5 and each processing of step a16 are sequentially and repeatedly executed, and the value of the index register i is incremented, and according to the value, as shown in FIG.
(2) and COM (3) are sequentially output, and each COM is sequentially added and stored in the checksum register chR. Therefore, the sub CPU 8 sequentially reads COM (1), COM (2), and COM (3).

Then, in FIG. 7, at the time of turning on / off the output of the WR signal for the fourth time regarding COM (3), the main CPU 2 makes the step a24 in FIG.
Clears the WR signal output flag (step a2
4) Set the WR signal switching timer WRT to the off time (30 μs) of the WR signal again (step a25),
Next, when the current value of the set number counter C2 has reached 4, it is determined to be true (step a26), the process proceeds to step a32, the output buffer OUT is cleared (step a32), and the output completion flag is set ( Step a33), output process of step a15 and step a33
The timer subtraction process of 16 is performed, and the divided transfer process of the current cycle ends. As a result of the output processing in step a15, the output of the WR signal is turned off and the data output is turned off.

Then, after the next cycle, the main CPU 2
The processing loop A is repeated until the off time set in the WR signal switching timer WRT elapses, and when the off time (30 μs) of the WR signal elapses, the main CPU 2
Is determined to be true by the output completion flag being set in the determination processing of step a21 after the determination of steps a19 and a20, and the process proceeds to step a34.

When the main CPU 2 shifts to step a34, the main CPU 2 sets the processing time setting timer Tm to the next value shown in FIG.
The interval time until the start of the second division transfer process is set to 1 ms (step a34), the CE signal output flag is cleared (step a35), and the number of times counter C1 is set.
Is incremented by 1 (step a36), and it is determined whether the value of the number-of-times counter C1 has reached four times, that is, whether the transfer of the entire command data has ended.
At the time when the second time is completed, the value of the frequency counter C1 is 1, so it is determined to be false and the initial condition setting identification flag F2 is set to 0.
It is cleared (step a38), the output process of step a15 and the timer subtraction process of step a16 are performed, and the divided transfer process of this cycle is completed. As a result of the output processing in step a15, the output of the CE signal is turned off. At this point, 1 in the timing chart of FIG.
The data division transfer process for the second time is completed.

In the processing of the next period and thereafter, the value of the processing flag F1 remains 1, and the value of the processing time setting timer Tm is not 0. Therefore, the main CPU 2 executes the step a1.
It is determined that the determination process of No. is false, only the timer subtraction process of step a16 is performed, and the divided transfer process is finished.

When the set time (1 ms) elapses, the value of the processing time setting timer Tm becomes 0 by the timer subtraction processing in step a16, so the main CPU 2
After the processing of step a1 and step a2, step a17
As a result of the initial condition setting identification flag F2 being cleared to 0, step a17 is determined to be true and step a
After shifting to No. 7 and setting 1 to the initial condition setting identification flag F2, steps a8 to a16 are sequentially executed to start the second data division transfer process in the timing chart of FIG. In step a12, the value corresponding to the second transfer of the divided command data is set in the output buffer OUT.

Thereafter, the main CPU 2 will sequentially perform the divided transfer processing of the data from the second time to the fourth time in the timing chart of FIG. 6 every 1 ms by the above-mentioned algorithm.

Then, in the fourth data division transfer process, when the division command COM (12) as the checksum data is set in the output buffer OUT, the step value of the index register i is 11. The main CPU 2 determines that the determination processing in step a27 is true, moves to step a39, and sets the cumulative addition value of COM1 to COM11 stored in the checksum register chR in the output buffer OUT (step a39). After the processing of steps a30 and a31, the output processing of step a15 and the timer subtraction processing of step a16 are performed, and the division transfer processing of the cycle is completed.

As a result of the output processing in step a15, a checksum for checking the data of COM1 to COM11 is output as COM (12) and input to the sub CPU 8. Further, the sub CPU 8 performs a data check of the entire command data by determining whether the checksum and the received cumulative addition value of COM1 to COM11 match or not match.

After that, at the time when the data division transfer processing in the fourth data division transfer processing is completed,
After clearing the CE signal output flag (step a3
5) The value of the frequency counter C1 is incremented by 1 (step a36), and it is determined whether or not the value of the frequency counter C1 has reached four times, that is, whether or not the transfer of the entire command data has been completed. When the fourth time is completed, the value of the number counter C1 is 4, so that it is determined to be true, and the value of the processing flag F1 is cleared to 0 to store the completion of the transfer of the entire command data (step a40). The initial condition setting identification flag F2 is cleared to 0 (step a38),
The output process of step a15 and the timer subtraction process of step a16 are performed, and the division transfer process of the current cycle is completed.
It should be noted that in the processing of the next cycle and thereafter, the newly created next command data is transferred.

Next, with reference to the flow charts of FIGS. 14 to 17, which are part of the control program stored in the ROM 9, the input processing of divided command data and the data check processing by the sub CPU 8 in the sub control unit 6 will be described. .

FIG. 14 is a flow chart showing the outline of the main routine of the control program stored in the ROM 9. After the power is turned on, the sub CPU 8 performs initialization processing (step B1) to initialize the flags, registers, and storage areas required for each processing.

When the initialization processing is completed, the sub CPU 8
It is determined whether or not an interrupt signal from the main control unit 1 as shown in FIG. 1 is input (step B2), and when the interrupt signal is not input, each display means, that is, FIG.
Left, middle, right special symbol display portions 17a to 17c, open count display LED 33, special winning opening prize display LED 32,
Special symbol memory number display LED26, normal symbol memory number display L
The commands transferred from the main control unit 1 that are updated and stored in the fixed command data storage areas KCOM (1) to KCOM (11) for each display drive process of step B3 relating to the ED 29 and the left and right normal symbol display units 27a and 27b. According to the contents of the data COM1 to COM11, the processes are repeated substantially in parallel at a predetermined processing cycle.

On the other hand, as shown in FIG. 1, the sub CPU 8 suspends each display drive process when an interrupt signal is input from the main control unit 1 and divides the divided command transferred from the main control unit 1. The command receiving process of step B4 for receiving data is performed.

The command receiving process of step B4 will be described below with reference to the flow charts of FIGS. The command reception process is started when an interrupt signal is input from the main control unit 1. First, the sub CPU
By reading the state of the input port (not shown), 8 determines whether or not the CE signal and the WR signal are input.

At step b1, it is judged whether or not the CE signal is input. Since the CE signal is output from the main CPU 2 at the same time as the interrupt signal, the determination processing in step b1 is determined to be true, and the sub CPU 8 determines in step b2.
Move to

At step b2, it is judged if the WR signal is the OFF input. As shown in the timing chart of FIG. 7, since the WR signal is off at the time of outputting the CE signal, the determination processing in step b2 is determined to be true, and the sub CPU 8 proceeds to step b3.

At step b3, it is judged if the falling edge of the WR signal as shown in FIG. 7 is detected. After detecting the off output of the WR signal, the sub CPU 8
It repeatedly determines whether or not there is a signal ON output,
When the output of the WR signal changes from off to on, step b
Since the determination process of 3 becomes true and the falling edge of the WR signal is detected, the sub CPU 8 proceeds to step b4.

At step b4, the main CPU 2
The 8-bit parallel output data output from the sub CPU 8 is read from the input port of the sub CPU 8 and stored in the input buffer INDAT having a size of 1 byte set in the RAM 10. That is, when the falling edge of the WR signal is detected, the output data (1 byte) output from the main CPU 2 is input to the sub CPU 8 side. Sub CP
U8 performs the process of step b4 and then executes step b5.
Then, the process proceeds to the header determination process of step b8.

The main C that is first input after the command reception process is started by the input of the interrupt signal
The output data from the PU 2 is a header representing the first time in the divided transfer of command data, as shown in FIGS. 5 and 7.

First, at step b5, it is judged if the data read into the input buffer INDAT is the first header. If the data read into the input buffer INDAT is the first header, the sub CPU
8 clears the checksum register CHR for cumulatively adding and storing each input divided command data for checking the error of the entire input command data (step b9).

Next, the sub CPU 8 inputs the 12 pieces of divided command data COM1 to COM1 shown in FIG.
COM (1) to C set in the RAM 10 corresponding to 2
The input buffer INDA is provided in each storage area of the OM (12).
An initial value of 1 is set in the index register j used to transfer the data read into T (step b
10).

Next, the sub CPU 8 is, for example, the first time, the second time, ... As shown in the timing chart of FIG.
In this way, the initial value 1 defining the first time is set to the reception number counter C3 that counts the number of times the reception process is performed (step b11), and the data input counter C4 that counts the number of times the divided command data is read each time.
Is set to 0 (step b12), and COM corresponding to 12 pieces of divided command data COM1 to COM12 is set.
All the storage areas of (1) to COM (12) are cleared (step b13), the process returns to step b2, and step b
The process of detecting the falling edge of the WR signal in step 2 and step b3 is performed.

As shown in FIG. 7, the output of the WR signal is 2
Since the output is on for 5 μs, the sub CPU8
Repeatedly determines that the determination process of step b2 is false.
Then, when the output of the WR signal changes from on to off, the determination result of step b2 becomes true, and the sub CPU 8 proceeds to step b3. Further, since the output of the WR signal is OFF output for 30 μs from the time when the output of the WR signal changes from ON to OFF, the sub CPU 8 executes the step b.
The determination process of 3 is repeatedly determined to be false. Then, when the output of the WR signal changes from OFF to ON, the determination processing in step b3 becomes true, and the trailing edge of the WR signal is detected,
The sub CPU 8 shifts to step b4, and the 8-bit parallel output data output from the main CPU 2 is again read into the input buffer INDAT.

Since the first input data from the main CPU 2 from the time when the first header is detected is COM1 of the divided command data as shown in FIGS. 5 and 7, the input buffer INDAT is set. Is C
OM1 will be read.

After executing the processing of step b4, the sub CPU 8 shifts to step b5, where the input buffer IN
Since the data read in the DAT is not the header for the first time, it is determined to be false, and the process proceeds to step b6. Step b
In 6, it is determined whether or not the data read into the input buffer INDAT is the header for the second time. Similarly, it is determined to be false and the process proceeds to step b7. Further, in step b7, it is determined whether or not the data read into the input buffer INDAT is the third header, but similarly, it is determined to be false and the process proceeds to step b8. Furthermore, in step b8, the input buffer INDAT
It is determined whether or not the data read in is the fourth header, and similarly it is determined to be false and the process proceeds to step b14. That is, when the data read into the input buffer INDAT is the split command data, the sub CPU 8 moves to step b14.

At step b14, the data read into the input buffer INDAT is transferred to and stored in the data storage area COM (j) designated by the value of the index register j. For example, in this case, j
= 1, the divided command data COM1 read into the input buffer INDAT is stored in the data storage area C.
It is transferred to OM (1) and stored.

Next, the sub CPU 8 carries out step b15.
The value of the index register j is incremented by 1 (step b15), and the value of the index register j is changed to 1.
It is determined whether it has reached 2 (step b16).
The third time from the time when the fourth header is detected, that is,
The last output data from the main CPU 2 is
As shown in FIGS. 5 and 7, since the command data is checksum data as a whole, the determination process of step b16 is a process for detecting checksum data. At this point, the value of the index register j is 12
Therefore, the sub CPU 8 shifts to the step b17 after the discrimination processing of the step b16.

At step b17, the value stored in the checksum register CHR is set to the input buffer IN.
The data read into DAT is cumulatively added and stored (step b17). For example, in this case, the value of the divided command data COM1 read into the input buffer INDAT is added to the value 0 stored in the checksum register CHR, and the addition result is stored in the checksum register CHR.

After the processing of step b17, the sub CPU 8 increments the value of the data input counter C4 by 1 (step b18), and determines whether or not the value of the data input counter C4 has reached the data input count 3 of each time. (Step b19).

Since the value of the data input counter C4 is 1 when the divided command data COM1 is stored in the data storage area COM (1), the sub CP
U8 determines that the determination process of step b19 is false, and returns to step b2.

Thereafter, when the sub CPU 8 detects the falling edge of the WR signal by the same algorithm as described above,
The divided command data output from the main CPU 2 is read into the input buffer INDAT, the divided command data COM is stored in the storage area COMj designated by the value of the stepped index register j, and the input divided command data COM value is also stored. Is cumulatively added to the checksum register CHR. That is, the respective values of the divided command data of COM2 to COM3 output from the main CPU 2 are sequentially stored in the respective storage areas of COM (2) to COM (3), and the respective values of the divided command data of COM2 to COM3 are sequentially stored. Checksum register CHR
Cumulatively add to.

Then, the divided command data COM3 is stored in the storage area COM (3), and the divided command data C
When OM3 is cumulatively added to the checksum register CHR and the value of the data input counter C4 is incremented by 1 (step b18), the value of the data input counter C4 reaches the number of times of data input 3 each time, and the sub CPU 8 executes the operation of step b19. The determination process is determined to be true, and the process proceeds to the data check process after step c1.

At step c1, it is judged if the value of the reception number counter C3 has reached the number of receptions of the entire command data, which is 4 times. Since the value of the reception number counter C3 is 1 when the divided command data of COM1 to COM3 is received, the sub CPU 8 determines that the determination process of step c1 is false, and returns to the main routine to return to the step of FIG. The process proceeds to each display drive process of B3. Therefore, the process for the substantial data check is not performed.

The processing up to this point is the reception processing of the sub CPU 8 regarding the first transfer of the divided command data in the timing chart of FIG. After that, when the interrupt signal from the main CPU 2 is input again, the receiving process of the sub CPU 8 regarding the second transfer of the divided command data is started.

In the receiving process of the sub CPU 8 regarding the transfer of the second divided command data, the output data from the main CPU 2 which is first input is, as shown in FIG. 5 and FIG. 7, the second output in the divided transfer of the command data. Is a header that represents.

The second header is read into the input buffer INDAT, and the sub CPU 8 determines that the determination processing of step b5 is false after the processing of step b4 and the determination processing of step b6 is true, Step b
Move to 20.

Sub CPU 8 having moved to step b20
Sets the initial value 4 in the second transfer of the divided command data to the index register j (step b2
0), then the value of the reception counter C3 is incremented by 1 (step b21), and the data input counter C
4 is set to 0 (step b22), and the process returns to step b2.

Thereafter, the sub CPU 8 outputs the COM output from the main CPU 2 by the same algorithm as described above.
COM to each value of the divided command data of 4 to COM6.
(4) to COM (6) are sequentially stored in each storage area, and each value of the COM4 to COM6 divided command data is sequentially cumulatively added to the checksum register CHR,
The command receiving process for the second transfer of the divided command data is completed, and the process returns to the main routine.

Similarly, every time an interrupt signal is input from the main CPU 2, the command receiving process regarding the third and fourth transfer of the divided command data is started.

In the receiving process of the sub CPU 8 relating to the transfer of the third divided command data, the output data from the main CPU 2 which is first input is as shown in FIGS. 5 and 7 in the divided transfer of the command data. This is a header representing the third time. When the third header is read into the input buffer INDAT, the sub CPU 8 makes a determination at step b7 after the determination at step b5 and step b6.
Is determined to be true and 3 is stored in the index register j.
The initial value 7 in the transfer of the divided command data for the second time is set (step b23), and after the processes of steps b21 and b22, the process returns to step b2.

Thereafter, by the same algorithm as described above, the respective values of the division command data of COM7 to COM9 are sequentially stored in the respective storage areas of COM (7) to COM (9), and the division commands of COM7 to COM9 are stored. Each value of the data is sequentially accumulated in the checksum register CHR.

Further, in the receiving process of the sub CPU 8 regarding the transfer of the fourth divided command data, when the header of the fourth time is read into the input buffer INDAT, the sub CPU 8 determines after the determination of step b5, step b6 and step b7. When the determination processing in step b8 is determined to be true, the initial value 10 in the fourth transfer of the divided command data is set in the index register j (step b
24), after the processing of step b21 and step b22,
Return to step b2.

Thereafter, by the same algorithm as described above, the respective values of the divided command data of COM10 to COM11 are sequentially stored in the respective storage areas of COM (10) to COM (11), and at the same time COM10 to COM11.
Each value of the divided command data is sequentially accumulated in the checksum register CHR. Then, when COM12 which is the checksum data is stored in COM (12) (step b14), the value of the index register j is incremented to 12 by the processing of step b15, and the determination result of step b16 becomes true, The sub CPU 8 proceeds to step b18 without performing the addition processing of step b17, determines the determination processing of step b19 to be true, and proceeds to step c1. Therefore, the checksum register C
Each value of the divided command data of COM1 to COM11 is cumulatively added and stored in the HR.

As shown in the flow chart of FIG. 16, when the first header is detected, the reception number counter C3 is set to the initial value 1, and thereafter, each time the header is detected, the reception number is Since the value of the counter C3 is incremented by 1, the value of the reception counter C3 has reached 4 at the time when the fourth header is detected.

The sub CPU 8 determines that the determination processing of step c1 is true, shifts to step c2, and COM1 to COM11 stored in the checksum register CHR.
It is determined whether or not the cumulative addition value of the divided command data of (3) matches the value of COM12 stored in COM (12).

The COM 12 is used as a data check for the entire command data before transfer and is used by the main CPU 2
Is the value obtained as the cumulative addition value of the divided command data COM1 to COM11. Therefore, when the data transfer of the entire command data shown in the timing chart of FIG. 6 is normally performed, the cumulative addition value stored in the checksum register CHR on the sub CPU 8 side is COM (1
It matches the value of COM12 stored in 2).

In this case, the sub CPU 8 shifts to step c3 after the determination of step c2, and moves to each storage area C.
Main C stored in OM (1) to COM (11)
The divided command data from COM1 to COM11 transferred from the PU2 side, that is, the entire command data determined to be normal, is stored in the definite command data storage area K.
Transfer to COM (1) to KCOM (11) (step c
3) Return to the main routine. In the main routine, each display drive process is performed based on the contents of the command data stored in the newly updated and stored fixed command data storage areas KCOM (1) to KCOM (11).

When the data transfer of the entire command data is not normally performed, for example, when noise is mixed in the transferred command data due to the influence of noise, the sub CPU 8 side checks. The cumulative addition value stored in the sum register CHR is COM (1
The value of COM12 stored in 2) does not match.

In this case, the sub CPU 8 shifts to step c4 after determining in step c2, and each storage area C
All of OM (1) to COM (11) are cleared (step c4), and the process returns to the main routine. Therefore, COM1 to COM transferred from the main CPU 2 side stored in each of the storage areas COM (1) to COM (11)
The divided command data for which it is determined that the abnormalities up to 11 have occurred are discarded. In the main routine,
Confirmed command data storage area KC already stored
Each display drive process is performed based on the content of the previous command data stored in OM (1) to KCOM (11). Therefore, even if noise is mixed in the transferred command data due to the influence of noise, for example, in the symbol display unit, although the random number that establishes the big hit is extracted in the main control unit. There will be no trouble such as the display of a detached pattern.

As described above, the command data is transferred from the main control unit 1 to the sub control unit 6 via the one-way data transfer means 40. As described above, the command data transfer processing is as follows. The output direction of the control signal and the data is only one direction from the main CPU 2 to the sub CPU 8, and the READY signal is not output from the sub CPU 8 to the main CPU 2. Therefore, the processing in the data transfer process on the main control unit 1 side is performed. In time, it is not necessary to set the waiting time until the input of the READY signal transmitted from the sub control unit 6 is detected,
Therefore, the command data can be transferred smoothly, and thus the display operation of the symbol display device 7 is realized without delaying the occurrence of a specific game state.

Further, since the main control section 1 is always on the transmission side and the sub control section 6 is always on the reception side, the switching operation of transmission / reception is not performed, so that noise can be eliminated.

Further, from the sub control unit 6 to the main control unit 1
Since the data signal input to the sub-control unit 6 is prohibited, even if an illegal signal is output from the sub-control unit 6 to the main control unit 1 via the symbol display device 7 by some means, the sub-control unit 6 outputs the illegal signal. It is possible to prevent an illegal signal from being input to the main control unit 1, and thus it is possible to prevent the winning state from being established even if the winning is not established.

Further, as is apparent from the above description,
Only when the entire command data transferred from the main CPU 2 side is received by the sub CPU 8 side and the data check processing determines that the command data is normal, the entire received command data is determined command data and Since the display drive processing is performed by the fixed command data, the display drive processing is always performed based on the normal command data even if noise is mixed in the transferred command data due to the influence of noise. Will be done.

Further, from the main CPU 2 side to the sub CPU 8
Since the whole command data to be transferred to each side is divided into four and each divided command data is transferred by time division, compared to the case where the whole command data is transferred all at once, from the main CPU 2 side to the sub CPU 8 Since the connection time for data transfer to the side is short by being divided into quarters, it is less susceptible to noise and the entire command data can be transferred more reliably.

Even if the display drive time of the symbol display device 7 is long, the time required for one data transfer is short, so the processing time required for the display drive process on the sub CPU 8 side is the data on the main CPU 2 side. It can be avoided that it becomes longer than the output timing processing cycle, and this will prevent the transmission and reception timing from deviating, causing flicker on the symbol display part and distorting the display. Various problems such as doing are solved.

The unidirectional data transfer means 40 uses a programmable peripheral interface (PPI) in place of the transistor array, sets the PPI in one direction for output, that is, sets the main controller 1 side as an input, and Control unit 6
The side may be set to output.

Further, in the embodiment, the sub control unit 6
Is a display unit 1 composed of dot matrix LEDs
7 has been described as an example of display drive control, but instead of the display unit 17 configured by dot matrix LEDs,
The liquid crystal display screen of the liquid crystal display device including the character ROM, the video RAM, and the VDP (video display processor) may be display driven and controlled.

[0126]

According to the data transmission device for a pachinko machine of the present invention, command data is transferred only from the main control unit to the sub-control unit, so that there is no waiting during the processing time in the data transfer process on the main control unit side. It is not necessary to set the time, so that the data transfer can be smoothly performed, and as a result, the display operation of the symbol display device can be realized without delaying the occurrence of a specific game state.

Further, the main control section is always the transmitting side,
Since the sub-control unit is always on the receiving side, the transmission / reception switching operation is not performed, so that noise can be eliminated.

Further, since the data signal input from the sub control unit to the main control unit is prohibited, an illegal signal is output from the sub control unit to the main control unit via the symbol display device by some means. Even in this case, it is possible to prevent an unauthorized signal from being input from the sub-control unit to the main control unit, and thus it is possible to prevent the winning state from being established even if the winning is not established.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing a part of a data transmission device in a pachinko machine according to an embodiment of the present invention.

FIG. 2 is a schematic front view of the game board provided in the pachinko machine of the embodiment.

FIG. 3 is a block diagram showing the connection of each display unit in the sub control unit.

FIG. 4 is a diagram showing a configuration of command data sent from a main control unit to a sub control unit.

FIG. 5 is a diagram showing a configuration of transfer data sent from a main control unit to a sub control unit at each time.

FIG. 6 is a timing chart showing transfer timing of command data from the main control unit to the sub control unit by time division.

FIG. 7 is a timing chart showing the transfer timing of divided command data from the main control unit to the sub control unit at each time.

FIG. 8 is a flowchart showing a part of a data division transfer process performed by a main CPU in a main control unit.

FIG. 9 is a continuation of the flowchart of FIG.

FIG. 10 is a continuation of the flowchart of FIG.

FIG. 11 is a continuation of the flowchart of FIG.

FIG. 12 is a continuation of the flowchart of FIG. 11.

FIG. 13 is a continuation of the flowchart of FIG.

FIG. 14 is a flowchart schematically showing a main routine executed by a sub CPU in a sub control unit.

FIG. 15 is a flowchart showing a part of a command reception process executed by the sub CPU in the sub control unit.

FIG. 16 is a continuation of the flowchart of FIG.

FIG. 17 is a continuation of the flowchart of FIG.

FIG. 18 is a timing chart showing the transfer of command data from the conventional main control unit to the sub control unit.

[Explanation of symbols]

 1 Main Control Unit 2 Main CPU 3 ROM 4 RAM 5 Communication Interface 6 Sub Control Unit 7 Symbol Display Device 8 Sub CPU 9 ROM 10 RAM 11 Output Port 12 Common 1 Output Circuit 13 Common 2 Output Circuit 14 Common 3 Output Circuit 15 Common 4 Output circuit 16 LED signal output circuit 17 Special symbol display section 17a Left special symbol display section 17b Medium special symbol display section 17c Right special symbol display section 18 Game board 19 Starting port 20 Ordinary electric auditors 21 Gate 22 Gate 23 Big winning hole 24 Prize device unit 25 Display device body 26 Special symbol memory number display LED 27a Left ordinary symbol display part 27b Right ordinary symbol display part 28 Regular symbol display 29 Normal symbol memory number display LED 30 Movable door 31 Specific area 32 Large winning award number of prizes Display LED 33 Opening count display LED 3 Display drive circuit 35 display drive circuit 36 display driver 37 display driver 38 display driver 39 display driver 40 the unidirectional data transfer means

Claims (1)

[Claims] 1. A main control unit for performing control relating to the entire pachinko game of a pachinko machine, and a symbol display device provided in the pachinko machine, and the control unit from the main control unit according to the control signal. A sub-control unit for controlling display drive of the symbol display device, and intervening between the main control unit and the sub-control unit, and enables transfer of command data only from the main control unit to the sub-control unit. A data transmission device in a pachinko machine, comprising: a one-way data transfer means for prohibiting a data signal input from a sub control unit to a main control unit.