JPH08222835A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH08222835A
JPH08222835A JP2716595A JP2716595A JPH08222835A JP H08222835 A JPH08222835 A JP H08222835A JP 2716595 A JP2716595 A JP 2716595A JP 2716595 A JP2716595 A JP 2716595A JP H08222835 A JPH08222835 A JP H08222835A
Authority
JP
Japan
Prior art keywords
insulating layer
copper powder
layer
conductor circuit
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2716595A
Other languages
Japanese (ja)
Other versions
JP2737683B2 (en
Inventor
Seiichi Inoue
誠一 井上
Masao Ishibashi
正朗 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7027165A priority Critical patent/JP2737683B2/en
Publication of JPH08222835A publication Critical patent/JPH08222835A/en
Application granted granted Critical
Publication of JP2737683B2 publication Critical patent/JP2737683B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE: To obtain large adhesive strength between an insulating layer and conductor layer by exposing part of copper particles on the surface of the insulating layer by removing the surface layer of the insulating layer after fixing the particles scattered on the surface of the insulating layer by pressing down the particles and forming a conductor circuit by plating the surface of the insulating layer on which part of the particles is exposed. CONSTITUTION: A conductor circuit 2a is formed by etching the copper which is the base material for a copper-plated laminated substrate 1 and an insulating layer 3 is formed on the surface of the substrate 1. Then copper particles 4 are spread on the surface of the layer 3 and buried in the layer 3 by pressing down the particles 4 and part of the particles 4 is exposed on the surface of the layer 3 by polishing the surface of the layer 3. In addition, a second conductor circuit 6a is formed by forming via holes 5 and plated conductor layers on the surface of the layer 3 and internal surfaces of the holes 5, and then, etching the conductor layer in a second pattern. Moreover, a third conductor circuit 9a is formed by opening a through hole 8 and forming a plated conductor layer on the internal surface of the hole 8 and the surface of an insulating layer 7, and then, etching the conductor layer 7 in a third pattern.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、印刷配線板の製造方法
に関し、特に絶縁層上にめっき等で導電層を形成する印
刷配線板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board in which a conductive layer is formed on an insulating layer by plating or the like.

【0002】[0002]

【従来の技術】電子機器の携帯化が進む中で、印刷配線
板に対する多層化・高密度化の要求はますます高まるば
かりである。このような要求に応える印刷配線板の製造
方法として、基板上に導体層と絶縁層とを繰り返し形成
して多層化するビルドアップ工法が注目されている。ビ
ルドアップ工法を適用することにより、安価で高密度な
印刷配線板の製造が可能となる。しかしながら、ビルド
アップ工法では、繰り返し形成する絶縁層と導体層との
間の密着強度に問題があり、密着強度を向上させるため
に種々の工夫がなされている。ここで、特開平3−28
3493号に報告されている絶縁層と導体層との界面に
銅粉を散布する方法を従来技術として図9を参照しなが
ら説明する。
2. Description of the Related Art As electronic devices are becoming more portable, the demand for multilayered and high-density printed wiring boards is ever increasing. As a method of manufacturing a printed wiring board that meets such a demand, a build-up method in which a conductor layer and an insulating layer are repeatedly formed on a substrate to form a multilayer has attracted attention. By applying the build-up method, it is possible to manufacture an inexpensive and high-density printed wiring board. However, in the build-up method, there is a problem with the adhesion strength between the insulating layer and the conductor layer that are repeatedly formed, and various measures have been taken to improve the adhesion strength. Here, JP-A-3-28
The method of spraying copper powder on the interface between the insulating layer and the conductor layer reported in Japanese Patent No. 3493 will be described with reference to FIG. 9 as a conventional technique.

【0003】まず図9(a)に示すような銅張りガラス
エポキシ積層基板からなる基材10を出発材料とする。
図9(b)に示すように、基材10上に基材銅11を設
け、基材銅11を通常のフォトリソグラフィー法等によ
り所望のパターン形状に蝕刻し、基材銅11からなる回
路(以下、単に導体回路11aという)を形成する。
First, a base material 10 made of a copper-clad glass epoxy laminated substrate as shown in FIG. 9A is used as a starting material.
As shown in FIG. 9B, a base material copper 11 is provided on the base material 10, and the base material copper 11 is etched into a desired pattern shape by an ordinary photolithography method or the like to form a circuit composed of the base material copper 11 ( Hereinafter, simply referred to as the conductor circuit 11a) is formed.

【0004】次に図9(c)に示すように、基材10上
の導体回路11aが形成された表面に絶縁層12を形成
する。さらに図9(d)に示すように、未硬化状態の絶
縁層12の表面に銅粉13を隙間なく均一に散布し、加
熱により絶縁層12を硬化させる。次に図9(e)のよ
うに、基材10の裏面にも同様に絶縁層12を形成し、
銅粉13を散布し、絶縁層12を硬化させる。次いで図
9(f)に示すように、均一に散布された銅粉13上に
銅めっきを行い導体層14を形成する。さらに図10
(a)に示すように導体層14をフォトリソグラフィー
法等により所望のパターン形状に蝕刻し、導体層14か
らなる回路(以下、単に導体回路14aという)を形成
する。
Next, as shown in FIG. 9C, an insulating layer 12 is formed on the surface of the base material 10 on which the conductor circuit 11a is formed. Further, as shown in FIG. 9D, copper powder 13 is evenly dispersed on the surface of the uncured insulating layer 12 without any gap, and the insulating layer 12 is cured by heating. Next, as shown in FIG. 9E, the insulating layer 12 is similarly formed on the back surface of the base material 10,
Copper powder 13 is sprinkled to cure the insulating layer 12. Next, as shown in FIG. 9F, copper plating is performed on the copper powder 13 that has been uniformly dispersed to form a conductor layer 14. Furthermore, FIG.
As shown in (a), the conductor layer 14 is etched into a desired pattern shape by a photolithography method or the like to form a circuit including the conductor layer 14 (hereinafter, simply referred to as a conductor circuit 14a).

【0005】このような工程を繰り返すことにより、図
10(b)に示すような複数の導体層と絶縁層とが重な
った構造を得る。次に図10(c)に示すように、NC
ドリルを用いて基材10を上下に貫通する貫通スルーホ
ール16を形成する。次に図11(a)に示すように、
絶縁層15と銅粉13の層とを積層した後、銅粉13の
層の表面及び貫通スルーホール16の内周面に銅めっき
を行い導体層17を形成する。さらに図11(b)に示
すように、導体層17をフォトリソグラフィー法等によ
り蝕刻し、基材10上の上下側及び貫通スルーホール1
6の内周面に導体層17からなる導体回路17aを形成
し、多層印刷配線板を得る。
By repeating the above steps, a structure in which a plurality of conductor layers and an insulating layer overlap each other as shown in FIG. 10B is obtained. Next, as shown in FIG.
Through holes 16 are formed to vertically penetrate the substrate 10 using a drill. Next, as shown in FIG.
After laminating the insulating layer 15 and the layer of the copper powder 13, copper plating is performed on the surface of the layer of the copper powder 13 and the inner peripheral surface of the through-hole 16 to form the conductor layer 17. Further, as shown in FIG. 11B, the conductor layer 17 is etched by a photolithography method or the like, and the upper and lower sides of the base material 10 and the through-holes 1 are etched.
A conductor circuit 17a composed of the conductor layer 17 is formed on the inner peripheral surface of 6 to obtain a multilayer printed wiring board.

【0006】[0006]

【発明が解決しようとする課題】上述の従来技術におい
ては次のような欠点がある。すなわち、 (1)従来技術によって散布した銅粉13は図12
(b)に示すように下部のみが絶縁層12,15に差し
込まれ、その大部分が絶縁層の表面に露出した状態にあ
る。したがって絶縁層12,15と銅粉13の接着面積
が小さく、また、絶縁層12〜15と銅粉13との界面
に毛細管現象により薬液が染み込みやすい。通常、無電
解銅めっきの一連の処理には、銅表面を洗浄するための
マイクロエッチング処理が含まれるが、エッチング液が
絶縁層12,15と銅粉13の間に入り込み銅粉13を
溶解する。したがって、銅粉13は絶縁層12,15か
ら容易に脱落し、期待した密度強度が得られず、また、
無電解銅めっきラインの浴を銅粉13で汚染する恐れが
ある。 (2)配線密度を向上させる手段として、隣接する上下
の導体回路間のみを接続するビアホールの導入が効果的
であるが、従来技術による印刷配線板の製造方法では、
ビアホールの形成が困難である。すなわちビアホール
は、絶縁層を光硬化性樹脂で形成しフォトリソグラフィ
ー法でビアホールを形成するもの、絶縁層を熱硬化性樹
脂で形成しレーザーでビアホールを形成するもの等があ
るが、従来技術のように絶縁層12,15上に銅粉13
を隙間なく散布する方法では、光硬化に使用する紫外線
又はレーザー光が銅粉13の層に妨げられて絶縁層1
2,15に届かないため、ビアホールの形成は困難であ
る。
The above-mentioned prior art has the following drawbacks. That is, (1) the copper powder 13 dispersed by the conventional technique is shown in FIG.
As shown in (b), only the lower part is inserted into the insulating layers 12 and 15, and most of them are exposed on the surface of the insulating layer. Therefore, the adhesion area between the insulating layers 12 and 15 and the copper powder 13 is small, and the chemical solution easily penetrates into the interface between the insulating layers 12 to 15 and the copper powder 13 due to the capillary phenomenon. Usually, a series of treatments for electroless copper plating include micro-etching treatment for cleaning the copper surface, but the etching solution enters between the insulating layers 12 and 15 and the copper powder 13 to dissolve the copper powder 13. . Therefore, the copper powder 13 is easily removed from the insulating layers 12 and 15, and the expected density strength cannot be obtained.
The copper powder 13 may contaminate the bath of the electroless copper plating line. (2) As a means for improving the wiring density, it is effective to introduce via holes that connect only the adjacent upper and lower conductor circuits. However, in the method for manufacturing a printed wiring board according to the conventional technique,
It is difficult to form a via hole. That is, as the via hole, there are one in which an insulating layer is formed of a photo-curing resin and a via hole is formed by a photolithography method, and another in which an insulating layer is formed of a thermosetting resin and a via hole is formed by a laser. And copper powder 13 on the insulating layers 12 and 15
In the method of spraying without gaps, the ultraviolet or laser light used for photocuring is blocked by the layer of the copper powder 13 and the insulating layer 1
Since it does not reach 2,15, it is difficult to form a via hole.

【0007】本発明の目的は、かかる従来技術の欠点を
解決すると共に、従来より課題となっていた絶縁層と導
体層との密着強度を向上させる印刷配線板の製造方法を
提供することにある。
An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a method of manufacturing a printed wiring board which improves the adhesion strength between an insulating layer and a conductor layer, which has been a problem in the past. .

【0008】[0008]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る印刷配線板の製造方法は、絶縁層形成
工程と、銅粉散布工程と、埋込工程と、銅粉露出工程
と、導体回路形成工程とを少なくとも含む印刷配線板の
製造方法であって、絶縁層形成工程は、基板上に形成さ
れた導体回路の表面に絶縁層を形成するものであり、銅
粉散布工程は、前記絶縁層上に銅粉を散布するものであ
り、埋込工程は、前記銅粉を圧下して絶縁層内に押し込
め該銅粉を絶縁層内に定着させるものであり、銅粉露出
工程は、前記絶縁層の表層を取り除いて銅粉の一部を絶
縁層の表面に露出させるものであり、導体回路形成工程
は、前記銅粉の一部が露出した絶縁層の表面にめっきを
行い導体回路を形成するものである。
In order to achieve the above object, a method of manufacturing a printed wiring board according to the present invention comprises an insulating layer forming step, a copper powder spraying step, an embedding step, and a copper powder exposing step. A method for manufacturing a printed wiring board including at least a conductor circuit forming step, wherein the insulating layer forming step forms an insulating layer on the surface of the conductor circuit formed on the substrate, and the copper powder spraying step is The copper powder is sprayed on the insulating layer, and the embedding step is for pressing down the copper powder into the insulating layer and fixing the copper powder in the insulating layer. Is to remove the surface layer of the insulating layer to expose a part of the copper powder on the surface of the insulating layer, and the conductor circuit forming step performs plating on the surface of the insulating layer where the copper powder is partially exposed. A conductor circuit is formed.

【0009】また、絶縁層形成工程と、銅粉散布工程
と、埋込工程と、銅粉露出工程と、ビアホール形成工程
と、導体回路形成工程とを少なくとも含み、絶縁層を挾
んで隣接する導体回路相互間をビアホールを介して導通
させてなる印刷配線板の製造方法であって、絶縁層形成
工程は、基板上に形成された導体回路の表面に絶縁層を
形成するものであり、銅粉散布工程は、前記絶縁層上に
銅粉を散在散布するものであり、埋込工程は、前記銅粉
を圧下して絶縁層内に押し込め該銅粉を絶縁層内に定着
させるものであり、銅粉露出工程は、前記絶縁層の表層
を取り除いて銅粉の一部を絶縁層の表面に露出させるも
のであり、ビアホール形成工程は、前記絶縁層を貫通す
るビアホールを形成するものであり、導体回路形成工程
は、前記銅粉の一部が露出した絶縁層の表面及びビアホ
ールの内面にめっきを行い導体回路を形成するものであ
る。
Further, at least an insulating layer forming step, a copper powder spraying step, a burying step, a copper powder exposing step, a via hole forming step, and a conductor circuit forming step are included, and conductors adjacent to each other with an insulating layer sandwiched therebetween are included. A method for manufacturing a printed wiring board in which circuits are electrically connected via via holes, wherein an insulating layer forming step forms an insulating layer on a surface of a conductor circuit formed on a substrate. The spraying step is one in which copper powder is scattered on the insulating layer, and the embedding step is to push down the copper powder into the insulating layer to fix the copper powder in the insulating layer. The copper powder exposing step removes the surface layer of the insulating layer to expose a part of the copper powder on the surface of the insulating layer, and the via hole forming step forms a via hole penetrating the insulating layer, Conductor circuit formation process is a part of the copper powder On the surface and the inner surface of the via hole of the exposed insulating layer is to form a conductor circuit performs plating.

【0010】また、前記絶縁層形成工程は、基板上に形
成された導体回路の表面を粗面化し、絶縁層と導体回路
との密着強度を高めるものである。
In the insulating layer forming step, the surface of the conductor circuit formed on the substrate is roughened to increase the adhesion strength between the insulating layer and the conductor circuit.

【0011】また、前記銅粉露出工程は、前記絶縁層の
表層を研摩して銅粉を絶縁層表面に露出させるものであ
る。
In the copper powder exposing step, the surface layer of the insulating layer is polished to expose the copper powder on the surface of the insulating layer.

【0012】また、前記銅粉露出工程は、前記絶縁層の
表層を化学的酸化処理して銅粉を絶縁層表面に露出させ
るものである。
Further, in the copper powder exposing step, the surface layer of the insulating layer is chemically oxidized to expose the copper powder to the surface of the insulating layer.

【0013】また、前記導体回路形成工程は、絶縁層の
表面にめっきにより形成される導体回路をなす導体層
を、絶縁層に埋設された銅粉により絶縁層上に密着させ
るものである。
Further, in the conductor circuit forming step, a conductor layer forming a conductor circuit formed on the surface of the insulating layer by plating is brought into close contact with the insulating layer by copper powder embedded in the insulating layer.

【0014】また、前記銅粉散布工程は、少なくとも表
層が未硬化状態の絶縁層の表面に銅粉を散布するもので
ある。
In the copper powder spraying step, copper powder is sprayed on the surface of the insulating layer whose surface layer is at least uncured.

【0015】また、前記銅粉散布工程は、ビアホール形
成用の光線が絶縁層に届く間隔をもって銅粉を絶縁層上
に散布するものである。
Further, in the copper powder spraying step, copper powder is sprayed on the insulating layer at intervals such that a light beam for forming a via hole reaches the insulating layer.

【0016】また、前記埋込工程は、少なくとも絶縁層
の表層が未硬化状態であるときに、銅粉を圧下して絶縁
層内に定着するものである。
In the embedding step, copper powder is pressed down and fixed in the insulating layer when at least the surface layer of the insulating layer is in an uncured state.

【0017】[0017]

【作用】絶縁層上に散布した銅粉を圧下して、銅粉を絶
縁層内に完全に埋設させて定着し、銅粉の絶縁層に対す
るアンカー効果を向上させ、この埋設された銅粉をもっ
て、導体層をなすめっき被膜の絶縁層に対する密着強度
を向上させる。
[Function] The copper powder scattered on the insulating layer is pressed down so that the copper powder is completely embedded and fixed in the insulating layer to improve the anchoring effect of the copper powder on the insulating layer. , Improving the adhesion strength of the plated coating forming the conductor layer to the insulating layer.

【0018】さらに銅粉を絶縁層に完全に埋設させて定
着させることにより、導体層をなすめっき被膜の絶縁層
に対する密着強度を十分に確保することが可能となるた
め、銅粉の散布量を制御することにより、銅粉が埋設さ
れた絶縁層にビアホールの形成を可能にする。
Further, by completely embedding and fixing the copper powder in the insulating layer, it becomes possible to sufficiently secure the adhesion strength of the plated coating forming the conductor layer to the insulating layer, so that the amount of the copper powder sprayed can be increased. By controlling, it becomes possible to form a via hole in the insulating layer in which the copper powder is buried.

【0019】[0019]

【実施例】以下、本発明の実施例を図により説明する。Embodiments of the present invention will be described below with reference to the drawings.

【0020】(実施例1)図1〜図4は、本発明の実施
例1に係る印刷配線板の製造方法を工程順に示す断面図
である。
(Embodiment 1) FIGS. 1 to 4 are sectional views showing a method of manufacturing a printed wiring board according to Embodiment 1 of the present invention in the order of steps.

【0021】図において本発明に係る印刷配線板の製造
方法は、基本的には、絶縁層形成工程と、銅粉散布工程
と、埋込工程と、銅粉露出工程と、導体回路形成工程と
を少なくとも含むものであり、絶縁層形成工程におい
て、基板上に形成された導体回路の表面に絶縁層を形成
し、銅粉散布工程において、前記絶縁層上に銅粉を散布
し、埋込工程において、前記銅粉を圧下して絶縁層内に
押し込め該銅粉を絶縁層内に定着させ、銅粉露出工程に
おいて、前記絶縁層の表層を取り除いて銅粉の一部を絶
縁層の表面に露出させ、導体回路形成工程において、前
記銅粉の一部が露出した絶縁層の表面にめっきを行い導
体回路を形成し、絶縁層に埋設した銅粉をもって、導体
層をなすめっき被膜の絶縁層に対する密着強度を高め、
多層化・高密度の印刷配線板を製造するものである。
In the figure, the method for manufacturing a printed wiring board according to the present invention basically comprises an insulating layer forming step, a copper powder spraying step, an embedding step, a copper powder exposing step, and a conductor circuit forming step. In the insulating layer forming step, an insulating layer is formed on the surface of the conductor circuit formed on the substrate, and in the copper powder dispersing step, copper powder is dispersed on the insulating layer, and an embedding step is performed. In, in pressing the copper powder into the insulating layer and fixing the copper powder in the insulating layer, in the copper powder exposing step, the surface layer of the insulating layer is removed and a part of the copper powder is applied to the surface of the insulating layer. In the step of forming a conductor circuit by exposing, the conductor circuit is formed by plating on the surface of the insulating layer where a part of the copper powder is exposed in the conductor circuit forming step, and the copper powder embedded in the insulating layer forms an insulating layer of a plating film forming the conductor layer. Increase the adhesion strength to
It manufactures multi-layered and high-density printed wiring boards.

【0022】さらに本発明に係る印刷配線板の製造方法
は、上述した基本的構成に付加してビアホール形成工程
を有し、ビアホール形成工程において、前記絶縁層を貫
通するビアホールを形成し、導体回路形成工程におい
て、前記銅粉の一部が露出した絶縁層の表面及びビアホ
ールの内面にめっきを行い導体回路を形成し、これによ
り絶縁層を挾んで隣接する導体回路相互間をビアホール
を介して導通させてなる印刷配線板を製造するするもの
である。
Furthermore, the method for manufacturing a printed wiring board according to the present invention has a via hole forming step in addition to the above-mentioned basic structure, and in the via hole forming step, a via hole penetrating the insulating layer is formed to form a conductor circuit. In the forming step, the surface of the insulating layer where a part of the copper powder is exposed and the inner surface of the via hole are plated to form a conductor circuit, and the conductor layer is sandwiched between the conductor circuits to conduct electricity through the via hole. The printed wiring board thus manufactured is manufactured.

【0023】次に本発明に係る印刷配線板の製造方法を
図1〜図4に示す具体的な例を用いて説明する。本実施
例では、図1(a)に示すように導体回路が形成される
基板として、導体層をなす基材銅(銅箔)2が両面に張
り付けられた銅張りガラスエポキシ積層基板からなる基
材1を用いている。
Next, a method for manufacturing a printed wiring board according to the present invention will be described with reference to specific examples shown in FIGS. In this embodiment, as a substrate on which a conductor circuit is formed as shown in FIG. 1A, a base made of a copper-clad glass epoxy laminated substrate having a base material copper (copper foil) 2 forming a conductor layer adhered on both sides. Material 1 is used.

【0024】まず図1(b)に示すように、通常のフォ
トリソグラフィー法等により基材1の基材銅2を所望形
状のパターンに蝕刻し、基材銅2からなる導体回路(以
下、導体回路2aという)を形成する。ここで基材銅2
を所望形状のパターンに蝕刻する際のマスクとなるレジ
スト層としてドライフィルムを使用し、基材銅(銅箔)
2を蝕刻するエッチング液として塩化第二鉄水溶液を使
用した。
First, as shown in FIG. 1 (b), a base material copper 2 of a base material 1 is etched into a pattern of a desired shape by a normal photolithography method or the like to form a conductor circuit (hereinafter referred to as a conductor) composed of the base material copper 2. Circuit 2a). Base material copper 2 here
Using a dry film as a resist layer that serves as a mask when etching a pattern of a desired shape, copper (copper foil) as a base material
An aqueous solution of ferric chloride was used as an etching solution for etching 2.

【0025】次に絶縁層3を基材1上に形成するにあた
って、酸性塩化第二銅水溶液で導体回路2aの表面を粗
面化後、アルカリ性過硫酸カリウム水溶液で導体回路2
aの表面を酸化し針状に粗面加工することで、導体回路
2aと次に形成する絶縁層3との間の密着性を向上させ
る。導体回路2aの粗面処理には、ここで示したアルカ
リ性過硫酸カリウム水溶液の他にも、アルカリ性亜塩素
酸ナトリウム,硫化カリ−塩化アンモニア水溶液等が使
用できる。
Next, when forming the insulating layer 3 on the substrate 1, the surface of the conductor circuit 2a is roughened with an aqueous solution of acidic cupric chloride, and then the conductor circuit 2 is formed with an aqueous solution of alkaline potassium persulfate.
By oxidizing the surface of a and roughening it into a needle shape, the adhesion between the conductor circuit 2a and the insulating layer 3 to be formed next is improved. In addition to the alkaline potassium persulfate aqueous solution shown here, alkaline sodium chlorite, potassium sulfide-ammonia chloride aqueous solution or the like can be used for the rough surface treatment of the conductor circuit 2a.

【0026】図1(c)に示すように、導体回路2aの
粗面化処理を施した後、感光性液状絶縁樹脂をロールコ
ーターにより、基材1の導体回路2aが形成された表面
上に塗布し絶縁層3を形成する。絶縁層3の形成には、
ロールコーターの他にも、カーテンコーター,スプレー
コーター,スクリーン印刷等の方法が用いられる。ロー
ルコーターでは1回の塗布によって15μmの厚さの絶
縁層3が得られるので、塗布を4回繰り返し60μmの
絶縁層3を得た。形成される樹脂層3の厚さは塗布する
方法によって異なるため、数回の塗布・乾燥を繰り返し
所望の厚さの絶縁層3を形成する。また、絶縁層3の表
層のみを未乾燥状態にしておくため、3回目のコートを
行った後、ベーキング(90℃,30分)により予備硬
化を行い、4回目のコートを行った後は、ベーキングを
行わない。これにより、絶縁層3は、乾燥した層45μ
mと未乾燥の層15μmが重なった状態となる。
As shown in FIG. 1C, after the conductor circuit 2a is roughened, a photosensitive liquid insulating resin is applied by a roll coater on the surface of the base material 1 on which the conductor circuit 2a is formed. The insulating layer 3 is formed by coating. To form the insulating layer 3,
Besides the roll coater, methods such as a curtain coater, a spray coater, and screen printing are used. With the roll coater, the insulating layer 3 having a thickness of 15 μm can be obtained by one coating, so the coating was repeated 4 times to obtain the insulating layer 3 having a thickness of 60 μm. Since the thickness of the resin layer 3 to be formed differs depending on the coating method, coating and drying are repeated several times to form the insulating layer 3 having a desired thickness. In addition, in order to leave only the surface layer of the insulating layer 3 in an undried state, after the third coating, pre-curing is performed by baking (90 ° C., 30 minutes), and after the fourth coating, Do not bake. As a result, the insulating layer 3 is a dried layer 45μ.
m and the undried layer 15 μm overlap each other.

【0027】次に図1(d)に示すように、表層が未乾
燥である絶縁層3の表面に平均粒径10μm,粒度分布
が5〜15μmの銅粉4を散布する。ここで後工程にお
いてビアホール形成工程を実施するにあたっては、銅粉
4を2mg/cm2程度の密度で均一に散布する。銅粉
の散布には、コンベア式のエア散布装置を用い、0.5
〜0.8kg/cm2の圧力,2m/分のコンベア速度
で行った。銅粉4の散布が過剰であった場合、後工程で
の光硬化が十分に行われずビアホールを形成することが
できない。ビアホールの形成には、ビアホールを形成す
る箇所の基材1の表面が銅粉4により覆われずに少なく
とも50%以上の面積が露出している必要がある。本実
施例では、表面の面積の60%程度が露出している。絶
縁層3のうち、4回目にコートされた層はベーキングを
行っていないため、流動性を持っており、従って、散布
した銅粉4は、絶縁層3内に埋め込まれるようになって
いる。
Next, as shown in FIG. 1D, copper powder 4 having an average particle size of 10 μm and a particle size distribution of 5 to 15 μm is sprayed on the surface of the insulating layer 3 whose surface layer is undried. Here, in performing the via hole forming step in the subsequent step, the copper powder 4 is evenly dispersed at a density of about 2 mg / cm 2 . For spraying copper powder, use a conveyor type air spraying device
It was carried out at a pressure of ˜0.8 kg / cm 2 and a conveyor speed of 2 m / min. If the copper powder 4 is excessively dispersed, the photo-curing in the subsequent step is not sufficiently performed and the via hole cannot be formed. To form a via hole, it is necessary that the surface of the base material 1 where the via hole is formed is not covered with the copper powder 4 and an area of at least 50% or more is exposed. In this embodiment, about 60% of the surface area is exposed. Among the insulating layers 3, the layer coated for the fourth time has no fluidity, and therefore has fluidity, and therefore the scattered copper powder 4 is embedded in the insulating layer 3.

【0028】次に図1(e)に示すように、プレス処理
により銅粉4を絶縁層3中に埋め込む。プレスは、ステ
ンレス製の鏡板を用い、常温下、80〜100kg/c
2の圧力で60秒間行い、銅粉4を絶縁層3中に完全
に埋没し3次元的に捕捉し、銅粉4を絶縁層3中に定着
させる。プレス処理を行う際、鏡板と絶縁層3との間に
ポリエチレン製の剥離用のフィルムを介装し、未硬化の
絶縁層3の表面に鏡板が付着しないよう処理している。
さらに、図1(f)に示すように裏面にも同様の工程を
施す。
Next, as shown in FIG. 1 (e), copper powder 4 is embedded in the insulating layer 3 by pressing. The press uses a stainless steel end plate, and at room temperature 80 to 100 kg / c
The copper powder 4 is completely buried in the insulating layer 3 and three-dimensionally captured by fixing the copper powder 4 in the insulating layer 3 by performing the treatment at a pressure of m 2 for 60 seconds. When performing the pressing process, a polyethylene peeling film is interposed between the end plate and the insulating layer 3 so that the end plate is not attached to the surface of the uncured insulating layer 3.
Further, as shown in FIG. 1F, the same process is performed on the back surface.

【0029】次工程で銅粉4を絶縁層3の表面に露出さ
せる処理を行う前に、絶縁層3の未硬化部分を予備硬化
させるために、ベーキング(90℃,30分)を行う。
そして図2(a)に示すように、ベルト研磨装置により
絶縁層3の表層を約5μm研磨する。ここでは、#60
0のベルトを2Kgf/cm2の圧力で使用し3回研磨
を繰り返した。銅粉4は、絶縁層3の表面から5μm程
度の間に分布しているため、研磨により、ほとんどの銅
粉4が部分的に絶縁層3の表面に露出する。
Before the process of exposing the copper powder 4 to the surface of the insulating layer 3 in the next step, baking (90 ° C., 30 minutes) is performed to pre-cure the uncured portion of the insulating layer 3.
Then, as shown in FIG. 2A, the surface layer of the insulating layer 3 is polished by about 5 μm by a belt polishing device. Here, # 60
No. 0 belt was used at a pressure of 2 kgf / cm 2 , and polishing was repeated 3 times. Since the copper powder 4 is distributed within about 5 μm from the surface of the insulating layer 3, most of the copper powder 4 is partially exposed on the surface of the insulating layer 3 by polishing.

【0030】次に図2(b)に示すように、紫外線(積
算露光量4000〜6000mJ)を照射することによ
りビアホール形成部以外の絶縁層3の表面を光硬化さ
せ、さらに現像することにより未硬化であるビアホール
形成部の絶縁層3と銅粉4とを同時に除去し、ビアホー
ル5(ビア径0.1mm以上)を形成し、ビアホール5
内に下層の導体回路2aを露出させる。さらに絶縁層3
の硬化を進めるためにベーキング(140℃,1時間)
を行う。
Next, as shown in FIG. 2B, the surface of the insulating layer 3 other than the via hole forming portion is photo-cured by irradiation with ultraviolet rays (integrated exposure amount of 4000 to 6000 mJ), and further development is carried out. The insulating layer 3 and the copper powder 4 in the via-hole forming portion, which is hardened, are simultaneously removed to form a via hole 5 (via diameter of 0.1 mm or more).
The lower conductor circuit 2a is exposed inside. Insulation layer 3
Baking (140 ° C, 1 hour) to accelerate curing
I do.

【0031】アルカリ性過マンガン酸塩水溶液(KMn
O4:40〜60g/1,規定度:1.0〜1.2N,
60〜80℃)を用いて、絶縁層3の表面を化学的に酸
化する。酸化により、絶縁層3の表層1〜2μmが除去
され、前記ベルト研磨装置による研磨で露出しなかった
銅粉4が部分的に露出する。同時に絶縁層3の表面が粗
面化され、絶縁層3と次に形成する導体層6との密着性
を向上させる。次に図2(c)に示すように、無電解銅
めっき及び電気銅めっきを連続して施すことにより、絶
縁層3上の銅粉4が露出した表面とビアホール5の内面
にめっき被膜からなる20μmの導体層6を形成する。
また、無電解銅めっきのみで導体層6を形成しても良
い。本発明により散布した銅粉4は、絶縁層3内に完全
に埋め込まれ、図12(a)のような状態にある。銅粉
4と導体層6も密着は良好であり、アンカー効果により
絶縁層3に対する導体層6の密着性が向上する。また銅
粉4が絶縁層3内に完全に埋設されているため、図12
(b)に示す従来のように銅粉4と絶縁層3との間に隙
間が形成されず薬液が染み込みにくくマイクロエッチン
グ処理においても、銅粉4が脱落することはない。しか
しながら、過剰なマイクロエッチングは、絶縁層3の表
面に露出した銅粉4を完全に溶解してしまうので、マイ
クロエッチングを0.5〜1μm程度の厚さにコントロ
ールすることが必要である。
Alkaline permanganate aqueous solution (KMn
O4: 40-60g / 1, Normality: 1.0-1.2N,
60 to 80 ° C.) is used to chemically oxidize the surface of the insulating layer 3. By oxidation, the surface layer 1 to 2 μm of the insulating layer 3 is removed, and the copper powder 4 not exposed by the polishing by the belt polishing device is partially exposed. At the same time, the surface of the insulating layer 3 is roughened to improve the adhesion between the insulating layer 3 and the conductor layer 6 to be formed next. Next, as shown in FIG. 2C, electroless copper plating and electrolytic copper plating are continuously performed to form a plating film on the exposed surface of the copper powder 4 on the insulating layer 3 and the inner surface of the via hole 5. A conductor layer 6 of 20 μm is formed.
The conductor layer 6 may be formed only by electroless copper plating. The copper powder 4 scattered by the present invention is completely embedded in the insulating layer 3 and is in a state as shown in FIG. The copper powder 4 and the conductor layer 6 also have good adhesion, and the anchor effect improves the adhesion of the conductor layer 6 to the insulating layer 3. In addition, since the copper powder 4 is completely embedded in the insulating layer 3, as shown in FIG.
No gap is formed between the copper powder 4 and the insulating layer 3 unlike the conventional case shown in (b), and the chemical liquid is less likely to permeate, and the copper powder 4 does not fall off even in the micro etching process. However, excessive micro-etching completely dissolves the copper powder 4 exposed on the surface of the insulating layer 3, so it is necessary to control the micro-etching to a thickness of about 0.5 to 1 μm.

【0032】次に図2(d)に示すように、図1(b)
で用いた通常のフォトリソグラフィー法等により導体層
6を所望形状のパターンに蝕刻し、導体層6からなる導
体回路(以下、導体回路6aという)を形成する。この
場合、基材1上の導体回路2aの一部と絶縁層3上の導
体回路6aの一部とは、ビアホール5の内面に形成され
た導体層6により導通される。
Next, as shown in FIG. 2D, as shown in FIG.
The conductor layer 6 is etched into a pattern having a desired shape by the usual photolithography method used in step 1 to form a conductor circuit composed of the conductor layer 6 (hereinafter referred to as a conductor circuit 6a). In this case, a part of the conductor circuit 2 a on the base material 1 and a part of the conductor circuit 6 a on the insulating layer 3 are electrically connected by the conductor layer 6 formed on the inner surface of the via hole 5.

【0033】さらに上述した工程を繰り返し図3(a)
に示すような複数の導体層と絶縁層とが重なった構造を
得る。
Further, the above-mentioned steps are repeated and shown in FIG.
A structure in which a plurality of conductor layers and an insulating layer are overlapped with each other is obtained.

【0034】次に図3(b)に示すように、図2(b)
の工程と同様にビアホール5を形成し、N/Cドリルに
より貫通スルーホール8を開ける。
Next, as shown in FIG. 3B, as shown in FIG.
The via hole 5 is formed in the same manner as in the step (1), and the through-hole 8 is opened by an N / C drill.

【0035】次に図3(c)に示すようにめっきを行
い、貫通スルーホール8の内面と絶縁層7の表面とにめ
っき被膜による導体層9を設ける。絶縁層3又は7上の
導体回路2a,6aのうちスルーホール8に露出したも
のは導体層9に導通される。最後に、図4に示すように
絶縁層7上の導体層9を図1(b)で用いた通常のフォ
トリソグラフィー法等により所望形状のパターンに蝕刻
し、導体層9からなる回路(以下、導体回路9aとい
う)を形成する。
Next, as shown in FIG. 3 (c), plating is performed to provide a conductor layer 9 made of a plated film on the inner surface of the through hole 8 and the surface of the insulating layer 7. Of the conductor circuits 2a and 6a on the insulating layer 3 or 7, those exposed in the through holes 8 are conducted to the conductor layer 9. Finally, as shown in FIG. 4, the conductor layer 9 on the insulating layer 7 is etched into a pattern of a desired shape by the ordinary photolithography method used in FIG. The conductor circuit 9a) is formed.

【0036】(実施例2)図5〜図8は、本発明の実施
例2を示す断面図である。次に本発明に係る印刷配線板
の製造方法を図5〜図8に示す具体的な例を用いて説明
する。本実施例では、図5(a)に示すように導体回路
が形成される基板として、導体層をなす基材銅(銅箔)
2が両面に張り付けられた銅張りガラスエポキシ積層基
板からなる基材1を用いている。
(Embodiment 2) FIGS. 5 to 8 are sectional views showing Embodiment 2 of the present invention. Next, a method for manufacturing a printed wiring board according to the present invention will be described with reference to specific examples shown in FIGS. In this embodiment, as a substrate on which a conductor circuit is formed as shown in FIG. 5A, a base material copper (copper foil) forming a conductor layer.
2 is used as a base material 1 made of a copper-clad glass-epoxy laminated substrate having both surfaces attached.

【0037】まず図5(b)に示すように、通常のフォ
トリソグラフィー法等により基材1の基材銅2を所望形
状のパターンに蝕刻し、基材銅2からなる導体回路(以
下、導体回路2aという)を形成する。ここで基材銅2
を所望形状のパターンに蝕刻する際のマスクとなるレジ
スト層としてドライフィルムを使用し、基材銅(銅箔)
2を蝕刻するエッチング液として塩化第二鉄水溶液を使
用した。
First, as shown in FIG. 5B, the base material copper 2 of the base material 1 is etched into a pattern of a desired shape by a normal photolithography method or the like to form a conductor circuit (hereinafter referred to as a conductor) made of the base material copper 2. Circuit 2a). Base material copper 2 here
Using a dry film as a resist layer that serves as a mask when etching a pattern of a desired shape, copper (copper foil) as a base material
An aqueous solution of ferric chloride was used as an etching solution for etching 2.

【0038】次に絶縁層3を基材1上に形成するにあた
って、酸性塩化第二銅水溶液で導体回路2aの表面を粗
面化後、アルカリ性過硫酸カリウム水溶液で導体回路2
aの表面を酸化し針状に粗面加工することで、導体回路
2aと次に形成する絶縁層3との間の密着性を向上させ
る。導体回路2aの粗面処理には、ここで示したアルカ
リ性過硫酸カリウム水溶液の他にも、アルカリ性亜塩素
酸ナトリウム,硫化カリ−塩化アンモニア水溶液等が使
用できる。
Next, in forming the insulating layer 3 on the substrate 1, the surface of the conductor circuit 2a is roughened with an aqueous solution of acidic cupric chloride, and then the conductor circuit 2 is treated with an aqueous solution of alkaline potassium persulfate.
By oxidizing the surface of a and roughening it into a needle shape, the adhesion between the conductor circuit 2a and the insulating layer 3 to be formed next is improved. In addition to the alkaline potassium persulfate aqueous solution shown here, alkaline sodium chlorite, potassium sulfide-ammonia chloride aqueous solution or the like can be used for the rough surface treatment of the conductor circuit 2a.

【0039】図5(c)に示すように、導体回路2aの
粗面化処理を施した後、感光性液状絶縁樹脂をカーテン
コーターにより、基材1の導体回路2aが形成された表
面上に塗布し絶縁層3を形成する。絶縁層3の形成に
は、カーテンコーターの他にも、ロールコーター,プレ
ーコーター,スクリーン印刷等の方法が用いられる。カ
ーテンコーターでは1回の塗布によって10μmの厚さ
の絶縁層3が得られるので、塗布を5回繰り返し50μ
mの絶縁層3を得た。形成される樹脂層3の厚さは塗布
する方法によって異なるため、数回の塗布・乾燥を繰り
返し所望の厚さの絶縁層3を形成する。また、絶縁層3
の表層のみを未乾燥状態にしておくため、4回目のコー
トを行った後、ベーキング(90℃,30分)により予
備硬化を行い、5回目のコートを行った後は、ベーキン
グを行わない。これにより、絶縁層3は、乾燥した層4
0μmと未乾燥の層10μmが重なった状態となる。
As shown in FIG. 5C, after the conductor circuit 2a is roughened, a photosensitive liquid insulating resin is applied to the surface of the base material 1 on which the conductor circuit 2a is formed by a curtain coater. The insulating layer 3 is formed by coating. In addition to the curtain coater, a method such as a roll coater, a play coater, or screen printing is used to form the insulating layer 3. With the curtain coater, the insulating layer 3 having a thickness of 10 μm can be obtained by one application, so the application is repeated 5 times and 50 μm.
m insulating layer 3 was obtained. Since the thickness of the resin layer 3 to be formed differs depending on the coating method, coating and drying are repeated several times to form the insulating layer 3 having a desired thickness. Also, the insulating layer 3
In order to leave only the surface layer of No. 1 in an undried state, after the fourth coating, pre-curing is performed by baking (90 ° C., 30 minutes), and after the fifth coating, baking is not performed. As a result, the insulating layer 3 becomes the dried layer 4
0 μm and 10 μm of the undried layer overlap each other.

【0040】次に図5(d)に示すように、表層が未乾
燥である絶縁層3の表面に平均粒径10μm粒度分布が
5〜15μmの銅粉4を散布する。ここで後工程におい
てビアホール形成工程を実施するにあたっては、銅粉4
を2mg/cm2程度の密度で均一に散布する。銅粉の
散布には、コンベア式のエア散布装置を用い、0.5〜
0.8kg/cm2の圧力,2m/分のコンベア速度で
行った。銅粉4の散布が過剰であった場合、後工程での
光硬化が十分に行われずビアホールを形成することがで
きない。ビアホールの形成には、ビアホールを形成する
箇所の基材1の表面が銅粉4により覆われずに少なくと
も50%以上の面積が露出している必要がある。本実施
例では、表面の面積の60%程度が露出している。絶縁
層3のうち、4回目にコートされた層はベーキングを行
っていないため、流動性を持っており、従って、散布し
た銅粉は、絶縁層3の表層に埋め込まれるようになって
いる。
Next, as shown in FIG. 5D, copper powder 4 having an average particle size of 10 μm and a particle size distribution of 5 to 15 μm is sprayed on the surface of the insulating layer 3 whose surface layer is undried. When performing the via hole forming step in the subsequent step, the copper powder 4
Is evenly distributed at a density of about 2 mg / cm 2 . For spraying copper powder, use a conveyor type air spraying device,
It was carried out at a pressure of 0.8 kg / cm 2 and a conveyor speed of 2 m / min. If the copper powder 4 is excessively dispersed, the photo-curing in the subsequent step is not sufficiently performed and the via hole cannot be formed. To form a via hole, it is necessary that the surface of the base material 1 where the via hole is formed is not covered with the copper powder 4 and an area of at least 50% or more is exposed. In this embodiment, about 60% of the surface area is exposed. Of the insulating layers 3, the layer coated for the fourth time has no fluidity, and therefore has fluidity, and therefore, the scattered copper powder is embedded in the surface layer of the insulating layer 3.

【0041】次に図5(e)に示すように、ローラー処
理により銅粉4を絶縁層3中に埋め込む。ローラー処理
は、ステンレス製のローラーの周面にポリエチレンをコ
ーティングしたものを用い、ローラー処理を行う際、未
硬化の絶縁層3の表面にローラーの周面が付着しないよ
うに処理している。ローラーにより銅粉4を圧下する線
圧力を100〜120kg/cm2とし、ローラーと基
材1との相対搬送速度を1m/分とし、銅粉4を絶縁層
3中に完全に埋設し3次元的に捕捉し、銅粉4を絶縁層
3中に定着させる。さらに図5(f)に示すように裏面
にも同様の工程を施す。
Next, as shown in FIG. 5E, the copper powder 4 is embedded in the insulating layer 3 by a roller treatment. The roller treatment is performed by using a stainless steel roller whose peripheral surface is coated with polyethylene. When the roller treatment is performed, the peripheral surface of the roller is not attached to the surface of the uncured insulating layer 3. The linear pressure for pressing down the copper powder 4 by the roller is 100 to 120 kg / cm 2 , the relative transport speed between the roller and the substrate 1 is 1 m / min, and the copper powder 4 is completely embedded in the insulating layer 3 to form a three-dimensional structure. And then the copper powder 4 is fixed in the insulating layer 3. Further, as shown in FIG. 5F, the same process is performed on the back surface.

【0042】次工程で銅粉4を絶縁層3の表面に露出さ
せる処理を行う前に、絶縁層3の未硬化部分を予備硬化
させるために、ベーキング(90℃,30分)を行う。
Before the process of exposing the copper powder 4 to the surface of the insulating layer 3 in the next step, baking (90 ° C., 30 minutes) is performed to pre-cure the uncured portion of the insulating layer 3.

【0043】次に図6(a)に示すように、紫外線(積
算露光量4000〜6000mJ)を照射することによ
りビアホール形成部以外の絶縁層3の表面を光硬化さ
せ、さらに現像することにより未硬化であるビアホール
形成部の絶縁層3と銅粉4とを同時に除去し、ビアホー
ル5(ビア径0.1mm以上)を形成し、ビアホール5
内に下層の導体回路2aを露出させる。さらに絶縁層3
の硬化を進めるためにベーキング(140℃,1時間)
を行う。
Next, as shown in FIG. 6 (a), the surface of the insulating layer 3 other than the via hole forming portion is photo-cured by irradiating with ultraviolet rays (integrated exposure amount 4000-6000 mJ), and further developed to develop the surface. The insulating layer 3 and the copper powder 4 in the via-hole forming portion, which is hardened, are simultaneously removed to form a via hole 5 (via diameter of 0.1 mm or more).
The lower conductor circuit 2a is exposed inside. Insulation layer 3
Baking (140 ° C, 1 hour) to accelerate curing
I do.

【0044】次に図6(b)に示すようにアルカリ性過
マンガン酸塩水溶液(KMnO4:40〜60g/1,
規定度:1.0〜1.2N,60〜80℃)を用いて、
絶縁層3の表面を化学的に酸化する。酸化により、絶縁
層3の表層1〜2μmが除去される。銅粉4は、絶縁層
3の表面から1μm程度の間に分布しているため、前記
化学的酸化処理によりほとんど全ての銅粉4は、絶縁層
3の表面上に部分的に露出する。銅粉4の埋め込みが浅
いため、実施例1のようなベルト研磨は必要ない。絶縁
層3を機械的に研磨しないため、銅粉4に応力がかから
ず、銅粉4の脱落が起こりにくい。同時に絶縁層3の表
面が粗面化され、絶縁層3と次に形成する導体層6との
密着性を向上させる。次に図6(c)に示すように、無
電解銅めっき及び電気銅めっきを連続して施すことによ
り、絶縁層3上の銅粉4が露出した表面とビアホール5
の内面にめっき被膜からなる20μmの導体層6を形成
する。また、無電解銅めっきのみで導体層6を形成して
も良い。本発明により散布した銅粉4は、絶縁層3内に
完全に埋め込まれ、図12(a)のような状態にある。
銅粉4と導体層6も密着は良好であり、アンカー効果に
より絶縁層3と導体層6の密着性が向上する。また銅粉
4が絶縁層3内に完全に埋設されているため、図12
(b)に示す従来のように銅粉4と絶縁層3との間に隙
間が形成されず薬液が染み込みにくくマイクロエッチン
グ処理においても、銅粉4が脱落することはない。しか
しながら、過剰なマイクロエッチングは、絶縁層3の表
面に露出した銅粉4を完全に溶解してしまうので、マイ
クロエッチングを0.5〜1μm程度の厚さにコントロ
ールすることが必要である。
Next, as shown in FIG. 6 (b), an aqueous alkaline permanganate solution (KMnO4: 40-60 g / 1,
Normality: 1.0 to 1.2 N, 60 to 80 ° C.)
The surface of the insulating layer 3 is chemically oxidized. By oxidation, the surface layer 1 to 2 μm of the insulating layer 3 is removed. Since the copper powder 4 is distributed within about 1 μm from the surface of the insulating layer 3, almost all the copper powder 4 is partially exposed on the surface of the insulating layer 3 by the chemical oxidation treatment. Since the embedding of the copper powder 4 is shallow, belt polishing as in Example 1 is not necessary. Since the insulating layer 3 is not mechanically polished, stress is not applied to the copper powder 4, and the copper powder 4 is less likely to fall off. At the same time, the surface of the insulating layer 3 is roughened to improve the adhesion between the insulating layer 3 and the conductor layer 6 to be formed next. Next, as shown in FIG. 6C, electroless copper plating and electrolytic copper plating are continuously performed to expose the surface of the insulating layer 3 where the copper powder 4 is exposed and the via hole 5.
A conductor layer 6 having a thickness of 20 μm and formed of a plating film is formed on the inner surface of the. The conductor layer 6 may be formed only by electroless copper plating. The copper powder 4 scattered by the present invention is completely embedded in the insulating layer 3 and is in a state as shown in FIG.
The copper powder 4 and the conductor layer 6 also have good adhesion, and the adhesion effect improves the adhesion between the insulating layer 3 and the conductor layer 6. In addition, since the copper powder 4 is completely embedded in the insulating layer 3, as shown in FIG.
No gap is formed between the copper powder 4 and the insulating layer 3 unlike the conventional case shown in (b), and the chemical liquid is less likely to permeate, and the copper powder 4 does not fall off even in the micro etching process. However, excessive micro-etching completely dissolves the copper powder 4 exposed on the surface of the insulating layer 3, so it is necessary to control the micro-etching to a thickness of about 0.5 to 1 μm.

【0045】次に図6(d)に示すように、図5(b)
で用いた通常のフォトリソグラフィー法等により導体層
6を所望形状のパターンに蝕刻し、導体層6からなる導
体回路(以下、導体回路6aという)を形成する。この
場合、基材1上の導体回路2aの一部と絶縁層3上の導
体回路6aの一部とは、ビアホール5の内面に形成され
た導体層6により導通される。
Next, as shown in FIG. 6D, as shown in FIG.
The conductor layer 6 is etched into a pattern having a desired shape by the usual photolithography method used in step 1 to form a conductor circuit composed of the conductor layer 6 (hereinafter referred to as a conductor circuit 6a). In this case, a part of the conductor circuit 2 a on the base material 1 and a part of the conductor circuit 6 a on the insulating layer 3 are electrically connected by the conductor layer 6 formed on the inner surface of the via hole 5.

【0046】さらに上述した工程を繰り返し図7(a)
に示すような複数の導体層と絶縁層とが重なった構造を
得る。
Further, the steps described above are repeated, and FIG.
A structure in which a plurality of conductor layers and an insulating layer are overlapped with each other is obtained.

【0047】次に図7(b)に示すように、図2(b)
の工程と同様にビアホール5を形成し、N/Cドリルに
より貫通スルーホール8を開ける。
Next, as shown in FIG. 7B, as shown in FIG.
The via hole 5 is formed in the same manner as in the step (1), and the through-hole 8 is opened by an N / C drill.

【0048】次に図7(c)に示すようにめっきを行
い、貫通スルーホール8の内面と絶縁層7の表面とにめ
っき被膜による導体層9を設ける。絶縁層3又は7上の
導体回路2a,6aのうちスルーホール8に露出したも
のは導体層9に導通される。最後に、図8に示すように
絶縁層7上の導体層9を図5(b)で用いた通常のフォ
トリソグラフィー法等により所望形状のパターンに蝕刻
し、導体層9からなる回路(以下、導体回路9aとい
う)を形成する。
Next, as shown in FIG. 7C, plating is performed to provide a conductor layer 9 made of a plated film on the inner surface of the through hole 8 and the surface of the insulating layer 7. Of the conductor circuits 2a and 6a on the insulating layer 3 or 7, those exposed in the through holes 8 are conducted to the conductor layer 9. Finally, as shown in FIG. 8, the conductor layer 9 on the insulating layer 7 is etched into a pattern of a desired shape by the ordinary photolithography method used in FIG. The conductor circuit 9a) is formed.

【0049】[0049]

【発明の効果】以上説明したように本発明によれば、絶
縁層表面に散布した銅粉が絶縁層に3次元的に捕捉さ
れ、導体層であるめっき被膜と極めて強い密着強度が得
られる。また、強い密着強度を確保できることから、銅
粉の散布量を制御することで、ビアホールの形成を可能
にする。以上、本発明によれば、密着性に優れた高密度
の印刷配線板を得ることができる。
As described above, according to the present invention, the copper powder scattered on the surface of the insulating layer is three-dimensionally captured by the insulating layer, and extremely strong adhesion strength with the plated coating which is the conductor layer can be obtained. Further, since a strong adhesion strength can be secured, it is possible to form a via hole by controlling the amount of copper powder sprayed. As described above, according to the present invention, a high-density printed wiring board having excellent adhesion can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

【図2】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図3】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 3 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図4】本発明の実施例1を工程順に示す断面図であ
る。
FIG. 4 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図5】本発明の実施例1を工程順に示す断面図であ
る。
5A to 5C are cross-sectional views showing the first embodiment of the present invention in the order of steps.

【図6】本発明の実施例2を工程順に示す断面図であ
る。
FIG. 6 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図7】本発明の実施例2を工程順に示す断面図であ
る。
FIG. 7 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図8】本発明の実施例2を工程順に示す断面図であ
る。
FIG. 8 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図9】従来例を工程順に示す断面図である。FIG. 9 is a cross-sectional view showing a conventional example in the order of steps.

【図10】従来例を工程順に示す断面図である。FIG. 10 is a cross-sectional view showing a conventional example in the order of steps.

【図11】従来例を工程順に示す断面図である。FIG. 11 is a cross-sectional view showing a conventional example in the order of steps.

【図12】(a)は、本発明における銅粉の埋設状態を
示す断面図、(b)は、従来例における銅粉の埋設状態
を示す断面図である。
FIG. 12 (a) is a cross-sectional view showing an embedded state of copper powder in the present invention, and FIG. 12 (b) is a cross-sectional view showing an embedded state of copper powder in a conventional example.

【符号の説明】[Explanation of symbols]

1 基材 2 基材銅 2a 導体回路 3 絶縁層 4 銅粉 5 ビアホール 6 導体層 6a 導体回路 7 絶縁層 8 貫通スルーホール 9 導体層 9a 導体回路 10 基材 11 基材銅 12 絶縁層 13 銅粉 14 導体層 15 絶縁層 16 貫通スルーホール 17 導体層 1 Base Material 2 Base Material Copper 2a Conductor Circuit 3 Insulating Layer 4 Copper Powder 5 Via Hole 6 Conductor Layer 6a Conductor Circuit 7 Insulating Layer 8 Through Through Hole 9 Conductor Layer 9a Conductor Circuit 10 Base Material 11 Base Material Copper 12 Insulation Layer 13 Copper Powder 14 Conductor Layer 15 Insulating Layer 16 Through Through Hole 17 Conductor Layer

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層形成工程と、銅粉散布工程と、埋
込工程と、銅粉露出工程と、導体回路形成工程とを少な
くとも含む印刷配線板の製造方法であって、 絶縁層形成工程は、基板上に形成された導体回路の表面
に絶縁層を形成するものであり、 銅粉散布工程は、前記絶縁層上に銅粉を散布するもので
あり、 埋込工程は、前記銅粉を圧下して絶縁層内に押し込め該
銅粉を絶縁層内に定着させるものであり、 銅粉露出工程は、前記絶縁層の表層を取り除いて銅粉の
一部を絶縁層の表面に露出させるものであり、 導体回路形成工程は、前記銅粉の一部が露出した絶縁層
の表面にめっきを行い導体回路を形成するものであるこ
とを特徴とする印刷配線板の製造方法。
1. A method for manufacturing a printed wiring board, comprising at least an insulating layer forming step, a copper powder spraying step, an embedding step, a copper powder exposing step, and a conductor circuit forming step, the insulating layer forming step. Is for forming an insulating layer on the surface of the conductor circuit formed on the substrate, the copper powder spraying step is for spraying copper powder on the insulating layer, and the embedding step is for the copper powder. Is pressed down into the insulating layer to fix the copper powder in the insulating layer. In the copper powder exposing step, the surface layer of the insulating layer is removed to expose a part of the copper powder on the surface of the insulating layer. The method for producing a printed wiring board is characterized in that in the conductor circuit forming step, a conductor circuit is formed by plating the surface of the insulating layer where a part of the copper powder is exposed.
【請求項2】 絶縁層形成工程と、銅粉散布工程と、埋
込工程と、銅粉露出工程と、ビアホール形成工程と、導
体回路形成工程とを少なくとも含み、絶縁層を挾んで隣
接する導体回路相互間をビアホールを介して導通させて
なる印刷配線板の製造方法であって、 絶縁層形成工程は、基板上に形成された導体回路の表面
に絶縁層を形成するものであり、 銅粉散布工程は、前記絶縁層上に銅粉を散在散布するも
のであり、 埋込工程は、前記銅粉を圧下して絶縁層内に押し込め該
銅粉を絶縁層内に定着させるものであり、 銅粉露出工程は、前記絶縁層の表層を取り除いて銅粉の
一部を絶縁層の表面に露出させるものであり、 ビアホール形成工程は、前記絶縁層を貫通するビアホー
ルを形成するものであり、 導体回路形成工程は、前記銅粉の一部が露出した絶縁層
の表面及びビアホールの内面にめっきを行い導体回路を
形成するものであることを特徴とする印刷配線板の製造
方法。
2. An insulating layer forming step, a copper powder spraying step, a burying step, a copper powder exposing step, a via hole forming step, and a conductor circuit forming step, which at least include an insulating layer sandwiched between adjacent conductors. A method for manufacturing a printed wiring board in which circuits are electrically connected via via holes, wherein the insulating layer forming step forms an insulating layer on the surface of a conductor circuit formed on a substrate. The spraying step is one in which copper powder is scattered on the insulating layer, and the embedding step is for pressing down the copper powder into the insulating layer to fix the copper powder in the insulating layer, The copper powder exposing step removes the surface layer of the insulating layer to expose a part of the copper powder on the surface of the insulating layer, and the via hole forming step forms a via hole penetrating the insulating layer, In the conductor circuit forming step, part of the copper powder is A method for manufacturing a printed wiring board, characterized in that a conductor circuit is formed by plating the exposed surface of the insulating layer and the inner surface of the via hole.
【請求項3】 前記絶縁層形成工程は、基板上に形成さ
れた導体回路の表面を粗面化し、絶縁層と導体回路との
密着強度を高めるものであることを特徴とする請求項1
又は2に記載の印刷配線板の製造方法。
3. The insulating layer forming step is to roughen the surface of a conductor circuit formed on a substrate to enhance the adhesion strength between the insulating layer and the conductor circuit.
Or the method for manufacturing a printed wiring board according to item 2.
【請求項4】 前記銅粉露出工程は、前記絶縁層の表層
を研摩して銅粉を絶縁層表面に露出させるものであるこ
とを特徴とする請求項1又は2に記載の印刷配線板の製
造方法。
4. The printed wiring board according to claim 1, wherein in the copper powder exposing step, the surface layer of the insulating layer is polished to expose the copper powder to the surface of the insulating layer. Production method.
【請求項5】 前記銅粉露出工程は、前記絶縁層の表層
を化学的酸化処理して銅粉を絶縁層表面に露出させるも
のであることを特徴とする請求項1又は2に記載の印刷
配線板の製造方法。
5. The printing according to claim 1, wherein the copper powder exposing step is a step of chemically oxidizing the surface layer of the insulating layer to expose the copper powder on the surface of the insulating layer. Wiring board manufacturing method.
【請求項6】 前記導体回路形成工程は、絶縁層の表面
にめっきにより形成される導体回路をなす導体層を、絶
縁層に埋設された銅粉により絶縁層上に密着させるもの
であることを特徴とする請求項1又は2に記載の印刷配
線板の製造方法。
6. The conductor circuit forming step comprises contacting a conductor layer forming a conductor circuit formed by plating on the surface of the insulating layer with the copper powder embedded in the insulating layer onto the insulating layer. The method for manufacturing a printed wiring board according to claim 1, wherein the printed wiring board is manufactured.
【請求項7】 前記銅粉散布工程は、少なくとも表層が
未硬化状態の絶縁層の表面に銅粉を散布するものである
ことを特徴とする請求項1又は2に記載の印刷配線板の
製造方法。
7. The production of a printed wiring board according to claim 1, wherein in the copper powder spraying step, copper powder is sprayed on the surface of the insulating layer in which at least the surface layer is uncured. Method.
【請求項8】 前記銅粉散布工程は、ビアホール形成用
の光線が絶縁層に届く間隔をもって銅粉を絶縁層上に散
布するものであることを特徴とする請求項2又は7に記
載の印刷配線板の製造方法。
8. The printing according to claim 2, wherein in the copper powder spraying step, copper powder is sprayed on the insulating layer at intervals such that a light beam for forming a via hole reaches the insulating layer. Wiring board manufacturing method.
【請求項9】 前記埋込工程は、少なくとも絶縁層の表
層が未硬化状態であるときに、銅粉を圧下して絶縁層内
に定着するものであることを特徴とする請求項1又は2
に記載の印刷配線板の製造方法。
9. The embedding step is characterized in that, at least when the surface layer of the insulating layer is in an uncured state, the copper powder is pressed down and fixed in the insulating layer.
A method for manufacturing a printed wiring board according to.
JP7027165A 1995-02-15 1995-02-15 Manufacturing method of printed wiring board Expired - Fee Related JP2737683B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7027165A JP2737683B2 (en) 1995-02-15 1995-02-15 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7027165A JP2737683B2 (en) 1995-02-15 1995-02-15 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH08222835A true JPH08222835A (en) 1996-08-30
JP2737683B2 JP2737683B2 (en) 1998-04-08

Family

ID=12213456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7027165A Expired - Fee Related JP2737683B2 (en) 1995-02-15 1995-02-15 Manufacturing method of printed wiring board

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Country Link
JP (1) JP2737683B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361284C (en) * 2001-10-19 2008-01-09 全懋精密科技股份有限公司 IC packing substrate structure and its manufacture

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143686A (en) * 1984-08-17 1985-07-29 株式会社井上ジャパックス研究所 Method of producing printed circuit board
JPH03283493A (en) * 1990-03-30 1991-12-13 Masafumi Miyazaki Manufacture of multilayer wiring board

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Publication number Priority date Publication date Assignee Title
JPS60143686A (en) * 1984-08-17 1985-07-29 株式会社井上ジャパックス研究所 Method of producing printed circuit board
JPH03283493A (en) * 1990-03-30 1991-12-13 Masafumi Miyazaki Manufacture of multilayer wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361284C (en) * 2001-10-19 2008-01-09 全懋精密科技股份有限公司 IC packing substrate structure and its manufacture

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