JPH08213333A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To compensate a defect, which is induced in an insulating substrate at the time of n impurity implantation in the substrate, and to make a heat treatment of the substrate possible at a low temperature by a method wherein hydrogen ions are accelerate from a plasma space simultaneously with group III ions or group V ions and the group III ions or the group V ions and the hydrogen ions are selectively introduced in a silicon thin film using a mask formed on the silicon thin film. CONSTITUTION: A vacuum container 1 consisting of a quartz tube, electrodes 2 for high-frequency power which is applied to the outside, and an electromagnet 3 are provided and an external magnetic field is formed. pH3 gas, which is diluted with H2 and is introduced in the container 1, is excited in an electromagnetic field and generated phosphorus ions 4 and hydrogen ions 5 are accelerated. A sample 10 put on a base 6 is selecting doped using a mask 7. The sample 10 is an amorphous silicon semiconductor layer 9 formed on an insulation substrate 8. Thereby, impurities can be introduced on the substrate, on which a large area substrate is easily formed and which is formed with the amorphous silicon semiconductor layer, without using a deposition method and the number of processes can be lessened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION With the recent advances in office automation and computerization, it has become essential to increase the size of information input devices and display devices for both consumer and industrial use. In particular, in a contact type thin film image sensor as an input device and a liquid crystal display as a display device, a large area and high-speed processing have been demanded as the amount of information increases. These devices are composed of photosensors, thin film transistors and the like, and development of large area and low cost processes for them is strongly desired.

[0002]

2. Description of the Related Art Amorphous silicon is mainly used as a constituent material of the above-mentioned optical sensor, and polycrystalline silicon is used together with amorphous silicon as a constituent material of a thin film transistor. For forming an electrode contact portion and a source / drain region of an optical sensor or a thin film transistor using amorphous silicon, a high concentration and low resistance shallow (~ 200
Ii) The formation of an impurity-introduced layer is indispensable. Conventionally, the impurity-introduced layer was formed by plasma-enhanced chemical vapor deposition (P-CVD). In addition, it was necessary to remove the impurity by a method, and it was impossible to form an impurity-introduced layer selectively using an organic photosensitive material in a usual manner.

FIG. 9 shows a process for manufacturing a large-area inverted staggered amorphous silicon thin film transistor by using the conventional P-CVD method. On the insulating substrate 100, a metal gate electrode 101 such as Cr, a silicon nitride film 102 as a gate insulating film, an amorphous silicon film 103 as an active layer,
After forming silicon nitride 104 to be passivation as shown in FIG. 9A, after depositing n ⁺ amorphous silicon film 105 for forming source / drain regions on the entire surface (FIG. 9B), the source / drain regions are left. Instead of selectively etching away the layer 105 by photo-etching or forming the structure of FIG. 9C, the gate insulating film 102, amorphous silicon 103,
After continuously forming the passivation film 104, after forming the passivation film 104 as shown in FIG. 9A, FIG.
As shown in FIG. 9C, the n ⁺ amorphous silicon may be formed on the entire surface by the P-CVD method and the pattern may be formed by the photo-etching method. Then, by forming the metal electrode 6, an amorphous silicon thin film transistor is formed (FIG. 9D).

[0004]

In general, an ion implantation method is applied to the formation of the source / drain of a MOS transistor in an ordinary semiconductor integrated circuit using a single crystal silicon substrate, but it is not possible to form it on a large area substrate. Amorphous silicon, which is easy to perform, cannot be subjected to the necessary heat treatment by ordinary ion implantation, and thus a laborious process of forming and selectively removing the n ⁺ amorphous silicon layer 105 as shown in FIG. 9 is required. Has brought about an increase. That is, the ion implantation method is not suitable for forming a thin film transistor using amorphous silicon because it requires high-temperature heat treatment for activation and defect removal after impurity introduction. Further, in the method of FIG. 9, the n ⁺ film 105 for the source / drain is the film 10
Since it is deposited on the gate insulating film 102, the distance between the source / drain and the channel region 107 at the interface between the gate insulating film 102 and the silicon film 103 serving as an active layer is large, and the resistance between them is large, so that the transistor characteristics are deteriorated.

[0005]

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device capable of solving such a problem, and an amorphous silicon thin film in which a large area substrate can be easily formed. It is an object of the present invention to provide a method for manufacturing a semiconductor device using the substrate on which is formed without the step of depositing an impurity layer and the number of steps is small. Another object of the present invention is to provide a method for manufacturing a semiconductor device having a channel region and a low resistance between a source and a drain. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can perform uniform processing on a large area substrate in a short time.

In order to achieve the above object, the present invention provides a substrate on which a silicon thin film is formed, from a plasma space containing Group III element ions and hydrogen ions of the periodic table or Group V element ions and hydrogen ions of the periodic table. A mask formed on the silicon thin film is installed at a distant position to accelerate the group III element ion and hydrogen ion of the periodic table or the group V element ion and hydrogen ion of the periodic table from the plasma space. A method of manufacturing a semiconductor device is characterized in that the group III element ions and hydrogen ions of the periodic table or the group V element ions and hydrogen ions of the periodic table are selectively introduced.

Further, the present invention uses the above method particularly for the regions to be the MOS type field effect source and drain regions of the inverted stagger structure using amorphous silicon formed on the insulating substrate.

In the process technique of the present invention, hydrogen ions are introduced into the substrate at the same time as the impurity element ions, so that the impurities can be easily and surely injected into the amorphous silicon and the polycrystalline silicon which are integrated in a large area. That is, the technique used in the present invention uses a high-purity gas, extracts impurity element ions and hydrogen ions from the generated plasma, and irradiates the ions on the substrate heated to a predetermined temperature by low voltage acceleration in a shower shape to remove impurities. It is a new plasma process technology (ion shower doping technology) that introduces (doping). With this technology, the self-alignment technology used in the semiconductor LSI process can be applied to a large area, and the device performance is improved. Moreover, the process can be simplified, and control of polycrystalline silicon, formation of source / drain of an amorphous silicon thin film transistor, formation of shallow electrode regions, arbitrary selective doping of p and n, etc. can be easily performed.
It is also suitable for manufacturing an optical sensor using amorphous silicon. Particularly, in the case of amorphous silicon, hydrogen ions are injected at the same time as the impurity implantation into the amorphous silicon, so that defects induced during the impurity implantation can be compensated. It can be performed at a low temperature that does not change, and it becomes possible to form a high-quality impurity introduction layer and a junction.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the technique used in the present invention will be described. FIG. 1 is a conceptual diagram of this ion shower doping technique. For example, a vacuum container 1 made of a quartz tube 1, an electrode for high frequency power applied to the outside 2, an external magnetic field formed by an electromagnet 3
₍₂ ) Sample 1 placed on the substrate stage 6 by exciting the diluted PH ₃ gas in an electromagnetic field to accelerate the generated phosphorus ions 4 and hydrogen ions 5.
Selective doping is performed on the mask 0 using the mask 7.

The sample 10 is an amorphous silicon semiconductor layer 9 formed on the insulating substrate 8. 10 is a neutral molecule.

An apparatus for ion shower doping is shown in FIG. 2 at 13.56 megahertz (1 mega = 1).
( ⁶ ) high-frequency power and magnetic field are applied to the discharge chamber, the excited ions in the plasma are drawn into the processing chamber at a voltage of 1 to 10 kilovolts, and the large-area integrated device 10 (shown in FIG. 1) is heated to a predetermined temperature. The sample is irradiated with ions in a shower shape. Since this device uses high-frequency power to generate ions, it is possible to create uniform plasma and perform batch processing over a large area.
Since a large current ion beam can be obtained by applying a magnetic field,
When impurities are implanted into an A4 size thin film transistor using amorphous silicon, the processing time can be about 1 minute. Also, the device configuration is much simpler than that of the ion implantation device. Reference numeral 1 denotes a quartz tube that constitutes a vacuum container, and for example, 2% PH ₃ gas diluted with hydrogen introduced from the gas introduction tube 12 is exhausted by a vacuum pump and maintained at, for example, 10 ⁻⁴ Torr level. It is excited and discharged by the high frequency electrode 2 and the electromagnet 3 which are installed outside to form plasma containing at least phosphorus ions 4 and hydrogen ions 5. The magnetic field may not be applied depending on the processing time and the injection amount. Reference numeral 13 is an insulator flange that uses vinyl chloride to insulate the discharge chamber and the chamber 15 including the substrate table 14. The electrode 16 seals the quartz tube in a vacuum and a DC voltage (1 to 10 KV) is applied. Reference numeral 17 denotes another electrode, which is kept at the same potential as the electrode 16 in the present device, but of course a positive voltage may be applied to the electrode 16. 18
Is an AC power source for heating the substrate table 14, and a sample on which the large-area integrated device 10 is to be formed is placed on the substrate table 14. This heating means may not be used depending on the material and structure of the element. Reference numeral 19 is a vacuum flange, 20 is a heater, 21 is an opening, and 22 is an ionization vacuum gauge.

The features of this device are as follows: 1) Doping into a large area integrated device such as A4 size is possible.

2) The device structure is extremely simple and inexpensive. (Approximately one-third or less of that of ion implantation equipment) 3) High-efficiency ionization method using magnetic field is used, so a high-current ion beam can be obtained, and doping can be performed in A4 size in about 1 minute in a short time. It is possible.

4) Ion irradiation can be performed at an acceleration energy of 10 KeV or less, and a high-concentration shallow doping layer (up to 20 nm) can be formed.

5) Since selective doping using a mask such as an organic photosensitive material is possible, it is possible to simplify the process particularly in an amorphous silicon device and manufacture a device having a new structure.

This new plasma process technology facilitates mass production of a large-area long device in which thin film transistors and sensors are integrated, and creates a key device for input and display of OA equipment, image processing terminal equipment, etc. It becomes an important basic technology.

The following table shows a doping technology comparison table.

[0018]

[Table 1]

Further, as shown in FIG. 3, since selective doping for forming an arbitrary p-type / n-type conductive layer in an arbitrary region can be performed shallowly, the application region of the amorphous silicon device can be dramatically expanded. It will be possible. FIG. 3A schematically shows the conventional ion implantation method, and FIG. 3B schematically shows the ion shower method of this embodiment. In the case of FIG. 3A, only the impurity ions are implanted into the semiconductor thin film, and when the impurities are implanted, the bonds between the elements are broken to generate defects, and the number is considered to be several hundreds for one impurity ion. To be

On the other hand, in the case of FIG. 3B as well, it seems that a defect similarly occurs. However, in the case of the ion shower method of the present embodiment, hydrogen ions are also implanted together with the impurity ions, and it is considered that the hydrogen ions play a role of compensating for defects caused by the implantation of the impurity ions.

Particularly when the semiconductor thin film is amorphous silicon,
Hydrogen is introduced into the thin film from the beginning, and seems to play a role in compensating for defects. However, since the number of defects generated by the introduction of one impurity ion is large, it was originally included in the thin film. Defects cannot be sufficiently compensated by hydrogen alone, and defects can be sufficiently compensated by implanting hydrogen ions at the same time as impurity ion implantation. This allows
It is possible to perform the subsequent heat treatment process at a low temperature.

When the thin film 9 is amorphous silicon, the ion implantation method shown in FIG. 3A has a temperature at which the amorphous silicon is crystallized when the necessary heat treatment is performed after the ion implantation. , Not applicable. On the other hand, in the ion shower method of FIG. 3B, since hydrogen ions are used for doping with impurity ions,
The heat treatment process after the end of the ion shower can be performed at a temperature at which amorphous silicon does not crystallize. Therefore, the ion shower method can also be applied to amorphous silicon.

Next, description will be given of a case where the above-mentioned apparatus is used and applied to the production of a thin film transistor using amorphous silicon.

In FIG. 4A, 8 is a glass substrate and 30 is C.
A metal gate electrode such as r having a channel length of 10 μm. Reference numeral 31 denotes a P-CVD method using a mixed gas of a gate insulating film SiH ₄ gas and NH ₃ gas at a substrate temperature of 300 ° C. and about 30 ° C.
A SiN film of 00 ° is formed. Reference numeral 9 denotes an amorphous silicon substrate serving as an active layer of a transistor, that is, a channel portion and a source / drain portion, which is formed at a temperature of 250 ° C. at about 1000 °. A passivation film 32 is similarly formed by P-CVD at a substrate temperature of 250 ° C. to form a SiN film of about 3000 Å.
Then, after applying a photosensitive resin film, the passivation film 32 is photo-etched to leave a part as shown in FIG. 4B.
The dimension in the channel length direction at this time is, for example, 5 μ.

Then, the film 32 left behind is used as a mask.
Impurities are introduced into amorphous silicon using the above-described ion shower doping technique. First, the case of introducing n-type impurities will be described. PH ₃ gas diluted with hydrogen is introduced into the discharge chamber and discharged. As an example of the discharge condition at this time, the external high frequency power is 2 to 10 W, the external magnetic field is 50 gauss, and the vacuum degree is 5 × 1.
0 ^-4 Torr. The PH ₃ concentration diluted with hydrogen is 0.
In the case of 5%, at a position about 15 cm away from the outlet of the discharge chamber,
When the amorphous silicon 9 was irradiated with the ion shower 32 accelerated at 3.5 KeV at a substrate temperature of 300 ° C., the amorphous silicon was etched simultaneously with the introduction of impurities. P
When the H ₃ concentration was 2%, doping was mainly performed and etching was hardly observed. PH ₃ concentration is 10%
In this case, P was deposited on the amorphous silicon film. When the thickness of the amorphous silicon 9 is 1000 Å and the ion acceleration energy is 3.5 KeV, the P doping depth (projection range) is about 50 Å, so the source
The high concentration layer 34 (above the dotted line) is formed only in the surface region of the amorphous silicon film in the drain region. The thickness of the amorphous silicon is thin, for example, 500 °, the ion acceleration energy is 10 KeV, and the peak concentration is 10 ²⁰ / cm.
^When it is set to ³ , the concentration of the amorphous silicon 9 at a depth of 500 ° is 10 ¹⁵ / cm ³ .

As shown in FIG. 4C following FIG. 4B, the amorphous silicon is removed except for the transistor portion 9 and then source / drain electrodes 35 and 36 are formed.

By the above method, not only the process steps can be remarkably simplified and the area can be increased, but also the high concentration of amorphous silicon between the source / drain high concentration region layer 34 and the channel 37 can be obtained as shown in FIG. The resistance area is reduced. That is, a source region having a depth of l ₁ is formed in the amorphous silicon 9, the distance between the source and the channel can be shortened to l _2, and the resistance R can be reduced.

Conventionally, when a necessary heat treatment is performed on amorphous silicon after performing ion implantation, the temperature reaches a temperature at which the amorphous silicon is crystallized, so that the source region is formed by ion implantation. become unable. Therefore,
The source was deposited on the amorphous silicon 9 and the resistance R could not be reduced. However, in the ion shower method of the present invention, since hydrogen ions are used for doping together with impurity ions, the heat treatment process after the ion shower can be performed at a temperature at which amorphous silicon is not crystallized, and a source is deposited and formed. do not have to.

Further, by optimizing the parameters such as the film thickness of the amorphous silicon 9, the ion acceleration energy, the substrate temperature, etc., the source / drain regions can be formed over the entire thickness of the amorphous silicon, so that the input signal loss is lost. Relax or
Effects such as improvement of the switching speed of the amorphous thin film transistor also occur. Further, hydrogen ions are simultaneously implanted together with the doping of the impurity ions, so that the electrical characteristics due to the defects generated at the time of doping the impurities are compensated, which is suitable for the amorphous silicon which needs to contain hydrogen. At this time, there is an optimum value for the amount of hydrogen ions. When introducing impurities using PH ₃ , 0.5 to 10% in hydrogen is optimal. However, for example, when PH ₃ gas is diluted in He gas, hydrogen ions should be doped separately from P doping. Good.
The same applies when PF ₃ gas is used. Needless to say, the hydrogen-diluted PH ₃ gas may be treated in a separate step of hydrogen ion doping or hydrogen or plasma discharge containing hydrogen.

FIG. 6 shows an embodiment of this technique in which the source / drain regions are formed in a self-aligned manner using polycrystalline silicon or amorphous silicon. 6 and 8 are, for example, a quartz glass substrate, and 50 is about 2000 formed by a low pressure CVD method.
Å Polycrystalline silicon, 51 is a gate insulating film of ˜1000 Å thermal oxide film, and 52 is about 3000 Å gate polycrystalline silicon. As shown in FIG. 6, after pattern formation, ions are accelerated in a self-aligned manner, for example, in a plasma discharge of 2% PH ₃ gas diluted with hydrogen at 6 KeV, and impurities are introduced as an ion shower as indicated by an arrow. Then, anneal at 900 ° C. for 30 minutes in N ₂ gas. After that, a transistor is formed by a usual method. According to this method, even in a large area substrate, uniform and entire doping can be performed simultaneously without the need for ion shower scanning.

When amorphous silicon is used for the active layer instead of polycrystalline silicon, an insulating film formed by a photo CVD method or an ECR plasma CVD method is used instead of a thermal oxide film as a gate insulating film, and aluminum, another metal or metal is used. After patterning the silicide as the gate electrode as shown in FIG.
A transistor can be easily formed by raising the temperature at 00 to 300 ° C. and performing ion shower doping.

When the technique of the present invention is applied to the production of a thin film transistor using polycrystalline silicon, as shown in FIG. 3, polycrystalline silicon by ion shower extracted from formation of source / drain regions or plasma discharge of hydrogen gas is used. It can be applied to the grain boundary (Note 2) control of FIG. 7 shows an example of electric characteristics of the thin film transistor.

Further, in order to confirm the usefulness of the plasma processing technique of the present invention, an optical line sensor using amorphous silicon and a thin film transistor using polycrystalline silicon are integrated on a quartz substrate to form an integrated line sensor. I made a prototype. With regard to the transistor, on / off characteristics of 5 digits or more were obtained, and a drive circuit by this transistor and a sensor were integrated to obtain a photocurrent / dark current ratio of 2 digits or more. FIG. 8 shows the configuration and characteristics of this element.

The present invention relates to the source / source of a MOS transistor.
Not only is it applied to the formation of the drain, but as shown in FIG. 3, since the acceleration energy of ions during doping is lower than that in the case of conventional ion implantation, a mask is used.
An extremely shallow high-concentration impurity layer can be formed in an arbitrary region. For example, when the semiconductor thin film is amorphous silicon and the mask material is a silicon nitride film, ion acceleration energy is 3.5 KeV, P atoms are 5 × 10 ¹⁴ / cm ² , and the substrate temperature is 250 ° C. A layer having a conductivity of 10 ⁻³ (Ω · cm) ⁻¹ could be formed. For comparison, when formed by the ion implantation method, it is usually 0.1.
More than μm.

Further, the present invention can be applied to the introduction of P, n arbitrary group V and group III elements of the periodic table.

[0036]

EFFECTS OF THE INVENTION Since hydrogen ions are doped at the same time as Group III or Group V ions of the periodic table, defects induced during impurity implantation can be compensated and heat treatment at low temperature becomes possible. In particular, impurities can be introduced into a substrate on which amorphous silicon is formed, which is easy to form a large-area substrate, without using a deposition method, and the number of steps can be reduced. Also,
The resistance can be reduced by reducing the distance between the channel region of the transistor and the source / drain. Furthermore, by generating ions by discharge decomposition with high-frequency power under application of a magnetic field, a uniform plasma and a high-current ion beam can be provided, so that impurities can be uniformly introduced into a large-area substrate in a short time. .

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an impurity introduction method by an ion shower system used in the present invention.

FIG. 2 is a schematic diagram of an ion shower doping apparatus.

[Fig. 3] (A) State diagram of ion implantation method (B) State diagram of ion shower method

FIG. 4 is a sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention.

5 is a partially enlarged cross-sectional view of the transistor in FIG. 3C.

FIG. 6 is a sectional view of a manufacturing process of a polycrystalline silicon transistor.

FIG. 7 is an electrical characteristic diagram of a thin film transistor.

FIG. 8A is an integrated plan view of an amorphous silicon sensor and a thin film transistor, FIG. 8B is a sectional view taken along line XX ′ of FIG. 8A, and FIG. 8C is a characteristic diagram of FIG.

FIG. 9 is a process sectional view of a conventional amorphous silicon thin film transistor.

[Explanation of symbols]

 Reference Signs List 3 electromagnet 4 phosphorus ion 5 hydrogen ion 8 insulating substrate 9 amorphous silicon semiconductor layer 10 mask 34 high concentration impurity introduction layer

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/336

Claims (6)

[Claims] 1. A substrate on which a silicon thin film is formed is placed at a position apart from a plasma space containing group III element ions and hydrogen ions of the periodic table or group V element ions and hydrogen ions of the periodic table, and the plasma is formed. Ion and hydrogen ions of Group III element of the periodic table or V of the periodic table from the space
By accelerating group element ions and hydrogen ions, and selectively using the mask formed on the silicon thin film, the periodic table
A method for manufacturing a semiconductor device, which comprises introducing Group III element ions and hydrogen ions or Group V element ions and hydrogen ions of the periodic table. 2. A group III element ion and a hydrogen ion of the periodic table, or a group V element ion and a hydrogen ion of the periodic table are generated by discharge decomposition with high frequency power. A method for manufacturing a semiconductor device as described above. 3. A group III element ion and a hydrogen ion of the periodic table or a group V element ion and a hydrogen ion of the periodic table are generated by discharge decomposition by high frequency power under application of a magnetic field. The method for manufacturing a semiconductor device according to item 1. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon thin film is polycrystalline silicon or amorphous silicon. 5. The silicon thin film is amorphous silicon, the source gas for generating group V ions is PH ₃ diluted with hydrogen gas, and its concentration is in the range of more than 0.5% and less than 10%. The method for manufacturing a semiconductor device according to claim 1, wherein: 6. A gate electrode, a gate insulating film, and amorphous silicon to be an active layer and an insulating film are sequentially formed on an insulating substrate, and the insulating film formed on the amorphous silicon is used as a mask. A region of the semiconductor device is characterized in that regions to be the source and drain regions are irradiated with ions of group III elements and hydrogen ions of the periodic table or ions of group V elements of the periodic table and hydrogen ions by accelerating them from the plasma space. Production method.