JP2516951B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICABILITY With the recent shift to OA and computerization, it has become essential to increase the size of information input devices and display devices for both consumer and industrial use. In particular, in a contact type thin film image sensor as an input device and a liquid crystal display as a display device, a large area and high-speed processing have been demanded as the amount of information increases. These devices are composed of photosensors, thin film transistors and the like, and development of large area and low cost processes for them is strongly desired.

2. Description of the Related Art Amorphous silicon is mainly used as a constituent material of the above-described optical sensor, and polycrystalline silicon is used together with amorphous silicon as a constituent material of a thin film transistor. It is essential to form a high-concentration, low-resistance shallow (~ 200Å) impurity-doped layer for the formation of electrode contacts and source / drain regions of photosensors and thin-film transistors that use amorphous silicon. Although it was formed by using the chemical vapor deposition method (P-CVD), it is necessary to remove unnecessary regions by photo-etching after the deposition of the thin film into which impurities are introduced. It was impossible to selectively form the impurity introduction layer used.

FIG. 9 shows a process of manufacturing an amorphous silicon thin film transistor having a large-area inverted stagger structure using a conventional P-CVD method. A metal gate electrode 101 such as Cr, a silicon nitride film 102 as a gate insulating film, an amorphous silicon film 103 as an active layer, and a silicon nitride 104 as a passivation are formed on an insulating substrate 100 as shown in FIG. 9A. After that, the n ⁺ amorphous silicon film 105 for forming source / drain regions is formed on the entire surface.
9A as a process of selectively etching away the layer 105 by photolithography or leaving the source / drain regions after depositing the entire surface (FIG. 9B) or forming the structure of FIG. 9C. Instead of forming the above structure, the gate insulating film 102, the amorphous silicon 103, and the passivation film 104 are continuously formed, and then the passivation film 104 is formed as shown in FIG. 9A and then the entire surface as shown in FIG. 9B. In some cases, n ⁺ amorphous silicon is formed by the P-CVD method, and a pattern is formed by the photo-etching method as shown in FIG. 9C. After that, the metal electrode 6 is formed to form an amorphous silicon thin film transistor.
(FIG. 9D) Problems to be Solved by the Invention Generally, an ion implantation method is applied to the formation of the source / drain of a MOS transistor in a general semiconductor integrated circuit using a single crystal silicon substrate, but a large area substrate is used. Amorphous silicon that can be easily formed on the upper surface cannot be subjected to the necessary heat treatment by normal ion implantation, and as shown in FIG. 9, it is troublesome to form and selectively remove the n ⁺ amorphous silicon layer 105. Processes are required, resulting in an increase in processes. That is, the ion implantation method is not suitable for forming a thin film transistor using amorphous silicon because it requires high-temperature heat treatment for activation and defect removal after impurity introduction. Further, in the method of FIG. 9, n ⁺ for source / drain is used.
Since the film 105 is deposited on the film 103, the distance between the source / drain and the channel region 107 at the interface between the gate insulating film 102 and the silicon film 103 to be the active layer is large, and the resistance between them is large, resulting in poor transistor characteristics. was there.

Means for Solving the Problems The present invention provides a method for manufacturing a semiconductor device capable of solving such a problem, in which an amorphous silicon thin film that facilitates formation of a large-area substrate is provided. It is an object of the present invention to provide a method for manufacturing a semiconductor device using the formed substrate without the step of depositing an impurity layer and the number of steps is small. Another object of the present invention is to provide a method for manufacturing a semiconductor device having a channel region and a low resistance between a source and a drain. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can perform uniform processing on a large area substrate in a short time.

In order to achieve the above object, the present invention provides a substrate on which a silicon thin film is formed, at a position apart from a plasma space containing periodic group III element ions and hydrogen ions or periodic table group V element ions and hydrogen ions. By arranging and accelerating the group III element ions and hydrogen ions of the periodic table or the group V element ions and hydrogen ions of the periodic table from the plasma space, selectively using a mask formed on the silicon thin film. A method for manufacturing a semiconductor device, characterized in that the group III element ion and hydrogen ion of the periodic table or the group V element ion and hydrogen ion of the periodic table are introduced.

Further, the present invention uses the above method particularly for the regions to be the MOS type field effect source and drain regions of the inverted stagger structure using amorphous silicon formed on the insulating substrate.

Operation In the process technology of the present invention, hydrogen ions are introduced into the substrate at the same time as the impurity element ions, so that the impurities can be easily and surely injected into the amorphous silicon and the polycrystalline silicon which are integrated in a large area. That is, the technique used in the present invention uses a high-purity gas, extracts impurity element ions and hydrogen ions from the generated plasma, and irradiates the ions on the substrate heated to a predetermined temperature by low voltage acceleration in a shower shape to remove impurities. It is a new plasma process technology (ion shower doping technology) that introduces (doping). With this technology, the self-alignment technology used in the semiconductor LSI process can be applied to a large area, and the device performance is improved. Moreover, the process can be simplified, and control of polycrystalline silicon, formation of source / drain of amorphous silicon thin film transistor, formation of shallow electrode region, p, n
Arbitrary selective doping and the like can be easily performed, which is also suitable for manufacturing an optical sensor using amorphous silicon. In particular, in the case of amorphous silicon, hydrogen ions are implanted at the same time as the impurity implantation into the amorphous silicon, and defects induced during the impurity implantation can be compensated. Therefore, the heat treatment temperature is
It can be performed at low temperature where amorphous silicon does not crystallize,
It is possible to form a high quality impurity introduction layer and a junction.

Example First, the outline of the technique used in the present invention will be described. FIG. 1 is a conceptual diagram of this ion shower doping technique. For example, a vacuum container made of a quartz tube 1, a high-frequency power electrode 2 applied to the outside, and an external magnetic field formed by an electromagnet 3 are provided. For example, H ₂ diluted PH ₃ gas introduced into the vacuum container 1 is excited by an electromagnetic field. And accelerate the generated phosphorus ions 4 and hydrogen ions 5,
The sample 10 placed on the substrate stage 6 is selectively doped using the mask 7.

The sample 10 is the amorphous silicon semiconductor layer 9 formed on the insulating substrate 8. 10 indicates a neutral molecule.

As shown in Fig. 2, the apparatus for ion shower doping applies a high frequency of 13.56 megahertz (1 mega = 10 ⁶ ) and a magnetic field to the discharge chamber to apply ions in the excited plasma to a voltage of 1 to 10 kilovolts. The large area integrated device 10 (sample in FIG. 1) heated to a predetermined temperature is irradiated with ions in a shower shape. This device
Since the excitation of ions is performed using a high frequency power source,
Amorphous silicon was used because a uniform plasma can be created, a large area can be collectively processed, and a high-current ion beam can be obtained by applying a magnetic field.
When implanting impurities into the A4 size thin film transistor, the processing time can be about 1 minute. Also, the device configuration is much simpler than that of the ion implantation device. Reference numeral 1 is a quartz tube constituting a vacuum container, for example, 2% when diluted with hydrogen introduced from the gas introduction tube 12
A plasma containing at least phosphorous ions 4 and hydrogen ions 5 excited by a high-frequency electrode 2 and an electromagnet 3 installed outside the quartz tube 1 while maintaining the PH ₃ gas of 10 ^-4 Torr while exhausting it with a vacuum pump. To form. Reference numeral 13 is an insulator flange that uses vinyl chloride to insulate the discharge chamber and the chamber 15 including the substrate table 14. The electrode 16 vacuum-seales the quartz tube and is applied with a DC voltage (1 to 10 KV). 17
In the present device, another electrode is kept at the same potential as the electrode 16, but of course a positive voltage may be applied to the electrode 16. 18
Is an AC power source for heating the substrate table 14, and a sample on which the large-area integrated device 10 is to be formed is placed on the substrate table 14.

Depending on the material and structure of the element, this heating means may not be used.

Reference numeral 19 is a vacuum flange, 20 is a heater, 21 is an opening, and 22 is an ionization vacuum gauge.

The features of this device are as follows: 1) Doping into large area integrated devices such as A size is possible.

2) The device configuration is extremely simple and inexpensive. (Approximately one-third or less of ion implantation equipment) 3) High-efficiency ionization method using magnetic field is used, so a high-current ion beam can be obtained and doping can be performed in a short time of about 1 minute at A size. It is possible.

4) Ion irradiation can be performed with an acceleration energy of 10 KeV or less, and a high-concentration shallow doping layer (up to 20 nm) can be formed.

5) Since selective doping using a mask such as an organic photosensitive material is possible, it is possible to simplify the process especially in an amorphous silicon device and manufacture a device having a new structure.

This new plasma process technology facilitates the mass production of large area long devices with thin film transistors and sensors integrated, and is important for creating key devices for input and display of OA equipment, image processing terminal equipment, etc. It becomes basic technology.

 The following table shows a comparison table of doping technologies.

Further, as shown in FIG. 3, selective doping for forming an arbitrary p-type / n-type conductive layer in an arbitrary region can be performed shallowly, so that the application region of the amorphous silicon device can be dramatically expanded. Become.

FIG. 3A schematically shows the conventional ion implantation method, and FIG. 3B schematically shows the ion shower method of this embodiment. In the case of FIG. 3A, only the impurity ions are implanted into the semiconductor thin film, and when the impurities are implanted, the bonds between the elements are broken to generate defects, and the number of defects is several hundreds with respect to one impurity ion. it is conceivable that.

On the other hand, in the case of FIG. 3B as well, it seems that a defect similarly occurs. However, in the case of the ion shower method of the present embodiment, hydrogen ions are also implanted together with the impurity ions, and it is considered that the hydrogen ions play a role of compensating for defects caused by the implantation of the impurity ions.

In particular, when the semiconductor thin film is amorphous silicon, hydrogen is introduced into the thin film from the beginning, and it seems that it plays a role of defect compensation, but the number of defects generated by the introduction of one impurity ion is large. Therefore, the defects contained in the thin film from the beginning cannot be sufficiently compensated, and the defects can be sufficiently compensated by implanting hydrogen ions at the same time as the impurity ion implantation. This allows the subsequent heat treatment step to be performed at a low temperature.

When the thin film 9 is amorphous silicon, the ion implantation method of FIG. 3A has a temperature at which the amorphous silicon is crystallized when a necessary heat treatment is performed after the ion implantation. Not applicable. On the other hand, in the ion shower method of FIG. 3B, since the hydrogen ions are used for the doping together with the impurity ions, the heat treatment step after the ion shower can be performed at a temperature at which the amorphous silicon is not crystallized. Therefore, the ion shower method can also be applied to amorphous silicon.

Next, a case where the above device is used to apply to the production of a thin film transistor using amorphous silicon will be described.

In FIG. 4A, 8 is a glass substrate, 30 is a metal gate electrode of Cr or the like, and has a channel length of 10 μ, for example. A gate insulating film 31 is a P-CVD method using a mixed gas of SiH ₄ gas and NH ₃ gas to form a SiN film of about 3000 Å at a substrate temperature of 300 ° C. 9 is an active layer of the transistor, that is, the channel part and the source / drain part.
Form. Reference numeral 32 is a passivation film, which is similarly formed by P-CVD to form a SiN film of about 3000 Å at a substrate temperature of 250 ° C. Then, after applying a photosensitive resin film, the passivation film 32 is photo-etched to leave a part as shown in FIG. 4B. The dimension in the channel length direction at this time is, for example, 5 μ.

Then, using the film 32 left behind as a mask, impurities are introduced into the amorphous silicon by using the ion shower doping technique described above. First, the case of introducing n-type impurities will be described. PH ₃ gas diluted with hydrogen is introduced into the discharge chamber and discharged. As an example of the discharge condition at this time, the external high frequency power is 2 to 10 W
The external magnetic field was 50 gauss and the vacuum degree was 5 × 10 ^-4 Torr. Further, when the PH ₃ concentration of hydrogen dilution is 0.5%, when the amorphous silicon 9 is irradiated with the ion shower 32 accelerated at 3.5 KeV at a substrate temperature of 300 ° C. at a position about 15 cm away from the outlet of the discharge chamber, impurities Etching of amorphous silicon occurred simultaneously with the introduction of When the PH ₃ concentration was 2%, the doping was predominant and etching was hardly observed. Further, when the PH ₃ concentration was 10%, P was deposited on the amorphous silicon film.
When the thickness of the amorphous silicon 9 is 1000Å and the ion acceleration energy is 3.5 KeV, the P doping depth (projection range) is about 50Å, so even if the distribution is wide, The high concentration layer 34 (above the dotted line) is formed only in the surface region of the crystalline silicon film. When the thickness of amorphous silicon is thin, for example, 500 Å, the acceleration energy of ions is 10 KeV, and the peak concentration is 10 ²⁰ / cm ³ , the concentration of amorphous silicon 9 at a depth of 500 Å is 10 ¹⁵ / cm.
It becomes ³ .

As shown in FIG. 4C, which follows FIG. 4B, the source / drain electrodes 35 and 36 are formed after removing the amorphous silicon except for the transistor portion of 9.

By the above method, not only the process steps can be remarkably simplified and the area can be increased easily, but as shown in FIG. 5, a high resistance region of amorphous silicon between the source / drain high concentration region layer 34 and the channel 37 can be obtained. Is less. That is, the source region having a depth of l ₁ is formed in the amorphous silicon 9, the distance between the source and the channel can be shortened to l _2, and the resistance R can be reduced.

Conventionally, when a necessary heat treatment is performed on amorphous silicon after performing ion implantation, the temperature reaches a temperature at which the amorphous silicon is crystallized, so that the source region cannot be formed by ion implantation. Therefore, the source was deposited and formed on the amorphous silicon 9, and the resistance R could not be reduced. However, in the ion shower method of the present invention, since hydrogen ions are used for doping together with impurity ions, the heat treatment step after the ion shower can be performed at a temperature at which amorphous silicon is not crystallized.
There is no need to deposit the source.

Further, by optimizing parameters such as the film thickness of the amorphous silicon 9, the ion acceleration energy, and the substrate temperature, the source / drain regions can be formed over the entire thickness of the amorphous silicon, so that the loss of the input signal is mitigated. In addition, the effect of improving the switching speed of the amorphous thin film transistor can be obtained. Further, hydrogen ions are simultaneously implanted together with the doping of the impurity ions, so that the electrical characteristics due to the defects generated at the time of doping the impurities are compensated, which is suitable for the amorphous silicon which needs to contain hydrogen. At this time, there is an optimum value for the amount of hydrogen ions. When introducing impurities using PH ₃ , 0.5 to 10% in hydrogen is optimal, but for example, when PH ₃ gas is diluted in He gas, hydrogen ions may be doped separately from P doping. . The same applies when using PF ₃ gas. Of course, even in the case of PH ₃ gas diluted with hydrogen, it is needless to say that the treatment may be performed in a separate step of hydrogen ion doping or hydrogen or plasma discharge containing hydrogen.

FIG. 6 shows an embodiment in which the source / drain regions are formed in a self-aligned manner by using this technique using polycrystalline silicon or amorphous silicon. FIG. 6 shows, for example, a quartz glass substrate, 50 is about 2000Å polycrystalline silicon formed by the low pressure CVD method, 51 is a gate insulating film of ~ 1000Å thermal oxide film, and 52 is about 3000.
Å The gate is polycrystalline silicon. As shown in Fig. 6, after patterning, self-aligned, for example, 2% PH by hydrogen dilution
Ions are accelerated at 6 KeV from the plasma discharge of ₃ gases, and impurities are introduced as an ion shower as shown by the arrow. Then, anneal at 900 ° C. for 30 minutes in N ₂ gas. After that, a transistor is formed by a usual method. According to this method, even in a large area substrate, uniform and entire doping can be performed simultaneously without the need for ion shower scanning.

When amorphous silicon instead of polycrystalline silicon is used for the active layer, it is used as a gate insulating film by photo-CVD or ECR plasma CV.
An insulating film formed by the D method is used in place of the thermal oxide film, and aluminum, another metal, or metal silicide is used as a gate electrode to form a pattern as shown in FIG. 6, and then the substrate is heated at 200 to 300 ° C. and ion shower doped. This makes it possible to easily create a transistor.

When the technique of the present invention is applied to the production of a thin film transistor using polycrystalline silicon, as shown in FIG. 3, grains of polycrystalline silicon by ion shower extracted from formation of source / drain regions or plasma discharge of hydrogen gas. It can be applied to field (Note 2) control. An example of electrical characteristics of the thin film transistor is shown in FIG.

Further, in order to confirm the usefulness of the plasma process technology of the present invention, an optical line sensor using amorphous silicon and a thin film transistor using polycrystalline silicon were integrated on a quartz substrate to fabricate an integrated line sensor. With regard to the transistor, on / off characteristics of 5 digits or more were obtained, and a drive circuit by this transistor and a sensor were integrated to obtain a photocurrent / dark current ratio of 2 digits or more. The structure and characteristics of this element are shown in FIG.

The present invention is not only applied to the formation of the source / drain of a MOS transistor, but as shown in FIG. 3, the acceleration energy of ions during doping is lower than that in the case of conventional ion implantation. Can be used to form an extremely shallow high-concentration impurity layer in an arbitrary region. For example, when the semiconductor thin film is amorphous silicon and the mask material is a silicon nitride film, the ion acceleration energy is 3.5 KeV,
By doping with P atoms at 5 × 10 ¹⁴ / cm ² and a substrate temperature of 250 ° C., a layer having a conductivity of −10 ⁻³ (Ω · cm) ⁻¹ at −200 Å or less was formed. For comparison, when the ion implantation method is used, the thickness is usually 0.1 μm or more.

Further, in the present invention, P, n is an arbitrary periodic table V
It can be applied to the introduction of group III elements.

EFFECTS OF THE INVENTION Since hydrogen ions are doped at the same time as Group III or Group V ions of the periodic table, defects induced at the time of impurity implantation can be compensated, and low-temperature heat treatment can be performed. In particular,
Impurities can be introduced into a substrate on which amorphous silicon is formed, which is easy to form a large-area substrate, without using a deposition method, and the number of steps can be reduced. In addition, the resistance can be reduced by reducing the distance between the channel region of the transistor and the source / drain. Furthermore, by generating ions by discharge decomposition with high-frequency power under application of a magnetic field, a uniform plasma and a high-current ion beam can be provided, so that impurities can be uniformly introduced into a large-area substrate in a short time. .

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an impurity introduction method by an ion shower system used in the present invention, FIG. 2 is a schematic diagram of an ion shower doping apparatus, FIG. 3 (A) is a state diagram of an ion implantation method,
FIG. 3B is a state diagram of an ion shower system, FIGS. 4A to 4C are cross-sectional views of a manufacturing process of a thin film transistor of one embodiment of the present invention, and FIG. 5 is a sectional view of FIG. FIG. 6 is a partial enlarged cross-sectional view of a transistor, FIG. 6 is a cross-sectional view of a manufacturing process of a polycrystalline silicon transistor, FIG. 7 is an electrical characteristic diagram of a thin film transistor, and FIG. 8A is an integrated plan view of an amorphous silicon sensor and a thin film transistor. FIG. 8 (B) is a sectional view taken along line XX ′ of FIG. 8 (A), FIG. 8 (C) is a characteristic diagram of FIG. 8 (A), and FIGS. 9 (A) to 9 (D) are conventional amorphous materials. FIG. 6 is a process cross-sectional view of a high-quality silicon thin film transistor. 3 ... electromagnet, 4 ... phosphorus ion, 5 ... hydrogen ion,
8 ... Insulating substrate, 9 ... Amorphous silicon semiconductor layer, 10 ...
… Mask, 34 …… High-concentration impurity introduction layer.

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Claims (4)

(57) [Claims] 1. A substrate is provided with a plasma space containing an impurity containing a Group III element or a Group V element of the periodic table and hydrogen ions in a container, and extracting impurity ions and hydrogen ions from the plasma space. Irradiation is performed on the polycrystalline or amorphous silicon thin film formed above, and the impurities are selectively applied to the polycrystalline or amorphous silicon thin film by using a mask formed on the polycrystalline or amorphous silicon thin film. A method for manufacturing a semiconductor device, which comprises simultaneously introducing ions and hydrogen ions. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity ions and hydrogen ions are generated by discharge decomposition with high-frequency power. 3. The method of manufacturing a semiconductor device according to claim 1, wherein impurity ions and hydrogen ions are generated by discharge decomposition with high frequency power under application of a magnetic field. 4. The silicon thin film is amorphous silicon, the source gas for generating group V ions is PH ₃ diluted with hydrogen gas, and its concentration is in the range of more than 0.5% and less than 10%. The method for manufacturing a semiconductor device according to claim 1, wherein