JPH08212133A - データ処理装置及びキャッシュメモリ制御方法 - Google Patents

データ処理装置及びキャッシュメモリ制御方法

Info

Publication number
JPH08212133A
JPH08212133A JP7034422A JP3442295A JPH08212133A JP H08212133 A JPH08212133 A JP H08212133A JP 7034422 A JP7034422 A JP 7034422A JP 3442295 A JP3442295 A JP 3442295A JP H08212133 A JPH08212133 A JP H08212133A
Authority
JP
Japan
Prior art keywords
data
write
cache
buffer
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7034422A
Other languages
English (en)
Japanese (ja)
Inventor
Toshihiko Kurihara
俊彦 栗原
Kenji Matsubara
健二 松原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7034422A priority Critical patent/JPH08212133A/ja
Priority to TW084113646A priority patent/TW296442B/zh
Priority to KR1019960001988A priority patent/KR960029986A/ko
Publication of JPH08212133A publication Critical patent/JPH08212133A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/282—Partitioned cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP7034422A 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法 Withdrawn JPH08212133A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP7034422A JPH08212133A (ja) 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法
TW084113646A TW296442B (enExample) 1995-01-31 1995-12-20
KR1019960001988A KR960029986A (ko) 1995-01-31 1996-01-30 데이타처리장치 및 캐쉬메모리제어방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7034422A JPH08212133A (ja) 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法

Publications (1)

Publication Number Publication Date
JPH08212133A true JPH08212133A (ja) 1996-08-20

Family

ID=12413777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7034422A Withdrawn JPH08212133A (ja) 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法

Country Status (3)

Country Link
JP (1) JPH08212133A (enExample)
KR (1) KR960029986A (enExample)
TW (1) TW296442B (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049395A1 (fr) * 1998-03-23 1999-09-30 Hitachi, Ltd. Controleur de memoire tampon
KR100794312B1 (ko) * 2006-12-27 2008-01-11 삼성전자주식회사 명령어 자동 처리 유니트를 포함한 메모리 컨트롤러 및그를 포함한 메모리 시스템
JPWO2012093475A1 (ja) * 2011-01-05 2014-06-09 富士通株式会社 情報転送装置および情報転送装置の情報転送方法
US12105629B2 (en) 2022-07-25 2024-10-01 Samsung Electronics Co., Ltd. Adaptive cache indexing for a storage device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049395A1 (fr) * 1998-03-23 1999-09-30 Hitachi, Ltd. Controleur de memoire tampon
KR100794312B1 (ko) * 2006-12-27 2008-01-11 삼성전자주식회사 명령어 자동 처리 유니트를 포함한 메모리 컨트롤러 및그를 포함한 메모리 시스템
US8060669B2 (en) 2006-12-27 2011-11-15 Samsung Electronics Co., Ltd. Memory controller with automatic command processing unit and memory system including the same
JPWO2012093475A1 (ja) * 2011-01-05 2014-06-09 富士通株式会社 情報転送装置および情報転送装置の情報転送方法
US12105629B2 (en) 2022-07-25 2024-10-01 Samsung Electronics Co., Ltd. Adaptive cache indexing for a storage device

Also Published As

Publication number Publication date
TW296442B (enExample) 1997-01-21
KR960029986A (ko) 1996-08-17

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20020402