WO1999049395A1 - Controleur de memoire tampon - Google Patents

Controleur de memoire tampon Download PDF

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Publication number
WO1999049395A1
WO1999049395A1 PCT/JP1998/001233 JP9801233W WO9949395A1 WO 1999049395 A1 WO1999049395 A1 WO 1999049395A1 JP 9801233 W JP9801233 W JP 9801233W WO 9949395 A1 WO9949395 A1 WO 9949395A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
request
store
buffer
address
Prior art date
Application number
PCT/JP1998/001233
Other languages
English (en)
Japanese (ja)
Inventor
Ichiki Honma
Hiroshi Kurokawa
Shinichi Mihashi
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001233 priority Critical patent/WO1999049395A1/fr
Publication of WO1999049395A1 publication Critical patent/WO1999049395A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Definitions

  • the present invention relates to a buffer storage control method, and more particularly to a control method suitable for a stored-type buffer storage.
  • One of the methods for speeding up data reference using a buffer memory that holds a part of the data in the main memory is a strain method.
  • FIG. 2 shows a conventional technique, which is a control method in which a part of data of a main memory 41 is stored in a buffer memory 30 in a stored manner.
  • Requests from the central processing unit are held in the request code register queue 1 and processed on a first-in first-out (FIFO) basis.
  • Address information corresponding to the request code register queue 1 is held in the address register queue 2 and store data is stored in the store data register queue 3, respectively.
  • the buffer address array 6 stores the address of data stored in the buffer memory in the main memory, and is controlled by, for example, a direct mapping method.
  • the buffer register 20 is a high-speed buffer installed between the main memory 41 and the buffer memory 30, temporarily holds the line transfer data, and stores the data in the buffer register 20 after all the line transfer data has been collected. The contents are written to buffer memory 30.
  • the request (ST0) extracted from the request code register queue 1 at time tO is determined by the request decoder 5 as a store request.
  • the store data is extracted from the address register queue 2 and the store data from the store data register queue 3.
  • a part of the address (column address) is sent to the buffer address array 6, and the address capacity is changed.
  • the hit determination circuit 10 determines whether or not the data exists in the buffer memory 30.
  • the column address is also sent to the address register 32 through the selector 36 at the same time, and the buffer memory 30 is stored. Since this case is a hit case, the hit judgment result 51 ⁇ s' rises, and the buffer storage access control unit 14 selects the selector 37 based on the hit judgment result 51.
  • the buffer storage writes the store data at time tl, and ST0 is completed.
  • the request (ST1) extracted from the request code register queue 1 refers to the buffer address array 6 in the same procedure.
  • the hit determination result 5 1 5 does not stand because this case is a mistake case.
  • the buffer memory access control unit 1 4 is set to write inhibit information to the control register 3 1 receives that no stand 5 1 force s, not written Sutoade one Taka s in the buffer memory at time t2
  • the buffer register access control unit 12 sets the stored data in the buffer register 20 at time t2 in response to the fact that it does not stand for 51 seconds, and at the same time, corresponds to the store destination position in the change bit 21.
  • the line transfer control unit 13 issues a request to the main memory access control unit 40 in response to the fact that 51 does not stand up, and at the same time, sends the address during line transfer to the line transfer address register 7. , Set each.
  • the main memory access control unit 40 activates the main memory 41, and the line transfer data is transferred from the main memory 41 to the buffer register 20 between times t4 and t5.
  • the buffer register access control unit 12 sets the line transfer data in the buffer register 20 between the time t5 and the time t6, but already uses the output of the change bit 21 to set the line transfer data. Control the bytes to which the store data is written so that they are not overwritten by the line transfer data.
  • the line transfer control unit 13 activates the buffer storage access control unit 14.
  • the buffer storage access control unit 14 receives this, and transfers the contents of the buffer register 20 to the write register 33, the write request to the control register 31 and the address to select and replace the selector 36. 2, each set.
  • the buffer memory 30 writes the line transfer data at time t7.
  • the contents of the line transfer address register 7, which is the address of the line transfer are set in the buffer address array 6, and at time t7, the line transfer address register 7 is reset. Complete.
  • the contents of the line transfer address register 7, buffer register 20 and change bit 21 become invalid and are not used until the next line transfer is started. That line transfer address register 7, Roh Ffareji Star 2 0, is changed bit 2 1 force s effective time from the time t2 to t6.
  • the request (ST1) that activated the line transfer can be processed at high speed. If the request (ST2) following the ST1 is a store request and matches the column address during the line transfer, Did not process the request until the line transfer was completed.
  • the request (ST2) is determined to be a store request by the request decoder 5 at time t2, and the address of the store request is compared with the contents of the line transfer address register 7 by the column conflict determination circuit 15.
  • the request cutout control unit 4 has suppressed the cutout of the request.
  • the capacity of the main memory 41 is 4 gigabytes
  • the capacity of the buffer storage is 1 megabyte
  • the data length (line size) transferred to the buffer storage 30 in one line transfer is 25.
  • the address registered in the address register queue 2 consists of the following three parts. That is, the upper address indicated by the address bits (0,0) to (1,3), the column address indicated by the address bits (1,4) to (2,7), and the address bit (3, This is the address within the line indicated by (0) to (3, 7).
  • the parts registered in the line transfer address register 7 are the upper addresses (0,0) to (3) and the column addresses (1,4) to (2,7).
  • the column conflict judgment circuit 15 has a column register in address register queue 2 When the address part 202 and the column address part 72 of the line transfer address register 7 are input, and both addresses match, the power is raised 53.
  • the section in which the request (ST2) cut-out force 5 ′ is suppressed due to such a conflict with the column address during line transfer is a section in which line transfer is executed, that is, the time when the line transfer address register 7 is valid.
  • line transfer is completed in 5 processing times from time t2 to t6, and if the processing time required for line transfer increases due to factors such as an increase in the amount of transfer data in line transfer, the At the same time, the time at which the subsequent request is cut out is delayed, which eventually leads to a reduction in the processing performance of the entire processing apparatus.
  • An object of the present invention is to make it possible to cut out a store request and store a store request for a store request following a request that has activated a line transfer, even if the address matches the address performing the line transfer. And to improve the performance of the entire processing apparatus. Disclosure of the invention
  • the present invention relates to a buffer storage control device for controlling buffer storage by a string method, a means for comparing an address being transferred in a line with an address of a subsequent request, and a line transfer when the address power is 5 '.
  • FIG. 1 is a block diagram of a first embodiment of the present invention
  • FIG. 2 is a block diagram of a conventional technique
  • FIG. 3 is a block diagram of a second embodiment of the present invention
  • FIG. FIG. 5 is a time chart (No. 1) in the first embodiment of FIG. 1
  • FIG. 6 is a time chart in the second embodiment of FIG.
  • FIG. 7 is a time chart (No. 2) in the first embodiment of FIG. 1
  • FIG. 8 is a diagram showing a method of determining a column conflict
  • FIG. 9 is a diagram showing a determination of an address conflict. It is a figure showing a method. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a first embodiment of the present invention.
  • the hit determination result 51 is not set in this case because it is a miss case.
  • the buffer memory access control unit 1 4 writes inhibition information to the control register 3 1 accepted by that no stand 5 1 force s hit determination result and set, at time t2 to Bruno Ffa Symbol ⁇ to so as not written power of s.
  • the buffer register ⁇ habit scan control unit 1 2 in response to the fact that not stand 5 1 force s hit determination result, at time t2 and at the same time set the strike Ade Ichita the buffer register 2 0, the change bit 2 1 Set the bit corresponding to the byte position of the middle store destination to 1 so that the store data will not be overwritten by the line transfer data.
  • the line transfer control unit 13 issues a request to the main memory access control unit 40 in response to the hit determination result 51 not being established, and also issues a line transfer address. Set the address during line transfer to register 7.
  • the main memory access control unit 40 activates the main memory 41, and the line transfer data is transferred from the main memory 41 to the buffer register 20 between times t4 and t5.
  • the buffer register access control unit 12 uses the output s of the line transfer data in the buffer register 20 between the time t5 and t6 to set the line transfer data and the output of the change bit 21 when the line transfer data is set.
  • the part that has been written door Adeta force s is controlled to like not such a go-between by overwriting the Rain transfer de one data.
  • the request (ST2) existing in the request code register queue 1 at time t2 is determined by the request decoder 5 to be a store request.
  • the contents of the line transfer address register 7 are compared with the address of ST2 and they match, 52, which is the result of the address conflict determination circuit 11, stands.
  • the capacity of the main memory 41 is 4 gigabytes
  • the capacity of the buffer storage is 1 megabyte
  • the data length (line size) transferred to the buffer storage 30 in one line transfer is 256.
  • the address registered in the address register queue 2 is composed of the following three parts. That is, the upper address indicated by the address bits (0,0) to (3), the column address indicated by the address bits (1,4) to (2,7), and the address bits (3,0) to ( This is an in-line address indicated by (3, 7).
  • the parts registered in the line transfer address register 7 are the upper addresses (0,0) to (1,3) and the column addresses (1,4) to (2,7).
  • the address conflict judgment circuit 11 has an upper address portion 201 and a column address portion 202 of the address register queue 2 and an upper address portion 70 1 and a column address portion 70 2 of the line transfer address register 7. 5 Entered, both address power s — If they match, the result of the address conflict judgment is 5 2 ⁇ 1.
  • the buffer register access control unit 1 2 sends the ST2
  • the contents of the 'store data register queue 3' which is the ST2 store data
  • the notifier register 20 the contents of the 'store data register queue 3', which is the ST2 store data
  • a store request that caused an address conflict even during line transfer can be processed by writing to the buffer register, and when store data and line transfer data are set in the buffer register 20 at the same time.
  • the corresponding bit of the change bit 21 is set to 1 at the same time to prevent overwriting by the line transfer data.
  • requests s are extracted from the request code register queue 1 from the requests ST3 to ST5 and processed.
  • ST3 to ST5 are all store requests, and the address matches the address being transferred during line transfer.
  • the line transfer control unit 13 activates the buffer storage access control unit 14.
  • the buffer storage access control unit 14 receives this, and writes the contents of the buffer register 20 to the write register 33, the write request to the control register 31, and the selector 36 to select and replace the line.
  • the buffer memory 30 writes the line transfer data at time t7.
  • the address in the main memory which is the target of the line transfer, is written from the line transfer address register 7 into the buffer address array 6, and the line transfer address register 7 is reset to perform a series of line transfers. Is completed.
  • the contents of the line transfer address register 7, the buffer register 20 and the change bit 21 become invalid and are not used until the next line transfer is started.
  • FIG. 1 a time chart in the case where the request following the request that activated the line transfer is a fetch and the address matches the address of the preceding store request is shown in FIG.
  • the operation of the fetch request (FT) at time t2 will be described. It is assumed that the FT existing in the request code register queue 1 at time t2 matches the address of ST1. Therefore, a comparison with the line transfer address register 7 gives an address conflict determination result 52.
  • the request cutout control unit 4 receives the fact that the FT is a fetch request from the request decoder 5 and that the FT is up to 52 s, and suppresses the cutout of the FT. This state continues until time t5 is a line transfer address register 7 force s effective, for updating the time t6 the buffer address array 6, actually become the FT force s possible cut becomes time t7 or later.
  • FIG. 3 shows a second embodiment of the present invention.
  • the difference between the present embodiment and the embodiment of FIG. 1 is that there is no buffer register 20 between the main memory 41 and the buffer memory 30 and there is no buffer register access control unit 12 and the light register 33 is The point is that write register A 34 and write register B 35 are used to support 2-port input. That is, with this change, the line transfer data is directly transferred from the main memory 41 to the buffer memory 30 via the write register B 35, and the write register A 34 can be written at the same time. Store data in the You.
  • FIG. 5 shows that when the store request (ST1) at time tl starts line transfer, the store data is set in the buffer register 20 in FIG. 5 ', FIG. 6 shows that data is written directly into the buffer memory 30, and that the line transfer data from the main memory 41 is written directly into the buffer memory 30.
  • the process of transferring data from the far register 20 to the buffer storage 30 can be omitted.
  • the update time of the buffer address array 6 to be t5
  • the time at which the store request (ST6) is cut out can be advanced as compared with the example of FIG.
  • the store data is written in parallel with the writing of the line transfer data.
  • Store processing can be performed without waiting for the completion of the transfer.
  • the throughput of the store processing is improved, and thus the throughput of the entire processing apparatus is improved.
  • the present invention relates to a storage device that performs control by the store-in method. Therefore, it is suitable for use in a buffer storage control device that improves the throughput of the entire storage device.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne un contrôleur de mémoire tampon commandant une mémoire tampon au niveau de la technique de mise en mémoire, lequel contrôleur est pourvu d'un dispositif permettant de comparer l'adresse en cours de transfert sur la ligne à l'adresse suivante d'une demande d'enregistrement, et d'un dispositif capable d'écrire en parallèle dans la mémoire tampon les données de transfert ligne et les données d'enregistrement en cas de concordance des données. Alors, la demande d'enregistrement suivante peut être traitée sans influence du temps de traitement sur la ligne de transfert, ce qui permet d'améliorer les performances du processeur dans son ensemble.
PCT/JP1998/001233 1998-03-23 1998-03-23 Controleur de memoire tampon WO1999049395A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001233 WO1999049395A1 (fr) 1998-03-23 1998-03-23 Controleur de memoire tampon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001233 WO1999049395A1 (fr) 1998-03-23 1998-03-23 Controleur de memoire tampon

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8312218B2 (en) 2006-02-27 2012-11-13 Fujitsu Limited Cache controller and cache control method
TWI760702B (zh) * 2020-03-03 2022-04-11 瑞昱半導體股份有限公司 資料寫入系統與方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111865A (ja) * 1984-06-27 1986-01-20 Hitachi Ltd メモリアクセス制御方式
JPH02259945A (ja) * 1989-03-31 1990-10-22 Fujitsu Ltd ストア処理方式
JPH08212133A (ja) * 1995-01-31 1996-08-20 Hitachi Ltd データ処理装置及びキャッシュメモリ制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111865A (ja) * 1984-06-27 1986-01-20 Hitachi Ltd メモリアクセス制御方式
JPH02259945A (ja) * 1989-03-31 1990-10-22 Fujitsu Ltd ストア処理方式
JPH08212133A (ja) * 1995-01-31 1996-08-20 Hitachi Ltd データ処理装置及びキャッシュメモリ制御方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8312218B2 (en) 2006-02-27 2012-11-13 Fujitsu Limited Cache controller and cache control method
TWI760702B (zh) * 2020-03-03 2022-04-11 瑞昱半導體股份有限公司 資料寫入系統與方法

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