WO1999049395A1

WO1999049395A1 - Buffer memory controller

Info

Publication number: WO1999049395A1
Application number: PCT/JP1998/001233
Authority: WO
Inventors: Ichiki Honma; Hiroshi Kurokawa; Shinichi Mihashi
Original assignee: Hitachi, Ltd.
Priority date: 1998-03-23
Filing date: 1998-03-23
Publication date: 1999-09-30

Abstract

A buffer memory controller that controls a buffer memory by the store-in method, which is provided with a means for comparing the address being transferred on line and the subsequent address of a store request and a means for writing, parallely in the buffer memory, the line transfer data and the store data when the data match. Thus the subsequent store request can be processed with no influence by the processing time on the line transfer, and thereby the processing performance of the entire processor can be improved.

Description

Technical field

The present invention relates to a buffer storage control method, and more particularly to a control method suitable for a stored-type buffer storage. Background art

One of the methods for speeding up data reference using a buffer memory that holds a part of the data in the main memory is a strain method.

In the store-in method, when a certain store request is not stored in the buffer capacity of the storage destination, a part of the corresponding main memory data is read in a certain unit (line) and transferred to the buffer storage (line transfer). ), And then writes the data of the strike request to the buffer storage.

The problem here is that the slower the main memory access speed is than the buffer memory access speed, the longer it takes to process the store request that activated the line transfer, and the The point is that the processing throughput force S decreases.

One of the methods for solving this problem is the technical capability shown in Japanese Patent Application Laid-Open No. S61-118865.

In other words, when a store request activates line transfer, the store request data is written to the buffer storage before the line transfer data is written to the buffer storage. Is to provide a function to prevent overwriting by line transfer data, thereby reducing the processing time by processing the request that started the line transfer without waiting for the completion of the line transfer. It is. FIG. 2 shows a conventional technique, which is a control method in which a part of data of a main memory 41 is stored in a buffer memory 30 in a stored manner.

Requests from the central processing unit (not shown) are held in the request code register queue 1 and processed on a first-in first-out (FIFO) basis. Address information corresponding to the request code register queue 1 is held in the address register queue 2 and store data is stored in the store data register queue 3, respectively.

The buffer address array 6 stores the address of data stored in the buffer memory in the main memory, and is controlled by, for example, a direct mapping method.

The buffer register 20 is a high-speed buffer installed between the main memory 41 and the buffer memory 30, temporarily holds the line transfer data, and stores the data in the buffer register 20 after all the line transfer data has been collected. The contents are written to buffer memory 30.

The operation of the prior art shown in FIG. 2 is shown in the time chart of FIG.

First, the operation in the case where the request address exists in the buffer memory (hit case) will be described.

The request (ST0) extracted from the request code register queue 1 at time tO is determined by the request decoder 5 as a store request. At this time, at the same time, the store data is extracted from the address register queue 2 and the store data from the store data register queue 3. A part of the address (column address) is sent to the buffer address array 6, and the address capacity is changed. The hit determination circuit 10 determines whether or not the data exists in the buffer memory 30. The column address is also sent to the address register 32 through the selector 36 at the same time, and the buffer memory 30 is stored. Since this case is a hit case, the hit judgment result 51 力 s' rises, and the buffer storage access control unit 14 selects the selector 37 based on the hit judgment result 51. Set store data to write register 33 and write signal to control register 31 I do. The buffer storage writes the store data at time tl, and ST0 is completed.

Next, the operation when the request does not exist in the addressless buffer storage (mis-case) will be described.

At time tl, the request (ST1) extracted from the request code register queue 1 refers to the buffer address array 6 in the same procedure. As a result, the hit determination result 5 1 ⁵ does not stand because this case is a mistake case. In this case, the buffer memory access control unit 1 4 is set to write inhibit information to the control register 3 1 receives that no stand 5 1 force ^s, not written Sutoade one Taka ^s in the buffer memory at time t2 Like On the other hand, the buffer register access control unit 12 sets the stored data in the buffer register 20 at time t2 in response to the fact that it does not stand for 51 seconds, and at the same time, corresponds to the store destination position in the change bit 21. Set the bit of the part (for example, one byte unit) to 1 to 1 so that the store data is not overwritten by the line transfer data. In parallel with this, the line transfer control unit 13 issues a request to the main memory access control unit 40 in response to the fact that 51 does not stand up, and at the same time, sends the address during line transfer to the line transfer address register 7. , Set each. The main memory access control unit 40 activates the main memory 41, and the line transfer data is transferred from the main memory 41 to the buffer register 20 between times t4 and t5. The buffer register access control unit 12 sets the line transfer data in the buffer register 20 between the time t5 and the time t6, but already uses the output of the change bit 21 to set the line transfer data. Control the bytes to which the store data is written so that they are not overwritten by the line transfer data.

When all the line transfer data is set in the buffer register 20 at time t6, the line transfer control unit 13 activates the buffer storage access control unit 14. The buffer storage access control unit 14 receives this, and transfers the contents of the buffer register 20 to the write register 33, the write request to the control register 31 and the address to select and replace the selector 36. 2, each set. The buffer memory 30 writes the line transfer data at time t7. At time t6, the contents of the line transfer address register 7, which is the address of the line transfer, are set in the buffer address array 6, and at time t7, the line transfer address register 7 is reset. Complete. After the time t7 when the line transfer is completed, the contents of the line transfer address register 7, buffer register 20 and change bit 21 become invalid and are not used until the next line transfer is started. That line transfer address register 7, Roh Ffareji Star 2 0, is changed bit 2 1 force ^s effective time from the time t2 to t6.

In the above-mentioned conventional technology, the request (ST1) that activated the line transfer can be processed at high speed. If the request (ST2) following the ST1 is a store request and matches the column address during the line transfer, Did not process the request until the line transfer was completed.

That is, in FIG. 4, the request (ST2) is determined to be a store request by the request decoder 5 at time t2, and the address of the store request is compared with the contents of the line transfer address register 7 by the column conflict determination circuit 15. When the signal 53 indicating the coincidence is raised, the request cutout control unit 4 has suppressed the cutout of the request.

The method of comparing the address will be described with reference to FIG.

In the case of this conventional technology, for example, the capacity of the main memory 41 is 4 gigabytes, the capacity of the buffer storage is 1 megabyte, and the data length (line size) transferred to the buffer storage 30 in one line transfer is 25. If it is 6 bytes, the address registered in the address register queue 2 consists of the following three parts. That is, the upper address indicated by the address bits (0,0) to (1,3), the column address indicated by the address bits (1,4) to (2,7), and the address bit (3, This is the address within the line indicated by (0) to (3, 7). Of these, the parts registered in the line transfer address register 7 are the upper addresses (0,0) to (3) and the column addresses (1,4) to (2,7). Here, the address bits ( _a , b) mean “b bits in a byte”. The column conflict judgment circuit 15 has a column register in address register queue 2 When the address part 202 and the column address part 72 of the line transfer address register 7 are input, and both addresses match, the power is raised 53.

The section in which the request (ST2) cut-out force ⁵ ′ is suppressed due to such a conflict with the column address during line transfer is a section in which line transfer is executed, that is, the time when the line transfer address register 7 is valid. In this configuration, line transfer is completed in 5 processing times from time t2 to t6, and if the processing time required for line transfer increases due to factors such as an increase in the amount of transfer data in line transfer, the At the same time, the time at which the subsequent request is cut out is delayed, which eventually leads to a reduction in the processing performance of the entire processing apparatus.

An object of the present invention is to make it possible to cut out a store request and store a store request for a store request following a request that has activated a line transfer, even if the address matches the address performing the line transfer. And to improve the performance of the entire processing apparatus. Disclosure of the invention

The present invention relates to a buffer storage control device for controlling buffer storage by a string method, a means for comparing an address being transferred in a line with an address of a subsequent request, and a line transfer when the address power is ⁵ '. by providing a possible force ^s possible means for writing data and strike Adeta the buffer memory in parallel, to process subsequent Sutari Kuesu bets without being affected by the processing time in the line transfer, the entire processing apparatus processing performance Improve. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a conventional technique, FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. FIG. 5 is a time chart (No. 1) in the first embodiment of FIG. 1, and FIG. 6 is a time chart in the second embodiment of FIG. FIG. 7 is a time chart (No. 2) in the first embodiment of FIG. 1, FIG. 8 is a diagram showing a method of determining a column conflict, and FIG. 9 is a diagram showing a determination of an address conflict. It is a figure showing a method. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.

FIG. 1 shows a first embodiment of the present invention.

The difference from the prior art of FIG. 2 is that the column conflict determination circuit 15 is replaced with the address conflict determination circuit 11 and that the buffer register access control unit 12 has an address conflict determination circuit 11. And the signal from the request decoder 5 is added.

The operation in the embodiment of FIG. 1 is shown in the time chart of FIG.

Since the request (ST0) at time tO is a hit case, it is the same as the operation of the conventional technique shown in FIG.

Next, a miss case will be described.

As a result of the request (ST1) extracted from the request code register queue 1 at the time referring to the buffer address array 6 in the same procedure, the hit determination result 51 is not set in this case because it is a miss case. Sutadeta this case, the buffer memory access control unit 1 4 writes inhibition information to the control register 3 1 accepted by that no stand 5 1 force ^s hit determination result and set, at time t2 to Bruno Ffa Symbol憶to so as not written power of ^s. On the other hand, the buffer register § habit scan control unit 1 2 in response to the fact that not stand 5 1 force ^s hit determination result, at time t2 and at the same time set the strike Ade Ichita the buffer register 2 0, the change bit 2 1 Set the bit corresponding to the byte position of the middle store destination to 1 so that the store data will not be overwritten by the line transfer data. In parallel with this, the line transfer control unit 13 issues a request to the main memory access control unit 40 in response to the hit determination result 51 not being established, and also issues a line transfer address. Set the address during line transfer to register 7. The main memory access control unit 40 activates the main memory 41, and the line transfer data is transferred from the main memory 41 to the buffer register 20 between times t4 and t5. The buffer register access control unit 12 uses the output ^{s of} the line transfer data in the buffer register 20 between the time t5 and t6 to set the line transfer data and the output of the change bit 21 when the line transfer data is set. the part that has been written door Adeta force ^s is controlled to like not such a go-between by overwriting the Rain transfer de one data.

The following shows the procedure for processing the request.

It is assumed that the request (ST2) existing in the request code register queue 1 at time t2 is determined by the request decoder 5 to be a store request. At this time, if the contents of the line transfer address register 7 are compared with the address of ST2 and they match, 52, which is the result of the address conflict determination circuit 11, stands.

The method of comparing the address will be described with reference to FIG.

In the case of the present embodiment, for example, the capacity of the main memory 41 is 4 gigabytes, the capacity of the buffer storage is 1 megabyte, and the data length (line size) transferred to the buffer storage 30 in one line transfer is 256. It can be understood that the address registered in the address register queue 2 is composed of the following three parts. That is, the upper address indicated by the address bits (0,0) to (3), the column address indicated by the address bits (1,4) to (2,7), and the address bits (3,0) to ( This is an in-line address indicated by (3, 7). Of these, the parts registered in the line transfer address register 7 are the upper addresses (0,0) to (1,3) and the column addresses (1,4) to (2,7).

The address conflict judgment circuit 11 has an upper address portion 201 and a column address portion 202 of the address register queue 2 and an upper address portion 70 1 and a column address portion 70 2 of the line transfer address register 7. ⁵ Entered, both address power ^s — If they match, the result of the address conflict judgment is 5 2 ± 1.

The buffer register access control unit 1 2 sends the ST2 In response to the store request and the address conflict determination result 52, the contents of the 'store data register queue 3', which is the ST2 store data, are set in the notifier register 20. Here, a store request that caused an address conflict even during line transfer can be processed by writing to the buffer register, and when store data and line transfer data are set in the buffer register 20 at the same time. However, care must be taken to always set the store data first. At this time, the corresponding bit of the change bit 21 is set to 1 at the same time to prevent overwriting by the line transfer data.

In the same procedure as above, between the times t3 and t5, requests s are extracted from the request code register queue 1 from the requests ST3 to ST5 and processed. However, here, it is assumed that ST3 to ST5 are all store requests, and the address matches the address being transferred during line transfer.

When all the line transfer data is set in the buffer register 20 at time t6, the line transfer control unit 13 activates the buffer storage access control unit 14. The buffer storage access control unit 14 receives this, and writes the contents of the buffer register 20 to the write register 33, the write request to the control register 31, and the selector 36 to select and replace the line. Set the column address part of the transfer address register 7 in the address register 32, respectively. The buffer memory 30 writes the line transfer data at time t7. At time t6, the address in the main memory, which is the target of the line transfer, is written from the line transfer address register 7 into the buffer address array 6, and the line transfer address register 7 is reset to perform a series of line transfers. Is completed. When the line transfer is completed, the contents of the line transfer address register 7, the buffer register 20 and the change bit 21 become invalid and are not used until the next line transfer is started.

During the update processing of the buffer address array 6 at time t6 and the update processing of the buffer memory 30 at time t7 to complete this line transfer, the All requests that match the dress need to be suppressed. Therefore, at time t6, there is a request (ST6) in the request code register queue 1 and the line transfer address register 7 is reset at the same time, so that the request cannot be cut out and the line transfer processing is completed. The cutting force is restarted at the point when it reaches t7.

Next, in the embodiment of FIG. 1, a time chart in the case where the request following the request that activated the line transfer is a fetch and the address matches the address of the preceding store request is shown in FIG.

In FIG. 7, the store request (ST0) at time tO is a hit case, and the store request (ST1) at time U is a miss case, and the operation is the same as that described in FIG.

The operation of the fetch request (FT) at time t2 will be described. It is assumed that the FT existing in the request code register queue 1 at time t2 matches the address of ST1. Therefore, a comparison with the line transfer address register 7 gives an address conflict determination result 52. The request cutout control unit 4 receives the fact that the FT is a fetch request from the request decoder 5 and that the FT is up to 52 s, and suppresses the cutout of the FT. This state continues until time t5 is a line transfer address register 7 force ^s effective, for updating the time t6 the buffer address array 6, actually become the FT force ^s possible cut becomes time t7 or later.

Next, FIG. 3 shows a second embodiment of the present invention.

The difference between the present embodiment and the embodiment of FIG. 1 is that there is no buffer register 20 between the main memory 41 and the buffer memory 30 and there is no buffer register access control unit 12 and the light register 33 is The point is that write register A 34 and write register B 35 are used to support 2-port input. That is, with this change, the line transfer data is directly transferred from the main memory 41 to the buffer memory 30 via the write register B 35, and the write register A 34 can be written at the same time. Store data in the You.

The operation in the second embodiment of FIG. 3 is shown in the time chart of FIG.

The difference between the operation of the present embodiment and FIG. 5 is that when the store request (ST1) at time tl starts line transfer, the store data is set in the buffer register 20 in FIG. ⁵ ', FIG. 6 shows that data is written directly into the buffer memory 30, and that the line transfer data from the main memory 41 is written directly into the buffer memory 30.

By directly writing the store data and the line transfer data to the buffer storage 30 in this manner, the process of transferring data from the far register 20 to the buffer storage 30 can be omitted. Further, in the present embodiment, by setting the update time of the buffer address array 6 to be t5, the time at which the store request (ST6) is cut out can be advanced as compared with the example of FIG.

In all the embodiments, the case where the writing back from the buffer memory 30 to the main memory 41 (line back) is unnecessary has been described. However, in the case where the line back is required, the line transfer is performed before starting the line transfer. It is clear that we need to perform the back and then activate the line transfer.

According to the present invention, for a store request following a request that activated line transfer, even when the address matches the address being transferred during line transfer, the store data is written in parallel with the writing of the line transfer data. Store processing can be performed without waiting for the completion of the transfer. As a result, the throughput of the store processing is improved, and thus the throughput of the entire processing apparatus is improved.

It is apparent that the present invention can be applied to the individual storage layers of the processing device having a plurality of storage layers in the embodiment. Industrial applicability

As described above, the present invention relates to a storage device that performs control by the store-in method. Therefore, it is suitable for use in a buffer storage control device that improves the throughput of the entire storage device.

Claims

The scope of the claims

1. It has a buffer memory for holding a part of the data in the main memory, and an address array for holding a main memory address of the data held in the buffer memory, and accesses the buffer memory by a store-in method. a control buffer storage control unit, Roh Tsufa Detaka required in the ^memory? from the main memory which is activated by the absence before the completion of the data transfer to the buffer memory, the Sutarikuesu bets that started the data transfer Sutadeta In the buffer storage control device having means for writing the data into the buffer storage, a means for detecting that the storage request force following the store request that started the data transfer matches the address during the data transfer, and In this case, the storage data of the subsequent storage request is buffered before the data transfer is completed. Means for writing to a buffer storage.

2.A buffer register is provided between the main memory and the buffer memory to store the transfer data and the store data of the store request that started the data transfer, or the transfer data and the store data of the store request that follows the store request that started the data transfer. 2. The buffer storage control device according to claim 1, wherein the content of the buffer register is written into the buffer storage after the data transfer is completed.

3. The buffer register includes a plurality of areas, and includes a determination bit for storing the position of the area where the store data has been written, and refers to the determination bit when writing the transfer data. 3. The buffer storage control device according to claim 2, further comprising means for controlling transfer data not to be written in the area where the data stands.

4.The buffer register includes a plurality of areas, and includes a determination bit for storing the position of the area where the store data has been written, and refers to the determination bit when writing the transfer data, and Day is for the region to stand-bit river crossing ^s 3. The buffer storage control device according to claim 2, further comprising means for controlling data transfer not to be performed.

5. In the buffer storage controlled by the store-in method, when the store data write destination (replay destination) of the store request that started the data transfer from the lower-level storage is determined, the store data of the store request is re-written. A buffer storage control method, comprising: writing to a race destination; and, if the request is for the succeeding store request, further writing the store data to the replacement destination before data transfer is completed.

6.In the store-in type buffer storage, for consecutive requests to the part where the address of the data transfer from the lower-order storage in the transfer unit is the same and the desired data capacity does not exist in the buffer storage, the preceding request A buffer storage characterized in that the processing time when the request is a store request and the subsequent request is a store request is shorter than the processing time when the preceding request is a store request and the subsequent request is a fetch request. Control method.