KR960029986A - 데이타처리장치 및 캐쉬메모리제어방법 - Google Patents

데이타처리장치 및 캐쉬메모리제어방법 Download PDF

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Publication number
KR960029986A
KR960029986A KR1019960001988A KR19960001988A KR960029986A KR 960029986 A KR960029986 A KR 960029986A KR 1019960001988 A KR1019960001988 A KR 1019960001988A KR 19960001988 A KR19960001988 A KR 19960001988A KR 960029986 A KR960029986 A KR 960029986A
Authority
KR
South Korea
Prior art keywords
data
cache
write
address
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960001988A
Other languages
English (en)
Korean (ko)
Inventor
도시히꼬 구리하라
겐지 마쯔바라
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 가나이 쯔또무
Publication of KR960029986A publication Critical patent/KR960029986A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/282—Partitioned cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1019960001988A 1995-01-31 1996-01-30 데이타처리장치 및 캐쉬메모리제어방법 Withdrawn KR960029986A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7034422A JPH08212133A (ja) 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法
JP95-034422 1995-01-31

Publications (1)

Publication Number Publication Date
KR960029986A true KR960029986A (ko) 1996-08-17

Family

ID=12413777

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960001988A Withdrawn KR960029986A (ko) 1995-01-31 1996-01-30 데이타처리장치 및 캐쉬메모리제어방법

Country Status (3)

Country Link
JP (1) JPH08212133A (enExample)
KR (1) KR960029986A (enExample)
TW (1) TW296442B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049395A1 (fr) * 1998-03-23 1999-09-30 Hitachi, Ltd. Controleur de memoire tampon
KR100794312B1 (ko) 2006-12-27 2008-01-11 삼성전자주식회사 명령어 자동 처리 유니트를 포함한 메모리 컨트롤러 및그를 포함한 메모리 시스템
JPWO2012093475A1 (ja) * 2011-01-05 2014-06-09 富士通株式会社 情報転送装置および情報転送装置の情報転送方法
US12105629B2 (en) 2022-07-25 2024-10-01 Samsung Electronics Co., Ltd. Adaptive cache indexing for a storage device

Also Published As

Publication number Publication date
JPH08212133A (ja) 1996-08-20
TW296442B (enExample) 1997-01-21

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960130

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid