TW296442B - - Google Patents

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Publication number
TW296442B
TW296442B TW084113646A TW84113646A TW296442B TW 296442 B TW296442 B TW 296442B TW 084113646 A TW084113646 A TW 084113646A TW 84113646 A TW84113646 A TW 84113646A TW 296442 B TW296442 B TW 296442B
Authority
TW
Taiwan
Prior art keywords
data
cache
write
address
buffer
Prior art date
Application number
TW084113646A
Other languages
English (en)
Chinese (zh)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW296442B publication Critical patent/TW296442B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851Cache with interleaved addressing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855Overlapped cache accessing, e.g. pipeline
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877Cache access modes
    • G06F12/0884Parallel mode, e.g. in parallel with main memory or CPU
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28Using a specific disk cache architecture
    • G06F2212/282Partitioned cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW084113646A 1995-01-31 1995-12-20 TW296442B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7034422A JPH08212133A (ja) 1995-01-31 1995-01-31 データ処理装置及びキャッシュメモリ制御方法

Publications (1)

Publication Number Publication Date
TW296442B true TW296442B (enExample) 1997-01-21

Family

ID=12413777

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084113646A TW296442B (enExample) 1995-01-31 1995-12-20

Country Status (3)

Country Link
JP (1) JPH08212133A (enExample)
KR (1) KR960029986A (enExample)
TW (1) TW296442B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049395A1 (fr) * 1998-03-23 1999-09-30 Hitachi, Ltd. Controleur de memoire tampon
KR100794312B1 (ko) 2006-12-27 2008-01-11 삼성전자주식회사 명령어 자동 처리 유니트를 포함한 메모리 컨트롤러 및그를 포함한 메모리 시스템
JPWO2012093475A1 (ja) * 2011-01-05 2014-06-09 富士通株式会社 情報転送装置および情報転送装置の情報転送方法
US12105629B2 (en) 2022-07-25 2024-10-01 Samsung Electronics Co., Ltd. Adaptive cache indexing for a storage device

Also Published As

Publication number Publication date
JPH08212133A (ja) 1996-08-20
KR960029986A (ko) 1996-08-17

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