經濟部中央標隼局員工消費合作社印製 A7 ______B7 五、發明説明（1 ) 〔發明背景〕 本發明係關於具有以所謂交換（swap)來控制的快取 記憶體的資料處理裝置，而且是關於此快取記憶體的控制 方法’特別是與’在上述的快取記憶體上，即使在對同一 快取線連續的儲存資料時，能夠阻止因快取失誤所產生的 處理性能下降的技術有關。譬如說，係與適用於具有快取 記憶體且以係以管線（pipel ine )形式來執行指令的單晶 粒（single chip)微處理器（micropricessor)的有效 技術有關。 眾所周知的，對於由具有中央處理裝置（central processing unit)等的指令處理裝置（imstruction processing unit) 所執行 的程式 （pr〇gram) 的資料處理而 言’參照上述程式的位址係具有局所性。因此在資料處理 系統（資料處理裝置）中使用快取記憶體。與資料處理系 統的主記憶裝置（main menony device)相比較，快取記 憶體的記憶容量（memony capacity)較小但是其位址存 取時間（address access time)很快。在資料處理過程 中，與保存在主記憶裝置的資料的一部份相同的資料層被 複製（copy)並儲存（store)在快取記憶體內。而能夠 改善資料處理系統的資料處理能力。 在指令處理裝置執行記憶體讀取 (memory read ace-ss )時，指令處理裝置首先會對快取記憶體做爲存取（ acess )。在所要的資料存在於快取記億體上時（所謂快取 命中（cache hit)之時，會從快取記憶體中讀出所要的資 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐) 一 4 - (請先閲讀背面之注意事項再填寫本頁) 裝. 、-» 經濟部中央標準局t貝工消費合作杜印製 A7 ___B7 五、發明説明（2 ) 料並供應到指令處理裝置。因此，不需要對主記憶裝置做 存取，表面上看起來因爲減少了記憶體存取時間，所以能 夠改善資料處理系統的資料處理性能。從主記憶裝置複製 資料到快取記憶體則是考慮所參照的位址的局所性的程序 並以所決定的資料的區段爲單位來進行。通常一個資料區 段的大小係約爲1 6〜1 2 8位元組（byte )。 在具有如此的快取記憶體的資料處理裝置中，在含有 做爲存取對象的資料的資料區段並不存在於快取記憶體上 的場合’即是快取失誤（each misss)的場合，需要從主 記憶裝置將含有該資料的資料區塊轉送（move-in)到快 取記憶體上。在此期間，因爲指令處理裝置係處在等待的 狀態，所以指令處理裝置的資料處理能力會降低其在等待 狀態下的時間的部份。因此，希望能夠開發出在快取失誤 時能夠盡可能的抑制指令處理裝置的資料處理能力下降的 快取控制方式^ 關於此點，在特開昭6 3 — 3 1 1 548號公報（公 開曰：1 988年1 2月20日）中公告了以下的控制方 式。對快取記憶體增設寫入資料緩衝器（write data buffer)。在執行暫存器（register)指示將資料寫入記 憶體的儲存命令而在快取失誤的場合，暫時將寫入資料（ write data)寫入寫入資料緩衝器。而在轉送（move-in )完成之後再從寫入資料緩衝器將寫入資料寫入快取記憶 體。在此方式中，指令處理裝置在將寫入資料寫入寫入資 料緩衝器之時便能夠完成該資料的儲存。因此，因爲能夠 ^紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 一 ' -5 _ (請先閱讀背面之注意事項再填寫本頁) .裝· --t 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3 ) 開始進行處理後續的指令，所以能夠減少指令處理裝置的 等待時間，而能夠改善指令處理裝置的資料處理能力。 〔發明概要〕 本發明者檢討了上述快取控制方式。在寫入資料緩衝 器內已經寫入了寫入資料的狀態下，如果因後續的儲存指 令而使記憶體寫入存取再度快取失誤（第2次失誤），貝IJ 如果不將該第2次失誤的寫入資料也收藏在寫入資料緩衝 器的話，則在到達與先前的儲存命令的資料壓塊被轉送完 畢爲止的期間爲止，指令處理裝置會處在等待的狀態》因 此，就好像在使泛用暫存器（gemral purpose register) 的內容退避到設置於記憶體上的堆疊（stack)的場合一 般，在對快取記憶體上的同一快取線上的同一資料區段連 續儲存的場合，當快取失誤發生時會使資料處理性能大幅 的下降。 本發明的目的係在於提供：即使是在對快取記憶體上 的同一快取線連續的進行儲存，也能夠阻止快取失誤所產 生的資料處理性能下降的資料處理裝置及快取控制方法。 本發明的前述及其它的目的及新特徵可由本說明書的 述及附圖來說明。 本專利發明中的代表部份概要的簡單說明係如下所述 的： 〔1〕資料處理裝置係具有： 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） m :_*-1 ϋ·^ HI · ^^^1 ^^^1 ^^^1 dn nn (請先閱讀背面之注意事項再填寫本頁) -6 - 經濟部中央標準局員工消費合作杜印製 A7 B7_ 五、發明説明（4 ) 產生位址信號並能夠存取記憶體的指令處理裝置（8 )，及 具有：由包含於上述位址信號的註標位址（index a-ddvess )(IDXi)所選擇的快取線，且上述快取線係與和 包含於該位址信號的標籤位址（tag address)(TAGi)比較 的快取標籤（cache tag)成對的一個區段資料區域；而 且被選擇了的快取線中的區段資料區域中的一個資料區域 的所布係由資料字元選擇情報（data word selection i-nformation) (BMRK)所指定的快取記憶體（6)，及 在寫入存取中的上述快取記憶體的快取失誤中，使具 有與上述快取失誤的位址信號的註標位址及標籤位址相同 的註標位址標籤位址的區段資料從上述快取記憶體的上位 處理裝置（2，4)被轉送的轉送資料緩衝器（93)， 及 包含：存寫入存取中的上述快取記憶體的快取失誤中 ，保持上述快取失誤的位址信號的標籤位址及註標位址的 寫入位址緩衝器（90)，及，依照資料字元選擇情報而 將寫入資料保持在相當於上述一個區段資料區域的記憶區 域的寫入資料緩衝器（91)，及，保持著保持於寫入資 料緩衝器的寫入資料的資料字元選擇情報的資料字元選擇 情報緩衝器（92)的寫入緩衝器（9)，及 使包含於寫入存取的位址信號的上述標籤位址及註標 位址寫入位址緩衝器所保持的標籤位址及註標位址相比較 的位址比較器（95)，及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公f ) ^^^1 ^^^^1 ^^^^1 n^— In flm V nn m^— \ 0¾. ，\兵 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ___B7 五、發明説明（5 ) 在寫入存取中的快取記憶體的快取失誤中，在上述寫 入資料緩衝器中沒有保持著有效資料時，以及，在寫入存 取中快取記憶體的快取失誤中’在上述寫入資料緩衝器保 持了有效資料且在上述位址比較器檢測出爲一致時，將該 寫入存取的寫入資料依照其資料字元選擇情報而收藏到寫 入資料緩衝器上的區段資料區域的資料區域的快取控制裝 置（6 0 )。 〔2〕在上述資料處理裝置中，爲了使對上述快取記 憶體進行快取寫入失誤的新輸入（entry)的追加以及收 藏於寫入緩衝器的寫入資料的寫入更效率化，而更設置了 選擇電路（94)。此選擇電路（94)，在寫入存取中 的快取記憶體的快取失誤中，將從上位記憶裝置轉送到資 料緩衝器的區段資料，以顯示上述資料字元選擇情報緩衝 器的資料字元選擇情報的寫入資料緩衝器上的資料區域的 資料來置換並供應給快取記憶體。 〔3〕在考慮以管線方式來執行命令的場合，在執行 指令處理裝置（8 )設置序列（sequemce)控制電路（ 8 0)。序列控制電路（8 0 )係以管線的（並列的）來 控制包含命令提取階段（fetch stage )( I F )，指令 解碼（decode)階段（D )、運算（operation)階段、 (E)、記億體存取階段（A)、以及寫入階段（W)的 命令執行序列（管線階段）。 此序列控制電路將儲存指令的記憶體寫入存取的要求 信號（S TRREQ)通知到上述快取控制電路（6 0 ) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X29?公釐） n i- I t -I— ; · 1^1 ^^1 -i I nn (請先聞讀背面之注意事項再填寫本頁) 一 8 - 經濟部中央標準局，負工消費合作杜印製 A7 B7 五、發明説明（6 ) ，並使對應於來自上述快取控制裝置（6 0 )的上述要求 信號的應答信號（L./ SACK)等待’且使指令執行階 段進入下一個指令的記憶體存取階段，但是，在輸出自上 述快取控制裝置（6 0 )的管線鎖定（pipeline lock) 的指示信號（Lock )被有效的利用的期間，上述序列控制 電路會控制指令執行動作以使記憶體存取階段以前的管線 階段的動作停止。 在因儲存指令而要求進行記憶體存取時（ S T R R E Q = 1 )，上述快取控制裝置（60)在下列 的3個場合會送對應該記億體存取要求的應答信號（ L / SACK)到指令處理裝置（8)。 1 .在對應該記憶體寫入存取要求的寫入存取在快取 命中（cache hit) (DSCMISS=0 )的場合。 2 .在對應該記憶體寫入存取要求的寫入存取在快取 失誤（cache miss)(DCMlSS=l)，而且，上述寫入資料緩 衝器沒有保持有效資料的狀態（WBFRVD=〇)的場 合。 3.在對應記憶體寫入存取要求的寫入存取在快取失 誤（dcmiss=i)，而且，上述寫入資料緩衝器保 持有效資料（WBFRVLD=1)，並由位址比較器檢 出爲一致（BLKMCH=1)的狀態的場合。 另一方面，上述快取控制裝置（6 0 )在以下的場合 會供應管線鎖定用的指示信號（K〇CK=1)到指令處 理裝置（8)。即是，對應該記憶體存取要求的寫入存取 本紙張尺度適用準（CNs ) Λ4規格（21〇χ 297公犛） I— nn m · ^^^1 ml —^ϋ —J (請先閱讀背面之注意事項再填寫本頁) -9 - 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（7 ) 爲快取失誤（DCMISS=1)，而且，寫入資料緩衝 器保持有效資料（WB FRVLD= 1 ) ’並在位址比較 器檢出不一致（BLKMCH=〇)的狀態的場合。 在輸出上述指示信號（KOCK= 1 )到指令處理裝 置後，上述快取控制裝置（6 0 )會對從快取失誤的位址 的區段資料的上位記憶裝置到上述轉送資料緩衝器的轉送 完成做出應答，並送出指示管線鎖定的解除的指示信號（ KOCK=〇)及對該記憶體存取要求的應答到指令處理 裝置。 〔4〕指令處理裝置（8)具有：運算電路（8)， 結合於內部匯流排（bus )的暫存器電路（8 1 )，及， 用以將上述內部匯流排上的寫入資料分配到位元（bit) 數比該內部匯流排多的快取匯流排（cache bus)的校準器 (alignh) ( 8 4 )，及，解碼器（decoda) ( 8 3 )。 上述解碼器（8 3 )係接受輸出自上述運算電路的寫入位 址及寫入位址的大小（size)的情報，並將寫入位址的一 部份解碼且將所得的位元位置做基準並以對應資料大小（ data size)的情報，並將寫入位址的一部份解碼且將所得 的位元位置做基準並以對應資料大小（data size )的位 元做爲選擇準位（level)而產生資料字元選擇情報（ BMRK)。再者，上述解碼器（83)也控制將上述內 部匯流排分配到以所產生的資料字元選擇情報所指示的快 取匯流排上的資料位置。由此，便能夠使快取寫入失誤的 寫入資料依其資料字元選擇情報而收藏而寫入資料緩衝器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） H— I ^^^1 HI-———— m 1^1 VJ 、vs (請先閱讀背面之注意事項再填艿本頁) -10 - A7 B7 29〇442 五、發明説明（8) 上的區段資料區域資料區域。 〔5〕以別的觀點而言，本發明爲： (請先閱讀背面之注意事項再填寫本頁) 一種資料處理裝置的快取記憶體控制方法，而此資料 處理裝置具有·· 能夠寫入存取記憶體的指令處理裝置（8 )，及 連接到上述指令處理裝置的快取記億體（6)，及 在寫入存取時’一時的保存上述快取記憶體的快取失 誤的存取位址情報及寫入資料的寫入緩衝器（9)，及 將包含上述快取失誤的存取位址的資料的區域資料從 快取記億體的上述記憶裝置（2，4 )轉送的轉送資料緩 衝器（9 3 )的資料處理裝置的快取記憶體控制方法，係 包含： 經濟部中央標準局員工消費合作杜印製 在寫入存取時’依上述快取記憶體的快取失誤而將上 述區段資料轉送到上述轉送資料緩衝器的第1的處理，及 將轉送到上述轉送資料緩衝器的上述區段資料的一部 份置換爲上述寫入緩衝器所保有的快取失誤的寫入資料， 並收藏於上述快取記憶體的所定快取線的第2的處理，及 在上述第2的處理之前，若對同一快取線連續進行寫 入存取而使快取失誤連續的產生時，將該後續的快取失誤 的寫入資料收藏在寫入緩衝器上並與先前收藏的寫入資料 的收藏位置爲不同的位置，的第3的處理。 在使汎用暫存器的內容退避到設置於記憶體上的堆疊 區域的場合，對快取記憶體上的同一快取線的儲存動作會 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 11 A7 B7 五、發明説明（9 ) 連續的發生。在此場合，若是一旦產生了快取失誤，則其 後的儲存動作也會變成快取失誤。但是，在本發明中，可 藉由位址比較器（9 5 )檢出連續的發生了對快取記憶體 上的同一快取線做了儲存動作。快取控制裝置（6 0 )， 則依上述位址檢出電路的檢出結果而在一旦產生快取失誤 的場合，會控制而使應儲存到快取記憶體上的同一快取線 的資料連續的保存在寫入緩衝器9。應儲存的資料保存在 寫入緩衝器（9)的狀態則依對儲存的應答而通知到指處 理裝置（8)。由此，指令處理裝置（8)便能夠知道該 寫入存取或儲存指令的執行完畢，而能夠進而控制下一個 指令的執行。由此可以縮短指令處理裝置的等待期間，而 即使在對快取記憶體上的同一快取線連續的進行儲存動作 之時，也能夠阻止快取失誤所引起的資料處理性能的下降 〇 經濟部中央標準局員工消費合作社印製 -----„---：---裝-- (請先閱讀背面之注意事項再填寫本頁) 在此期間’快取失誤的區段資料從上位記憶裝置轉送 到轉送資料緩衝器。轉送到轉送資料緩衝器的資料及寫入 緩衝器的資料則做爲新的輸入而被追加到快取記憶體內。 此時的選擇電路（9 4 )係使轉送資料緩衝器的區段資料 及寫入資料緩衝器的資料依照位元組記號（byte mark) 而合成。合成了的資料則做爲包含了快取失誤儲存資料的 新的輸入而被追加到快取記憶體（1 6 )內。因此，上述 快取輸入（cache enty )的追加，轉送資料緩衝器的區段 資料的寫入’以及，將寫入資料緩衝器的資料以位元組記 號來選擇並寫入並不需要分開來進行》以此點而言，也可 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 12 - 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（10) 使指令處理裝置的等待時間縮短》 〔圖面之簡單說明〕 第1圖係本發明的一實施例的微處理器的方塊圖。 第2圖係以例顯示指令處理裝置的一部份的方塊圖。 第3 (A) 、3 (B)及3 (C)圖係顯示依序改變 執行複數次的儲存指令的儲存資料的收藏位置，收藏於寫 入緩衝器的狀態的說明圖。 第4圖係位元組選擇電路的一例的方塊圖。 第5圖係顯示在資料1次快取控制裝置中，關於資料 儲存的控制邏輯的一例的方塊圖。 第6圖係儲存指令的管線階段的一例說明圖》 第7圓係載入（load )指令的管線階段的一例說明圖 〇 〔實施例1〕 圖1係本發明的一實施例的微處理器的方塊圖。本實 施例的微處理器1雖然沒有特別的限制，但是是基於精簡 指令集（reduced instuction set cmputer ; RISC)結構 (arhitectuve )而形成者，係由眾所周知的半導體集積電 路製造技術而形成於如單晶矽的一塊半導體基板（sen ic-onductor substrate)(半導體晶粒（semiconductor chip)上 。 具有R I S C結構的本實施例的微處理器1雖然沒有 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）Printed by the Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs A7 ______B7 V. Description of the invention (1) [Background of the invention] The present invention relates to a data processing device with a cache memory controlled by a so-called swap, and it is about The control method of the cache memory is 'particularly related to' the above-mentioned cache memory, which can prevent processing performance degradation caused by cache errors even when data is continuously stored on the same cache line . For example, it is related to an effective technology suitable for a single chip microprocessor (micropricessor) that has cache memory and executes instructions in the form of a pipeline (pipeline ine). It is well known that for the data processing of a program (pr〇gram) executed by an instruction processing unit (imstruction processing unit) having a central processing unit (central processing unit), the address referring to the above program is localized. Therefore, cache memory is used in the data processing system (data processing device). Compared with the main menony device of the data processing system, the memory capacity of the cache memory is small but the address access time is fast. During data processing, the same data layer as a part of the data stored in the main memory device is copied and stored in the cache memory. It can improve the data processing capability of the data processing system. When the instruction processing device performs memory read (memory read ace-ss), the instruction processing device first accesses the cache memory (acess). When the required data exists on the cache memory (so-called cache hit), the required capital paper size will be read from the cache memory and the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) 1 4-(please read the precautions on the back before filling in this page), install.,-»Central Ministry of Economic Affairs t Beigong Consumer Cooperation Du Printed A7 ___B7 V. Description of invention (2) Material and supply To the command processing device. Therefore, there is no need to access the main memory device. On the surface, it seems that because the memory access time is reduced, the data processing performance of the data processing system can be improved. Copying data from the main memory device to the cache Memory is a procedure that considers the locality of the referenced address and takes the determined data segment as a unit. Generally, the size of a data segment is about 1 6 ~ 1 2 8 bytes (byte ). In a data processing device having such a cache memory, when a data section containing data as an access target does not exist on the cache memory, it is a cache miss (each misss) Field of , The data block containing the data needs to be moved (move-in) from the main memory device to the cache memory. During this period, because the instruction processing device is in a waiting state, the data processing capability of the instruction processing device It will reduce the part of its time in the waiting state. Therefore, it is hoped that a cache control method that can suppress the decline of the data processing capability of the instruction processing device as much as possible in the case of cache errors can be developed ^ About this point, in the special open Zhao 6 3 — 3 1 1 548 (publication date: February 20, 1988) announced the following control method. Add a write data buffer (cache data buffer) to the cache memory. The register instructs the storage command to write the data to the memory, and in the event of a cache error, temporarily writes the write data (write data) to the write data buffer. And the transfer (move-in) is completed Then write the write data from the write data buffer to the cache memory. In this way, the instruction processing device can complete the writing of the data while writing the write data into the data buffer Therefore, because it can be ^ paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 1 '-5 _ (please read the precautions on the back before filling out this page). Install · --t Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative A7 B7 V. Description of the invention (3) Start processing subsequent instructions, so the waiting time of the instruction processing device can be reduced, and the data processing capability of the instruction processing device can be improved. [Summary of the Invention] The present invention The author reviewed the above cache control method. In the state where the write data has been written into the write data buffer, if the memory write access is again cached due to subsequent storage instructions (the second error) ), If IJ does not store the second erroneous write data in the write data buffer, the command processing device will reach the period until the data block of the previous storage command is transferred. "Waiting" Therefore, it seems that the contents of the general purpose register (gemral purpose register) are backed up to the stack on the memory. In general, if the same data segment on the same cache line on the cache memory is continuously stored, the data processing performance will be greatly reduced when a cache error occurs. An object of the present invention is to provide a data processing device and a cache control method that can prevent a decline in data processing performance caused by a cache error even if the same cache line on the cache memory is continuously stored. The foregoing and other objects and new features of the present invention can be explained by the description of this specification and the accompanying drawings. The brief description of the representative part of the outline of the patented invention is as follows: [1] The data processing device is provided with: This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) m: _ *-1 ϋ · ^ HI · ^^^ 1 ^^^ 1 ^^^ 1 dn nn (please read the notes on the back before filling out this page) -6-Employee Consumer Cooperation Cooperation Duo Printed by the Ministry of Economic Affairs Central Standards Bureau A7 B7_ V. DESCRIPTION OF THE INVENTION (4) An instruction processing device (8) that generates an address signal and can access memory, and has: selected by index a-ddvess (IDXi) included in the above address signal Cache line, and the above cache line is a section data area paired with a cache tag compared with the tag address (TAGi) included in the address signal; and is selected The layout of a data area in the section data area of the cache line is the cache memory (6) specified by data word selection i-nformation (BMRK), and in In the cache error of the cache memory in write access, the cache The segment data of the mislabeled address and the labeled address of the same address address are transferred from the above-mentioned cache memory upper processing device (2, 4) to the transfer data buffer ( 93), and a write address buffer including: storing a cache error of the cache memory in the write access, and holding the tag address and the annotation address of the address signal of the cache error ( 90), and, according to the data character selection information, the write data buffer (91) that keeps the write data in the memory area equivalent to the above one section data area, and, keeps the write data buffer The data character of the written data selects the data character of the information selects the write buffer (9) of the information buffer (92), and makes the above tag address and annotation included in the address signal of the write access The address comparator (95) that compares the label address and the marked address held by the address buffer, and the paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X 297 public f) ^ ^^ 1 ^^^^ 1 ^^^^ 1 n ^ — In flm V nn m ^ — \ 0¾., \ 兵 ( Read the precautions on the back first and then fill out this page) A7 ___B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (5) In the cache error of the write access cache, write in the above When there is no valid data held in the data buffer, and in the cache memory cache error during write access, 'the write data buffer holds valid data and is detected by the address comparator When they are consistent, the cached control device (60) of the data area of the section data area of the write data buffer is stored in the write data according to the data character selection information of the write access. [2] In the above data processing device, in order to make the addition of a new entry for a cache write error to the cache memory and the writing of write data stored in the write buffer more efficient, A selection circuit (94) is further provided. This selection circuit (94) transfers the segment data from the upper memory device to the data buffer in the cache error of the cache memory in the write access to display the data character selection of the information buffer The data character selects the information written to the data area of the data buffer of the information to replace and supply it to the cache memory. [3] When considering the execution of commands in a pipeline manner, a sequence control circuit (80) is provided in the execution instruction processing device (8). The sequence control circuit (80) is pipelined (parallel) to control the fetch stage (IF), instruction decoding stage (D), operation stage, (E), and The command execution sequence (pipeline phase) of the E-body access phase (A) and the write phase (W). This sequence control circuit notifies the above-mentioned cache control circuit (S TRREQ) request signal (S TRREQ) of the memory for storing instructions to the above-mentioned cache control circuit (60) n i- I t -I—; · 1 ^ 1 ^^ 1 -i I nn (please read the precautions on the back and then fill out this page) 1: 8-Printed by the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (6), and make the response signal (L./SACK) corresponding to the above request signal from the above cache control device (60) wait for 'and make the instruction execution stage enter the memory of the next instruction During the body access phase, however, during the period when the instruction signal (Lock) of the pipeline lock output from the cache control device (60) is effectively used, the sequence control circuit will control the command execution action to make The pipeline phase before the memory access phase stops. When a memory access is requested due to a storage command (STRREQ = 1), the above cache control device (60) will send a response signal (L / SACK) corresponding to the memory access request in the following 3 occasions Go to the instruction processing device (8). 1. When the write access corresponding to the memory write access request is in cache hit (DSCMISS = 0). 2. The write access corresponding to the memory write access request is in cache miss (DCMlSS = l), and the write data buffer does not maintain the state of valid data (WBFRVD = 〇) Occasions. 3. The write access in the corresponding memory write access request is in cache error (dcmiss = i), and the above write data buffer holds valid data (WBFRVLD = 1) and is checked by the address comparator When the status is consistent (BLKMCH = 1). On the other hand, the above cache control device (60) will supply an instruction signal for pipeline lock (K〇CK = 1) to the command processing device (8) in the following cases. That is, the paper size of the write-access book that corresponds to the memory access requirements is applicable to the (CNs) Λ4 specification (21〇χ 297 g) I— nn m · ^^^ 1 ml — ^ ϋ —J (please Read the precautions on the back first and then fill out this page) -9-A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs V. Invention description (7) Cache error (DCMISS = 1) The device maintains valid data (WB FRVLD = 1) 'and the address comparator detects inconsistencies (BLKMCH = 〇). After outputting the above instruction signal (KOCK = 1) to the command processing device, the above cache control device (60) will transfer the segment data from the cache missed address's upper memory device to the forwarding data buffer Complete the response, and send an instruction signal (KOCK = 〇) indicating the release of the pipeline lock and the response to the memory access request to the command processing device. [4] The instruction processing device (8) has: an arithmetic circuit (8), a register circuit (8 1) combined with an internal bus (bus), and for distributing the written data on the internal bus The aligner (8 4) of the cache bus (8 4) and the decoder (decoda) (8 3) of the cache bus with more bits than the internal bus. The decoder (8 3) receives the information of the write address and the size of the write address output from the arithmetic circuit, decodes a part of the write address and decodes the resulting bit position Make a reference and use the information corresponding to the data size, decode a part of the written address and use the obtained bit position as the reference and use the bit corresponding to the data size as the selection criterion Bit (level) to generate data character selection information (BMRK). Furthermore, the decoder (83) also controls the allocation of the internal bus to the data location on the cache bus indicated by the generated data character selection information. As a result, the written data of the cache writing error can be stored according to the data character selection information and written into the data buffer. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm). H— I ^^^ 1 HI -———— m 1 ^ 1 VJ, vs (please read the precautions on the back before filling this page) -10-A7 B7 29〇442 V. The area on the description of invention (8) Segment data area data area. [5] From another point of view, the present invention is: (Please read the precautions on the back before filling in this page) A method of cache control of a data processing device, and this data processing device has Command processing device (8) for accessing memory, and cache memory (6) connected to the above-mentioned command processing device, and cache errors that temporarily save the cache memory during write access Write buffer (9) for accessing address information and writing data, and the above-mentioned memory device (2, 4) for taking area data containing the cached access address data from the cache The method for controlling the cache memory of the data processing device of the forwarding data buffer (9 3), which includes: The employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs du printing is based on the above cache memory during write access The first processing of forwarding the sector data to the forwarding data buffer by a cache error, and replacing a part of the sector data forwarded to the forwarding data buffer with the data held by the write buffer Cache miss Write data in the cache and store it in the second line of the cache line of the above-mentioned cache memory, and before the second line of processing, if the same cache line is continuously written and accessed, the cache will fail In the case of continuous generation, the subsequent cached write data is stored in the write buffer and is located at a different position from the previously stored write data. Third processing. When the contents of the general-purpose register are backed up to the stacking area provided on the memory, the storage operation of the same cache line on the cache memory will apply the Chinese National Standard (CNS) A4 specification (210X) 297 mm) 11 A7 B7 5. Description of the invention (9) Continuous occurrence. In this case, if a cache error occurs, the subsequent storage operation will also become a cache error. However, in the present invention, it can be detected by the address comparator (95) that consecutive storage operations have been performed on the same cache line on the cache memory. The cache control device (60), according to the detection result of the above address detection circuit, in the event of a cache error, the control will be made so that the data of the same cache line that should be stored in the cache memory Continuously stored in the write buffer 9. The status of the data to be stored in the write buffer (9) is notified to the finger processing device (8) according to the response to the storage. Thus, the instruction processing device (8) can know that the execution of the write access or storage instruction is completed, and can further control the execution of the next instruction. Thereby, the waiting period of the command processing device can be shortened, and even when the storage operation is continuously performed on the same cache line on the cache memory, the decline in data processing performance caused by cache errors can be prevented. Ministry of Economy Printed by the Central Bureau of Standards' Staff Consumer Cooperative ----- „---: --- installed-- (please read the precautions on the back and then fill out this page) During this period, the information of the section of the cache error is from the upper The memory device is transferred to the transfer data buffer. The data transferred to the transfer data buffer and the data written to the buffer are added as new inputs to the cache memory. The selection circuit (9 4) at this time enables The section data of the transfer data buffer and the data written to the data buffer are synthesized according to the byte mark. The synthesized data is added as a new input including cached stored data. In the cache memory (16). Therefore, the addition of the above cache input (cache enty), the transfer of the data buffer section data writes, and the data written to the data buffer is marked with bytes Selection and writing do not need to be carried out separately. From this point of view, the paper standard can also be applied to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 12-A7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs B7 V. Description of the invention (10) Shorten the waiting time of the instruction processing device "[Simple description of the drawings] FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention. FIG. 2 is an example showing instructions A block diagram of a part of the processing device. Figures 3 (A), 3 (B), and 3 (C) show the change of the storage location of the stored data that is executed multiple times in sequence, and stored in the write buffer Figure 4 is a block diagram of an example of a byte selection circuit. Figure 5 is a block diagram showing an example of control logic for data storage in a data primary cache control device. FIG. 7 is an explanatory diagram of an example of a pipeline stage of a storage instruction. The seventh circle is an explanatory diagram of an example of a pipeline stage of a load instruction. [Embodiment 1] FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention. Figure. The micro Although the processor 1 is not particularly limited, it is based on a reduced instruction set (RISC) structure (arhitectuve), which is formed by a well-known semiconductor integrated circuit manufacturing technology and formed on a piece of semiconductor such as single crystal silicon The substrate (sen ic-onductor substrate) (semiconductor chip (semiconductor chip). The RISC structure of the present embodiment of the microprocessor 1 although the paper size is not applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)
In —flu ^^^^1 n m 1 mu Bufl— i ^—n ^^^^1 - 1 0¾ 、-a (請先閱讀背面之注意事項再填寫本頁) -13 - 2^'〇442 at B7 — ---------------- 一 ......""· 1 '*"1 五、發明説明（u) 特殊的限制其指令長度卻設定爲3 2位元（b i t )。並縮 小了指令集（instruction set)內所包含的指令的數目 ，譬如說，使存取記憶體的指令簡化爲從記憶體轉送資料 到泛用暫存器（general purpoes register)的載入指令 ，及，相反的，從泛用暫存器轉送資料到記憶體的儲存指 令。再者，雖然快取方式也沒有特殊限制，卻是採用2階 層快取方式，微處理器1係具有相互獨立的1次指令快取 記憶體(primary instruction cache memory ) 5 ，及， 1 次資料快取記憶體（primany data cache menory) 6 ;而微處理器1的外部則連接到做爲統一快取記憶體（u-nified cache memory)的 2 次快取記憶體（secondany cache mmoary) 2 。主記憶裝置(main memory device ) 4則經由記憶體匯流排（memory bus) 3而連接到微處理 器1。相對於後述的1次指令快取記憶體5及1次資料快 取記憶體6，2次快取記憶體2及主記憶裝置4係做爲其 上位記憶裝置。 經濟部中央標隼局員工消費合作社印裝 (請先閱讀背面之注意事項再填苟本頁) 1次資料快取記憶體6及2次快取記億體2之間係以 經過儲存方式（store-through system)來控制。在此方 式中’在將儲存資料寫入1次資料快取記憶體6時，一定 也會寫入2次快取記憶體2 » 2次快取記憶體2及主記憶 裝置4之間則以反寫方式（write back system)來控制 ’而使儲存資料僅被寫入2次快取記憶體。在2次快取記 憶體2中的所定快取線置換，即是，發生了輸入（enty ) 的替代（replace )，而且，在2次快取記憶體2的資料 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 14 - 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（12) 與主記憶裝置4的資料不一致時，會將2次快取記憶體2 的資料寫入主記憶裝置4。再者，爲了吸收1次資料快取 記憶體6及2次快取記憶體2的輸出量（through put) 的差而設置了由先進先出緩衝器（first-infirst-out buffev) (FIFO buffer )所構成的儲存緩衝器（ store buffer) 7。在1次快取記憶體5，6及2次快取 記憶體2之間則以1 6位元組爲1區段的單位進行資料轉 送。在2次快取記憶體2與主記憶裝置4之間也同樣的以 1 6位元組爲1區段的單元進行資料轉送。再者，雖然沒 有特別限制，1次快取記憶體5，6，2次快取記憶體2 ，儲存緩衝器7的資料寫入寬度均設爲1 6位元組。對 16位元組的資料寫入寬度的寫入位置係由包含中央處理 裝置（central processing undit) ( C P U )的指令處 裝置（instruction prcossign unit) 8 所產生的 1 6 位 的位元組記號B M R K (資料字元選擇情報data word selation information)所指定。此位元組記號會在後面 詳面說明；係將指令處理裝置8所管理的位址設爲位元組 位址，並由存取位址的下位4位元及資料大小而產生位元 組記號B M R K。 再者，在指令處理裝置8執行位址指令時1次快取記 憶體6產生快取失誤的場合，係採用將快取失誤的輸入從 主記憶裝置4或2次快取記億體轉送到1次資料快取記憶 體6的交換方式（swap system)。並設置有別於儲存緩 衝器7的寫入緩衝器9。在儲存指令執行中1次資料快取 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） ---——一II i------IT------〆 (請先閱讀背面之注意事項再填寫本頁) 15 - A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説咬 ( 13) 1 | 記 憶 體 6 發 生 快 取 失 誤 時 藉 由 將 儲 存 資 料 等 暫 時 的 寫 入 1 1 該 寫 入 緩 衝 器 9 指 令 處 理 裝 置 8 便 不 需 要 等 待 從 2 次 快 1 | 取 記 億 W 2 或 主 處 理 裝 置 4 的 資 料 的 區 段 轉 送 完 成 * 便 能 1 I 夠 持 續 的 執 行 後 續 的 指 令 〇 其 詳 細 的 如 後 述 〇 請 先 閲 1 1 I 1 次 指 令 快 取 記 憶 體 tlsz. 5 係 由 1 次 指 令 快 取 控 制 裝 置 if 背 1 1 5 0 來 控 制 其 壬|· 動 作 〇 指 令 處 理 裝 置 8 在 指 令 提 取 時 輸 出 指 之 注 音 1 1 令 位 址 I A D R S 9 並 送 出 指 令 讀 出 要 求 1 指 令 提 取 要 求 思 事 項 1 1 ， I F R E Q 到 1 次 指 令 快 取 控 制 裝 置 0 接 受 了 此 丹 填 寫 本 裝 I F R E Q 的 1 次 指 令 快 取 控 制 裝 置 5 0 則 在 1 次 指 令 快 頁 1 I 取 記 憶 體 ruz. 5 對 此 指 令 位 址 I A D R S 快 取 命 令 中 時 會 將 1 I 從 1 次 指 令 快 取 記 憶 體 5 所 讀 出 的 指 令 碼 ( code ) 1 1 I I C R D 經 過 選 擇 器 ( se 1 e c t or ) 5 1 而 供 應 到 指 令 處 1 訂 理 裝 置 8 〇 而 在 1 次 指 令 快 取 記 憶 體 HS. 5 快 取 失 誤 時 9 1 次 1 1 指 令 快 取 控 制 裝 置 5 0 會 輸 出 指 令 正 段 轉 送 要 求 1 1 I T R E Q 2 到 次 快 取 控 制 裝 置 〇 1 次 指 令 快 取 控 制 裝 置 1 5 0 則 依 對 上 述 I T R E Q 的 2 次 快 取 控 制 裝 置 1 0 的 應 *'>1 -I 答 ( 指 令 區 段 轉 送 應 答 ) I T A C K tit. 做 出 應 答 並 控 制 選 1 擇 器 5 1 而 使 從 2 次 快 取 記 億 體 2 或 主 記 憶 裝 置 4 轉 送 的 1 1 指 令 碼 I C R D 經 由 指 令 選 擇 器 5 1 而 供 應 到 指 令 處 理 裝 1 1 置 8 〇 1 次 指 令 快 取 控 制 裝 置 5 0 在 供 應 指 令 碼 之 1 I C R D 到 指 令 處 理 裝 置 8 時 » 會 通 知 指 令 讀 出 應 答 ( 指 令 1 I 提 取 承 認 ) I F A C K 給 指 令 處 理 裝 置 8 〇 1 1 I 再 者 y 1 次 指 令 快 取 控 制 裝 置 5 0 會 使 用 圖 未 示 的 指 1 1 1 令 用 位 指 變 換 緩 衝 器 ( in St Γ U c t i on addr es S tr an si at i - 1 1 1 本紙悵尺度適用中國國家榡準（CNS ) A4規格（2丨OX 297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（14) on look-aside buffer)來檢查是否可以存取該頁（ page )，若是不可以則會供應存取保護違及（access protection error)等的例外處理要求（exception proc es request)到指令處理裝置。 1次資料快取記憶體6雖然沒有特殊限制，卻具有複 數，如1 2 8的快取線，各快取線則由特理頁（phy si ca-1 page )號碼等的記憶區域及16位元組的資料部所構成。 指令處理裝置8所產生的邏輯位址（logical address) 則由邏輯頁（logical page)號碼（邏輯頁位址）及分枝 (of f set )所構成，而該分枝的下位4位元（第0位元〜 第3位元）係用以產生上述位元組記號BMRK。在本實 施例中，1 6位元組的資料部（一個區段資料區域）的資 料位置係由位元組記號B M R K所指定。位元組記號 BMRK爲由指令處理裝置8所產生的位址信號的下位4 位元，及，表示資料大小的控制情報所產生的1 6位元的 情報。上述分枝的上位側7位元（從第4位到第1 0位元 )則設定爲註標位址（inde address)，用以做爲快取線 的選擇，即是，做爲註標。在本實施例中，分枝係設爲 1 1位元，由此，頁大小（page size )則設爲2 K位元 組。使註標3的快取線所保有的物理頁號碼做爲快取標籤 (cache tag)並與存取位址的物理頁號碼做比較。在快 取標籤與存取位址的物理頁號碼一致時則設爲快取命中， 在不一致時則設爲快取失誤。 在此實施例中，將與快取標籤比較的位址信號的物理 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、yeIn —flu ^^^^ 1 nm 1 mu Bufl— i ^ —n ^^^^ 1-1 0¾, -a (please read the precautions on the back before filling this page) -13-2 ^ '〇442 at B7 — ---------------- 1. ...... " " · 1 '* " 1 V. Description of invention (u) Special restrictions on its command length Set to 32 bits. And reduce the number of instructions contained in the instruction set (instruction set), for example, to simplify the instruction to access the memory into a load instruction to transfer data from the memory to the general purpose register (general purpoes register), And, on the contrary, the storage command to transfer data from the general-purpose register to the memory. Furthermore, although there is no special limitation on the cache method, it uses a 2-level cache method. The microprocessor 1 has independent instruction cache memory (primary instruction cache memory) 5, and, the primary data Cache memory (primany data cache menory) 6; and the exterior of the microprocessor 1 is connected to the secondary cache memory (u-nified cache memory) as the secondary cache memory (secondary cache mmoary) 2. The main memory device 4 is connected to the microprocessor 1 via a memory bus 3. In contrast to the one-time instruction cache memory 5 and the one-time data cache memory 6, which will be described later, the second-time cache memory 2 and the main memory device 4 are used as their upper memory devices. Printed by the Employees ’Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs (please read the precautions on the back and then fill in this page). The data cache is stored between the primary data cache 6 and the secondary cache memory billion body 2 ( store-through system) to control. In this way, 'when the stored data is written into the data cache memory 1 once, it will also be written into the cache memory 2 twice »between the second cache memory 2 and the main memory device 4 The write back system (write back system) is used to control so that the stored data is only written to the cache twice. Replacement of the specified cache line in the secondary cache memory 2, that is, replacement of the input (enty) has occurred, and the paper size of the data in the secondary cache memory 2 is applicable to the Chinese national standard (CNS) A4 specification (210X297 mm) 14-A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (12) If the data of the main memory device 4 is inconsistent, the cache memory 2 will be cached 2 times的 数据 写 Main memory device 4. Furthermore, in order to absorb the difference between the output throughput of the primary data cache 6 and the secondary cache memory 2, a first-infirst-out buffev (FIFO buffer) ) Composed of storage buffer (store buffer) 7. The data is transferred in units of 16 bytes as one sector between the primary cache memory 5, 6 and the secondary cache memory 2. The data is transferred between the secondary cache memory 2 and the main memory device 4 in units of 16 bytes. Furthermore, although there is no particular limitation, the primary cache memory 5, 6, the secondary cache memory 2, and the data write width of the storage buffer 7 are all set to 16 bytes. The write position of the 16-byte data write width is a 16-bit byte symbol BMRK generated by an instruction prcossign unit 8 including a central processing device (central processing undit) (CPU) (Data word selation information). This byte symbol will be described in detail later; the address managed by the command processing device 8 is set to the byte address, and the byte is generated from the lower 4 bytes of the access address and the data size Symbol BMRK. In addition, when the instruction processing device 8 executes an address instruction, if the cache memory 6 generates a cache error once, the input of the cache error is transferred from the main memory device 4 or the second cache memory to the cache. One data cache 6 exchange system (swap system). Also, a write buffer 9 different from the storage buffer 7 is provided. The data is cached once during the execution of the storage instruction. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) ------- 一 II i ------ IT ------ 〆 ( Please read the precautions on the back before filling in this page) 15-A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invented bite (13) 1 | Memory 6 By storing data when a cache error occurs Temporary write 1 1 The write buffer 9 instruction processing device 8 does not need to wait for the transfer of the data from the second fast 1 | fetching 100 million W 2 or the data of the main processing device 4 * 1 I can last long enough The execution of the subsequent instructions. The details are described below. Please read 1 1 I 1 instruction cache memory tlsz. 5 is controlled by the instruction cache control device if 1 1 5 0 to control its operation | 〇 The command processing device 8 outputs the phonetic transcription of the finger during command extraction 1 1 The command address IADRS 9 and sends the command read request 1 Retrieval request considerations 1 1, IFREQ to 1 instruction cache control device 0 Accepted this Dan to fill in the IFREQ 1 instruction cache control device 5 0 then 1 instruction cache page 1 I fetch memory ruz. 5 In this IADRS cache command, the instruction address will read 1 I from the instruction cache memory 5 The instruction code (code) 1 1 IICRD is supplied through the selector (se 1 ect or) 5 1 Go to the command site 1 ordering device 8 〇 and cache memory HS in 1 command. 5 cache errors 9 1 time 1 1 command cache control device 5 0 will output command forward segment transfer request 1 1 ITREQ 2 to time Cache control device 〇1 instruction cache control device 1 5 0 according to the above ITREQ twice cache control device 1 0 response * '> 1 -I answer (command section transfer response) ITACK tit. Response and control the selector 5 1 to make the slave 2 times faster 1 1 instruction code ICRD transferred from the memory 2 or the main memory device 4 is supplied to the instruction processing device via the instruction selector 5 1 1 1 set 8 〇1 instruction cache control device 5 0 In the supply instruction code 1 ICRD to When the command processing device 8 »will notify the command read response (command 1 I fetch acknowledgement) IFACK to the command processing device 8 〇1 1 I and y 1 command cache control device 5 0 will use the finger not shown 1 1 1 Reusable bit index conversion buffer (in St Γ U cti on addr es S tr an si at i-1 1 1 The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX 297 mm) Printed A7 B7 by the Staff Consumer Cooperative of the Central Bureau of Standards. 5. Description of the invention (14) on look-aside buffer) to check whether the page can be accessed. If it is not possible, access protection error will be provided (access protection error) ) And other exception handling requests (exception proc es request) to the instruction processing device. Although the primary data cache 6 has no special restrictions, it has plural numbers, such as 1 2 8 cache lines, and each cache line is composed of the memory area such as the phy si ca-1 page number and 16 Constituted by the data portion of the byte. The logical address generated by the instruction processing device 8 is composed of a logical page number (logical page address) and a branch (of f set), and the lower 4 bits of the branch ( 0th bit ~ 3rd bit) are used to generate the above byte symbol BMRK. In this embodiment, the data position of the 16-byte data part (a section data area) is specified by the byte symbol B M R K. The byte symbol BMRK is the lower 4 bits of the address signal generated by the command processing device 8, and the 16-bit information generated by the control information indicating the data size. The upper 7 bits of the above branch (from the 4th bit to the 10th bit) are set as the inde address, which is used as the cache line selection, that is, as the annotation . In this embodiment, the branch system is set to 11 bytes, and thus the page size (page size) is set to 2 K bytes. The physical page number held by the cache line of the marked 3 is used as a cache tag and compared with the physical page number of the access address. When the cache tag matches the physical page number of the access address, it is set as a cache hit, and when it does not match, it is set as a cache error. In this embodiment, the physical paper size of the address signal compared with the cache tag is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297mm) (please read the precautions on the back before filling this page), ye
T 17 - 經濟部中央標準局員工消費合作社印製 A7 __B7 五、發明説明（15) 號碼設爲標籤位址。並在圖未示的資料用位址變換緩衝器 內進行將邏輯號碼轉換成物理號碼。 圖1雖然未顯示該位址變換緩衝器，但是請將其視爲 係內藏於指令處理裝置8內。因此，圖1所示的資料位址 DADRS係含有物理頁號碼（標籤位址），及，利用於 分枝內的上述註標位址位元（註標位址）。分枝在物理位 址及邏輯值位址相互間係共通的。 1次資料快取記憶體6係由1次資料快取控制裝置 6 0來控制其動作。指令處理裝置8在資料存取時輸出資 料位址DADR S及位元組記號BMAR。指令處理裝置 8在其資料存取係在儲存（記憶體寫入）的的場合，將供 應儲存要求STRREQ給1次資料快取控制裝置6 0。 另一方面，指令處理裝置8在其資料存取係在載入（記億 體讀取）的場合，供應載入要求LRDREQ給1次資料 快取控制裝置6 0。若由資料位址DADRS而使快取標 籤被註標，則由此註標而得到的物理頁號碼（物理頁在位 址）會與經由資料用位址變換緩衝器而被供應的物理頁位 址（標籤位址）相比較。1次資料快取控制裝置6 0則依 其比較結果而判斷1次資料快取記憶體6的快取命中/快 取失誤。此時，使用位於資料用位址變換緩衝器上的存取 保護情報並檢查是否可對該頁做存取等，在違反記憶體保 護等的場合，則要求用以處理此違反記憶體保護的例外處 理。 在載入要求中，在判定爲快取命中時，註標3的快取 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210X297公釐〉 ^^1 ^^^1 nn ^^^1 nn ^^^1-·J. 、V'B (請先閲讀背面之注意事項再填艿本頁) 18 - 經濟部中央標隼局負工消費合作社印聚 A7 ____ B7 五、發明説明（16) 線的資料部的資料會依位元組記號BMRKffiJ被選擇，並 經由載入選擇器6 1而供應到指令處埋裝置8。在載人要 求中’在判定爲快取失誤時’ 1次資料快取控制裝置6 〇 則輸出資料區段轉送要求D T R E Q到2次快取控制裝置 ’而對上述資料區段轉送要求DTREq的應答（資料區 段轉送應答）DTACK則與轉送自2次快取記憶體2或 主記憶裝置的資料一起經由載入資料選擇器6丨而供應到 指令處理裝置8。 在儲存要求中’在判定爲快取命中時，係依位元組記 號B MR K而選擇註標了的快取線的資料部的一部份，並 使來自指令處理裝置8的儲存資料STRDAT經由寫人 選擇器6 2而寫入此部份。在對1次資料快取記憶體6進 行寫入之時’1次資料快取控制裝置60會供應儲存緩衝 器寫入要求SBWREQ到2次快取控制裝置1 〇，由此 而將該儲存要求的儲存資料STRD AT，資料位址 DADRS ’及，位元組記號BMRK暫時的收藏到2次 快取記憶體2 ^ 在儲存要求中產生快取錯誤時，需要從主記憶裝置4 或2次快取記憶體2將該資料區段轉送（move-in)到快 取記憶體。在圖1中，9 3係轉送資料緩衝器。在儲存要 求時的寫入存取中的1次資料快取記憶體6的快取失誤中 ，將與上述快取失誤的寫入存取位址的資料位址 D A D R S (上述標籤位址及註標位址）共通的區段資料 從2次快取記憶體2或主記憶裝置4讀出並收藏到轉送資 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210'Χ297公釐） I— I I -裝 訂 Μ (請先閱讀背面之注意事項再填寫本頁) 19 - 經濟部中央標準局員工消費合作社印製 A7 ___________ B7 五、發明説明（ιη 料緩衝器9 3。在對上述轉送資料緩衝器轉送資料區段的 $間’爲了使指令處理裝置8解除等待的狀態而設置了前 述寫入緩衝器9。再者，用以轉送的資料區段轉送要求 DAREQ係從1次資料快取控制裝置6 〇供應到2次快 取控制裝置1 0。 i:述寫入緩衝器9係具有寫入位址緩衝器9 0，及， 寫入資料緩衝器9 1 ，及，位元組記號緩衝器9 2。在寫 入位址緩衝器9 0係在寫入存取中的丨次資料快取記憶體 6的快取失誤中’保持上述快取失誤的資料位址 DADRS(在本實施例中爲做爲物理頁號碼的標籤位址 ’及利用於1次資料快取記憶體6的註的註標位址）。上 述寫入資料緩衝器91則供應相當於1次資料快取記憶體 6的資料部6的一個區段資料區域的記憶區域，即是1 6 位元組的記憶區域，並依位元組記號BMRK而將寫入資 料保持在該記憶區域。位元組記號緩衝器（資料字元選擇 情報緩衝器）9 2則保持著保持於寫入資料緩衝器9 1的 寫入資料（儲存資料）的位元組記號BMRK。 圖2部份的顯示指令處理裝置8的內部構成。在此圖 中顯示著各分別爲4位元的3條的匯流排BUS 1 、 BUS 2、BUS 3做爲代表；8 0係用以管線的控制後 述的指令的執行及控制指令執行順序的序列控制電路。指 令處理裝置8則供應汎用暫存器8 1 ，而汎用暫存器8 1 則利用於資料位址及位址暫存器等^ 在運算器8 2所計算的邏輯位址LADRS的下位4 本紙張又度適用中國國家標準（CNS )八4規格（210X 297公釐） -批衣 I訂I'^ (請先閱讀背面之注意事項再填窝本頁) -20 - 經濟部中央標準局員工消費合作社印製 A7 ____B7 五、發明説明（1δ) 位元及儲存位址的資料大小係供應到解碼器8 4，並由此 而產生位元組記號B M R Κ。校準器8 4則將4位元組的 的匯流排BUS3的資料以位元組單位分配給16位元組 的儲存資料匯流排（供應了圖1的儲存資料STRDAT 的匯流排。此分配控制則是依解碼器8 3所形成的位元組 記號BMRK而進行。 譬如說’在供應到解碼器8 3的4位元的位址位元係 所有的位元均爲邏輯值，〇 〃時，若資料大小爲4位元組 則使位元組記號BMRK的最下位算起的4位元設爲邏輯 值""I" ’由此，而將4位元組的儲存資料配置到1 6位 元組的儲存資料匯流排的下位側4位元組。此時，若資料 大小爲2位元組則使位元組記號B M R K的最下位起2位 元爲邏輯值’1^，由此，可將2位元組的儲存資料配置 於1 6位元組的儲存資料匯流排的下位側2位元組。 再者，上述資料位址DADRS係利用：將在運算器 8 2所產生的邏輯位址L AD R S的邏輯頁號碼以圖未示 的資料用位址變換緩衝器變換所得的物理頁號碼及其分枝 所產生的。 在圖1中，9 5係判定連續的資料儲存是否是對1次 資料快取記憶體6的同一快取線的位址比較器。該位址比 較器9 5係比較：寫入位址緩衝器9 3所保持的上一次的 儲存的資料位址DADR S，及，指令處理裝置8這次輸 出的資料位址D A D R S，並將其比較結果輸入到1次資 料快取控制裝置6 0。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） awaav I ι^ϋ m nn ^^^1 - J. 、va (請先閱讀背面之注意事項再填寫本頁) -21 A7 B7 五、發明説明（l9) ----.--.--裝-- (請先閱讀背面之注意事項再填寫本頁) 在位址比較器9 5的比較結果爲一致的場合表示前後 的儲存位址係對1次資料快取記憶體6的同一快取線做儲 存。在此場合，因爲寫入資料緩衝器9 1具有快取線份的 資料記憶區域，所以1次資料快取控制裝置6 0爲了也能 夠使後續的快取失誤的儲存資料也收藏在寫入資料緩衝區 9 1 ，而輸出寫入要WBWREQ求到寫入緩衝區9。1 次資料快取控制裝置6 0除了輸出寫入要求WBWR E Q 之外也並行的輸出對此次的儲存要求S TRR E Q的應答 (載入/儲存應答）L/SACK到指令處理裝置8，而 使指令處理裝置8能夠執行下一個指令。 圖3 (A)、圖3 (B)及圖3 (C)係依序改變複 數次的儲存指令執行的儲存資料的收藏位置並顯示其收藏 於寫入緩衝器9內的狀態。 譬如說，如圖3 (A)所示的，在資料位址 DADRS = TAGi (標籤位址），IDXi (註標位 址），儲存資料 STRDAT = D〇，D1 ，D2，D3 (共計4位元組），位元組記號BMRK= 經濟部中央標準局員工消費合作社印裝 料器 資衝 次緩 1 入 若寫 ’ 入 時寫 之被 ο 會 ο 料 ο 資 ο 些 ο 這 ο 則 ο ο 誤 ο 失 ο 取 ο 快 0 6 ο 體 1 憶 1 記 1 取 1—I 快 ， G 時 A 此 T ο II 令 S 指 R 個 D 一 A 下D 行址 執位 夠料 能資 9 與 置使 裝 ο 理 1 處置 令裝 指制 使控 而取 ’ 快 9 次 令 指 2 存 體。儲 憶 3 爲 記 9 令 取器指 快衝次 次緩該 2 料的 從資行 段送執 區轉在 料到 8 資送置 的轉裝 通段理 共區處 i 始令 X開指 D 4 若 I 置 ’ 裝 憶 記 主 或 且 一適 一度 尺 一張 紙 準 標 家 國 國 經濟部中央標準局員工消費合作社印製 A7 B7______ 五、發明説明（20) 資料位址DADRS=TAGi ， IDXi ’儲存資料 STDDAT = D4 ’ D5 ’ D6 ’ D8 (共目十 4 位兀組 )，位元組記號B M R K = ooool 1 1 1000000 ◦的話’因爲此儲存與上 次的對像均爲同一快取線，所以與上次同樣的’ 1次資料 快取記憶體6爲快取失誤。此時’位址比較器9 5的比較 結果爲一致，而且’因爲在寫入緩衝器9內之收藏著有效 資料，所以不對位元組記號緩衝器9 2進行重置（reset 1 ，而是由1次資料快取控制裝置6 0送出寫入要求 W B W R E Q到寫入緩衝器9。 其結果爲如圖3 (B)所示的，這些資料會被收藏在 寫入緩衝器9。4位元組的儲存資料D4，D5，D6， D 7在校準器（aligner)8 4處被合併（merge)而被收 藏在16位元組的寫入資料緩衝器91。位元記號緩衝器 92的各位元則，譬如說，在RS (設定（set)/重 置（rest))正反器（flip-flop)處構成，並如圖3 ( B ) 所示的，將位元組緩衝器9 2的位元組記號對應著共計爲 8位元組的資料D0〜D8而使8位元設爲邏輯值 〇 再者，若指令處理裝置8連續的執行資料位址 DADRS=TAGi ， IDXi ，儲存資料 STRDAT = D8，D9，Dl〇，Dli (合計 4 位 元組），位元組記號B M R K = 0000000011110000的儲存指令，則因爲 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I - - n I I · 丁 I I- (請先閱讀背面之注意事項再填寫本頁) 23 - 經濟部中央標準局員工消費合作社印製 A7 _______B7 五、發明説明（21 ) 此儲存與上次的對象均爲同一快取線，所以與上次同樣的 ’ 1次資料快取記憶體6會快取失誤。此時，位址比較器 9 5的比較結果爲一致，而且，因爲在寫入緩衝器9內已 收藏了有效的資料，所以不對位元組記號緩衝器9 2進行 重置而是供應寫入要求WBWR E Q到寫入緩衝器9。 其結果’如圖3 ( C )所示的，這些資料會被收藏到 寫入緩衝器9。4位元組的儲存資料D 8〜D 1 1則在校 準器8 4處被合併並收藏於1 6位元組的寫入資料緩衝器 9 1 ’位元組記號9 2的位元組記號則對應著共計爲1 2 位元組的資料DO〜Dl 1而使8位元設爲邏輯值"1， 〇 因此，就好像在使用汎用暫存器的內容退避到設於記 憶體上的堆疊的場合一樣，在連續的對同一區段進行儲存 而使其變爲係置於快取記憶體上的同一快取線之時，即使 產生快取失誤，因爲能夠連續的將儲存資料保存在寫入儲 存器9，所以能夠縮短指令處理裝置的等待時間。即使在 1次資料記憶體6上對同一快取線做連續的資料儲存時， 也能夠阻止快取失誤所導致的資料處理性能的下降。 如圖1所示的，1次資料處理控制裝置6 0係具有： 顯示是否有有效資料收藏於寫入緩衝器9的旗標（flag) (寫入緩衝器有效旗標）6 0 0 »此旗標6 0 0在微處理 器1的出期重置（initalized reset)或是開機重置（ power on reset)的初期狀態下’係初期化爲保持邏輯值 的重置狀態（寫入緩衝器9內不存在有效資料）。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） n - 1^1 - -- f^lf I - - - I --:1 ! ^ (請先閱讀背面之注意事項再填寫本頁) -24 - 206442 A7 ___B7 五、發明説明（22) 旗標6 0 0在此重置狀態下，若是因資料儲存的快取失誤 而產生寫入要求WBWREQ到寫入緩衝器9中，則變成 保持著邏輯值*1^的設定狀態（寫入緩衝器9內存在有 效資料）。在因寫入緩衝器9的資料而使1次資料快取記 億體6更新時，旗標6 0 0則回到重置狀態。位元組記號 緩衝器9 2的重置端點（由輸入邏輯值，而重置）則 ’譬如說’由保有次資料快取控制裝置6 〇的上述旗標 600的反相位元所控制。 對上述轉送資料緩衝器9 3的資料區段轉送的完成係 由資料區段轉送應答D A T C K而從2次快取控制裝置 1 0送到1次資料快取控制裝置6 0。位元組選擇電路 9 4的資料輸入端點則與轉送資料緩衝器9 3的資料輸出 端點及寫入資料緩衝器91的資料輸出端點相結合。 經濟部中央標隼局員工消費合作社印製 n - - I —I- - I 士^I - 1-1- m _ I 丁 、τ (請先閱讀背面之注意事項再填筇本頁) 在將完成收藏於轉送資料緩衝器9 3的區段資料登錄 到1次資料快取記憶體6所定快取線時，位元組選擇電路 9 4將轉送資料緩衝器9 3的區塊資料置換爲顯示上述位 元組記號緩衝器9 2的位元組記號BMRK的寫入資料緩 衝器9 1上的資料區域的資料，並將置換了的資料供應到 1次資料快取記憶體6 »此動作係依1次資料快取控制裝 置6 0接受資料區段轉送應答DTACK而進行。 如圚4所示的’位元組選擇電路9 3具有依照位元組 記號緩衝器9 2的對應位元的控制而選擇轉送資料緩衝器 9 3的資料或是選擇寫入資料緩衝器9 1的資料的選擇器 Swl ector ) 9 4 1。選擇器9 4則在對應的寫入記號緩衝 本紙張&度適用中國國家縣（CNS ) Λ4規格（2丨〇χ 297公麓) --*- 經濟部中央標準局員工消費合作社印製 A7 ___B7 五、發明説明（23) 器的位元爲邏輯值時選擇寫入資料緩衝器9 1的位 元組資料’而在對應的寫入記號緩衝的位元的邏輯值 "時選擇轉送資料緩衝器93的位元組資料。位元組選擇 電路9 4的輸出則經由寫入選擇器6 2而供應到1次資料 快取記憶體6。再者，在儲存存取中，在1次資料快取記 憶體6命中的場合，寫入選擇器6 2直接選擇來自指令處 理裝置8的儲存資料並供應到1次資料快取記憶體6 ^ 在上述位元組選擇電路9 3中並不需要使：將快取失 誤的儲存資料寫入到1次資料快取記憶體6以做爲新的輸 入，以及，轉送資料緩衝器9 3的區段資料的寫入，及， 以位元組記號而做選擇並進行寫入資料緩衝器91的資料 寫入，分開的進行，因此，能夠將指令處理裝置8的這一 部分的等待時間縮短。 在本實施例的微處理器1中雖然沒有特殊限制，卻是 採用由I F (指令提取），D (指令解碼）、E (運算） 、A (記憶體存取）、及，W (寫入）的5個階段所構成 的管線。其控制係由圖2所示的序列控制電路8 0所負責 。在IF階段，指令處理裝置8從1次指令快取記憶體5 等提取指令。在D階段’指令處理裝置8將從I F階段取 得的指令解碼並產生各種控制情報。在E階段’指令處理 裝置8則依在D階段所產生的控制情報而進行用以執行載 入指令及儲存指令等的資料運算及位址運算。在A階段， 指令處理裝置8則使用在E階段所運算得的位址及資料而 進行記憶體存取。此時’1次資料快取控制裝置60會送 本紙張尺度適用中國國家標準（CNS M4規格（2丨〇x 297公釐）_ 26 - ί I*^^^1 ^^^1 ^n· ^^^1 —^ϋ \ , 0¾-=¾ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局一貝工消費合作社印t 五、發明説明（24) 來1次資料快取記憶體6的命中/失誤及是否有插隊等檢 測結果。 在鎖定管線的鎖定信號L ◦ C K設爲肯定（assert) 的場合’ I F ’ D，E ’ a的各階段的狀態會保持住而保 管線被鎖定。在管線鎖定是在A階段被鎖定的場合，在其 解除之後’指令處理裝置8的處理會被轉移到W階段，並 在該W階段’在儲存指令的場合則對1次資料快取記憶體 及寫入緩衝器做寫入，在載入指令的場合則對暫存器做寫 入。 圖5顯示與1次資料快取控制裝置6 0資料儲存有關 的控制邏輯的一例。同圖所示的邏輯係考慮了上述的管線 鎖定。在同圖中’ D CM I S S爲1次資料快取記憶體6 的快取失誤信號；係爲輸出於1次資料快取記憶體6的信 號。BLKMCH係資料區段一致信號；係輸出於位址比 較器9 5的信號。WBFRVLD係對應於上述旗標 6 0 0的旗檩，顯示在寫入暫存器9中是否收藏著有效資 料。 LOCK係管線鎖定信號。STRREQ、LRDREQ 、DTACK、L/SREQ、WBWREQ、 DTREQ係上述的要求信號。在此例中，這些信號及旗 標係設爲正邏輯。 同圖中的FF 1 ' FF3爲R/S正反器（flip-flop) 、 FF2 、 FF4 、 FF5 爲 D 型閂鎖 （latch) 、G1〜G3爲或閘（〇R gate) ，G4爲及閘（ 本紙張尺度適用中國國家標隼（CNS ) A4規格（2〗0><297公漦） (請先閱讀背面之注意事項再填寫本頁) —裝·T 17-Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy A7 __B7 V. Description of invention (15) The number is set as the label address. And convert the logical number into a physical number in the address conversion buffer for data not shown in the figure. Although the address conversion buffer is not shown in FIG. 1, please consider it to be embedded in the instruction processing device 8. Therefore, the data address DADRS shown in Figure 1 contains the physical page number (tag address), and, the above-mentioned annotation address bits (annotation address) used in the branch. The branches are common to each other in physical address and logical value address. The primary data cache memory 6 is controlled by the primary data cache control device 60. The command processing device 8 outputs the data address DADR S and the byte symbol BMAR during data access. The instruction processing device 8 sends the supply storage request STRREQ to the primary data cache control device 60 when its data access is in storage (memory writing). On the other hand, when the data access system is loading (memory reading), the instruction processing device 8 supplies the loading request LRDREQ to the primary data cache control device 60. If the cache tag is marked by the data address DADRS, the physical page number (physical page at the address) obtained by the marking will be the same as the physical page bit supplied through the data address conversion buffer Address (tag address). The primary data cache control device 60 judges the cache hit / cache error of the primary data cache memory 6 according to the comparison result. At this time, use the access protection information located on the data address conversion buffer and check whether the page can be accessed, etc. In the case of memory protection violation, etc., it is required to deal with the memory protection violation Exception handling. In the loading requirements, when it is judged as a cache hit, the paper size of the cached paper marked 3 is applicable to the China National Standard Falcon (CNS) Λ4 specification (210X297mm> ^^ 1 ^^^ 1 nn ^^^ 1 nn ^^^ 1- · J., V'B (please read the precautions on the back before filling in this page) 18-The Ministry of Economic Affairs Central Standard Falcon Bureau Negative Work Consumer Cooperative Printed A7 ____ B7 V. Description of invention (16 ) The data of the data section of the line will be selected according to the byte symbol BMRKffiJ, and supplied to the command embedding device 8 through the loading selector 6 1. In the manned request, "when it is judged as a cache error" The data cache control device 6 will output the data segment transfer request DTREQ to the 2nd cache control device 'and the response to the above data segment transfer request DTREq (data segment transfer response) DTACK is transferred from the 2 cache The data of the memory 2 or the main memory device is supplied to the instruction processing device 8 via the load data selector 6 together. In the storage request, when the cache hit is determined, it is selected according to the byte symbol B MR K The part of the data section of the marked cache line The stored data STRDAT of 8 is written to this part through the write selector 62. When writing to the primary data cache memory 6, the primary data cache control device 60 will supply the storage buffer to write SBWREQ is requested to the secondary cache control device 1 〇, thereby storing the stored data STRD AT, the data address DADRS 'and the byte symbol BMRK temporarily into the secondary cache memory 2 ^ in When a cache error occurs in the storage request, it is necessary to move-in the data section from the main memory device 4 or the secondary cache memory 2 to the cache memory. In FIG. 1, 9 3 is the transfer data Buffer. The data address DADRS (the tag bit above) of the data access address of the write access address of the cache error will be stored in the cache error of the data cache memory 6 in the write access at the time of the request Address and marked address) The common section data is read out from the secondary cache memory 2 or the main memory device 4 and stored to the transfer capital paper standard. It is applicable to the Chinese National Standard (CNS) Λ4 specification (210 ′ × 297 mm) I— II -Binding Μ (Please read the notes on the back before filling this page) 19-Printed A7 ___________ B7 by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (ιη material buffer 9 3. In order to release the wait for the command processing device 8 in the $ data transfer section of the above transfer data buffer The aforementioned write buffer 9 is provided. Furthermore, the data segment transfer request for transfer requires DAREQ to be supplied from the primary data cache control device 60 to the secondary cache control device 10. i: The write buffer 9 has a write address buffer 90, and a write data buffer 91, and a byte mark buffer 92. In the write address buffer 90, in the cache error of the primary data cache memory 6 during write access, the data address DADRS (in this embodiment is used as (The tag address of the physical page number and the tag address of the note used in the primary data cache 6). The above-mentioned write data buffer 91 supplies a memory area equivalent to a sector data area of the data portion 6 of the primary data cache 6, that is, a 16-byte memory area, and is marked according to the byte BMRK keeps the written data in the memory area. The byte symbol buffer (data character selection information buffer) 9 2 holds the byte symbol BMRK of the write data (stored data) held in the write data buffer 9 1. FIG. 2 shows the internal structure of the command processing device 8 in part. In this figure, three bus lines BUS 1, BUS 2, and BUS 3, each of which is 4 bits, are represented; 80 is used to control the execution of the commands described below and the sequence of the control command execution sequence. Control circuit. The instruction processing device 8 supplies the general-purpose register 8 1, and the general-purpose register 8 1 is used for data addresses and address registers, etc. ^ The lower 4 bits of the logical address LADRS calculated by the arithmetic unit 8 2 The paper is again applicable to the Chinese National Standard (CNS) 84 specifications (210X 297mm)-Approved clothing I set I '^ (please read the precautions on the back before filling the nest page) -20-Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative A7 ____B7 V. Description of invention (1δ) The data size of the bit and storage address is supplied to the decoder 84, and the byte symbol BMR Κ is generated from this. The calibrator 84 allocates the 4-byte bus BUS3 data to the 16-byte storage data bus in byte units (the storage data STRDAT bus of FIG. 1 is supplied. This allocation control It is performed according to the byte symbol BMRK formed by the decoder 83. For example, 'In the 4-bit address bit system supplied to the decoder 83, all the bits are logical values, when 〃, If the data size is 4 bytes, then the 4 bytes from the bottom of the byte symbol BMRK are set to logical values " " I " 'Thereby, the stored data of 4 bytes is allocated to 1 6 bytes of stored data on the lower side of the data bus 4 bytes. At this time, if the data size is 2 bytes, then the lowest byte of the byte symbol BMRK is 2 logical values of '1 ^, by Therefore, the 2-byte storage data can be arranged in the lower 2 bytes of the 16-byte storage data bus. In addition, the above data address DADRS is used: it will be generated in the arithmetic unit 8 2 The logical page number of the logical address of L AD RS is the physical data obtained by the conversion of the address conversion buffer with the data not shown in the figure. Number and its branch. In Figure 1, 9 5 is to determine whether the continuous data storage is an address comparator for the same cache line of the primary data cache memory 6. The address comparator 9 5 series comparison: write to the address buffer 9 3 the last stored data address DADR S, and the command processing device 8 output the data address DADRS this time, and input the comparison result to the primary data Cache control device 60. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) awaav I ι ^ ϋ m nn ^^^ 1-J., va (Please read the precautions on the back before filling in (This page) -21 A7 B7 5. Description of the invention (l9) ----.--.-- Installation-- (Please read the precautions on the back before filling in this page) The comparison result of the address comparator 9 5 In the case of coincidence, it means that the storage address before and after is to store the same cache line of the primary data cache memory 6. In this case, because the write data buffer 91 has the data storage area of the cache line, Therefore, the primary data cache control device 60 also receives the stored data for subsequent cache errors. In the write data buffer 9 1, and the output write requires the WBWREQ to obtain the write buffer 9. The primary data cache control device 6 0 also outputs the parallel output to this storage in addition to the output write request WBWR EQ Request S TRR EQ response (load / store response) L / SACK to the instruction processing device 8, so that the instruction processing device 8 can execute the next instruction. Figure 3 (A), Figure 3 (B) and Figure 3 (C ) Is to sequentially change the storage location of the stored data executed by a plurality of storage commands and display the status of its storage in the write buffer 9. For example, as shown in Figure 3 (A), at the data address DADRS = TAGi (tag address), IDXi (marked address), the stored data STRDAT = D〇, D1, D2, D3 (total 4 bits Tuple), byte symbol BMRK = Ministry of Economic Affairs, Central Bureau of Standards, Employee Consumer Cooperative Printed Charger, the capital charge is slowed down 1 in, if it is written, it will be written at the time of the meeting, the meeting will be made, the meeting will be made, the amount will be more Mistake, loss, fetch, fast 0 6 ο body 1 recall 1 record 1 take 1—I fast, G is A this T ο II let S refer to R D D A A D row address execution position is sufficient and sufficient energy and resources 9 and set Disposal ο Reason 1 Disposal order Requisition control and access control '9 orders faster 2 deposits. Cui Yi 3 is a 9-instruction, and the fetcher means that the second charge is transferred from the delivery section of the bank to the transfer zone of the transfer section to the common zone of the delivery of 8 materials. 4 If I set up a pretend memorizer or print a piece of paper with a suitable ruler, the A7 B7______ is printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy and Trade. 5. Description of the invention (20) Data address DADRS = TAGi, IDXi 'Stored data STDDAT = D4' D5 'D6' D8 (total ten ten bytes), byte symbol BMRK = ooool 1 1 1000000 ◦ 'This storage is the same cache line as the previous object , So the same 'data cache 6' as the last time is a cache error. At this time, the comparison result of the address comparator 95 is consistent, and because the valid data is stored in the write buffer 9, the byte mark buffer 9 2 is not reset (reset 1, but The primary data cache control device 60 sends the write request WBWREQ to the write buffer 9. As a result, as shown in FIG. 3 (B), these data will be stored in the write buffer 9. 4 bits The stored data D4, D5, D6, and D7 of the group are merged at the aligner 84 and stored in the write data buffer 91 of the 16-byte group. Each bit of the bit mark buffer 92 The meta-rule, for example, is formed at the RS (set / rest) flip-flop, and as shown in FIG. 3 (B), the byte buffer 9 2 The byte symbol corresponds to 8-byte data D0 ~ D8 and 8-bit is set to logic value. Furthermore, if the command processing device 8 continuously executes the data address DADRS = TAGi, IDXi, store data STRDAT = D8, D9, Dl〇, Dli (total 4 bytes), byte symbol BMRK = 0000000011110000 store command, because This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) II--n II · Ding I I- (please read the precautions on the back before filling this page) 23-Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs Print A7 _______B7 V. Description of the invention (21) This storage is the same cache line as the last object, so the same data cache memory 6 as the last time will be cached incorrectly. At this time, the address The comparison result of the comparator 95 is consistent, and because valid data has been stored in the write buffer 9, the byte mark buffer 92 is not reset but the write request WBWR EQ is supplied to write Into the buffer 9. As shown in Figure 3 (C), these data will be stored in the write buffer 9. The 4-byte storage data D 8 ~ D 1 1 is at the calibrator 84 The written data buffer 9 1 'byte symbol 9 2 that is merged and stored in 16 bytes corresponds to a total of 12 bytes of data DO ~ Dl 1 and makes 8 bits The element is set to a logical value " 1, 〇 Therefore, it is as if the content of the general purpose register is being used to back off As in the case of stacking on the memory, when the same section is continuously stored to become the same cache line placed on the cache memory, even if a cache error occurs, because it can The stored data is continuously stored in the write memory 9, so the waiting time of the command processing device can be shortened. Even when continuous data storage is performed on the same cache line on the primary data memory 6, the cache error can be prevented The resulting reduction in data processing performance. As shown in FIG. 1, the primary data processing control device 60 has: a flag indicating whether valid data is stored in the write buffer 9 (write buffer valid flag) 6 0 0 »this Flag 6 0 0 is in the initial state of microprocessor 1 initalized reset (power on reset) or power on reset (power on reset), the initial state is to maintain the logic value of the reset state (write buffer 9 There is no valid information). This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) n-1 ^ 1--f ^ lf I---I-: 1! ^ (Please read the notes on the back before filling in (This page) -24-206442 A7 ___B7 5. Description of the invention (22) Flag 6 0 0 In this reset state, if a write request WBWREQ is generated to the write buffer 9 due to a cache error in data storage, Then, it becomes the setting state that holds the logical value * 1 ^ (valid data exists in the write buffer 9). When the data cache memory 6 is updated once due to the data written into the buffer 9, the flag 6 0 0 returns to the reset state. The reset endpoint (reset by the input logic value) of the byte mark buffer 92 is 'for example' controlled by the inverse phase element of the above flag 600 holding the secondary data cache control device 6 . The transfer of the data section to the above-mentioned transfer data buffer 93 is completed by the data section transfer response D A T C K from the secondary cache control device 10 to the primary data cache control device 60. The data input terminal of the byte selection circuit 94 is combined with the data output terminal of the transfer data buffer 93 and the data output terminal of the write data buffer 91. Printed by the Ministry of Economic Affairs Central Standard Falcon Bureau Employee Consumer Cooperatives n--I -I--I taxi ^ I-1-1- m _ I Ding, τ (please read the precautions on the back and fill in this page). When the section data stored in the transfer data buffer 9 3 is registered in the cache line set by the primary data cache 6, the byte selection circuit 94 replaces the block data of the transfer data buffer 9 3 with the display The byte symbol BMRK of the above byte symbol buffer 92 writes the data in the data area on the data buffer 91, and supplies the replaced data to the primary data cache 6 »This action system According to the primary data cache control device 60, the data segment transfer response DTACK is performed. The byte selection circuit 9 3 shown in FIG. 4 has the option of transferring the data of the data buffer 9 3 or writing the data buffer 9 1 according to the control of the corresponding bit of the byte mark buffer 9 2 The selector of the data (Swl ector) 9 4 1. The selector 9 4 is in the corresponding writing mark buffer paper & degree is suitable for China National County (CNS) Λ4 specifications (2 〇 χ 297 Kg)-*-A7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy ___B7 Fifth, the invention description (23) When the bit of the device is a logical value, select the byte data written into the data buffer 91 and select the forwarding data when the logical value of the bit of the corresponding write mark buffer " Byte data of the buffer 93. The output of the byte selection circuit 94 is supplied to the primary data cache 6 via the write selector 62. Furthermore, in the storage access, when the primary data cache 6 hits, the write selector 62 directly selects the stored data from the command processing device 8 and supplies it to the primary data cache 6 ^ In the above-mentioned byte selection circuit 93, it is not necessary to write the stored data of the cache error to the primary data cache memory 6 as a new input, and to transfer the area of the data buffer 9 3 The writing of the segment data and the writing of the data into the data buffer 91 are selected by the byte symbol, and are performed separately. Therefore, the waiting time of this part of the command processing device 8 can be shortened. Although there is no special limitation in the microprocessor 1 of this embodiment, it uses IF (instruction fetch), D (instruction decoding), E (operation), A (memory access), and, W (write ) 5 stages of pipelines. The control is controlled by the sequence control circuit 80 shown in FIG. 2. In the IF stage, the instruction processing device 8 fetches instructions from the instruction cache memory 5 and the like. In the D stage ', the instruction processing device 8 decodes the instruction obtained from the I F stage and generates various control information. In the stage E ', the command processing device 8 performs data operations and address operations for carrying instructions and storing instructions in accordance with the control information generated in the stage D. In the A stage, the instruction processing device 8 uses the address and data calculated in the E stage for memory access. At this time, the primary data cache control device 60 will send this paper. The standard of the paper is applicable to the Chinese national standard (CNS M4 specification (2 丨 〇x 297 mm) _ 26-ί I * ^^^ 1 ^^^ 1 ^ n · ^^^ 1 — ^ ϋ \, 0¾- = ¾ (Please read the precautions on the back before filling in this page) Printed by the Central Bureau of Standards, Ministry of Economic Affairs, a shell industry consumer cooperative. V. Invention description (24) Take the detection result of the hit / mistake of the memory 6 and whether there is an interruption, etc. When the lock signal L ◦ of the lock pipeline is set to assert, the state of each stage of 'IF' D, E 'a will be maintained and The storage line is locked. When the pipeline lock is locked at stage A, after its release, the processing of the 'command processing device 8 will be transferred to the W stage, and once at the W stage' when the instruction is stored The data cache memory and the write buffer are used for writing, and in the case of a load command, the register is written. Figure 5 shows an example of control logic related to the data storage of the primary data cache control device 60. The logic system shown in the figure considers the above-mentioned pipeline locking. In the figure, 'D CM ISS is 1 Cache error signal of secondary data cache 6; it is the signal output in primary data cache 6. BLKMCH is the data section consistent signal; it is the signal output from address comparator 95. WBFRVLD system The purlin corresponding to the above flag 6 0 0 shows whether there is valid data stored in the write register 9. LOCK is the pipeline lock signal. STRREQ, LRDREQ, DTACK, L / SREQ, WBWREQ, DTREQ are the above requirements Signals. In this example, these signals and flags are set to positive logic. FF 1 'FF3 in the figure is R / S flip-flop, FF2, FF4, FF5 are D-type latches ( latch), G1 ~ G3 is OR gate (〇R gate), G4 is AND gate (This paper standard is applicable to China National Standard Falcon (CNS) A4 specification (2〗 0 > < 297 Gongluan) (Please read the back side first Matters needing attention and then fill out this page)-installed ·
、1T -27 - 經濟部中央標準局負工消費合作社印11 A7 B7___ 五、發明説明（25) AND gate) 、G5 爲反相器（inverter)。 F F 1 、F F 2係與無重疊（no-overlap) 2相時鐘（ clock)信號的一方的時鐘信號做同步動作；F F B 、 FF 4、FF 5則係與無重疊2相時鐘信號的另一方的時 鐘信號做同步動作。 在圖5中，在產生儲存要求（STRREQ=1)， 並因而使1次資料快取失誤產生（DCMISS=1)， 在此時在寫入緩衝器9內存在著有效資料（ WBFRVLD=1)，而且，在位址比較器95的比較 結果得知此次儲存並不是與上一次的儲存係同一快取線（ B L K M C Η * = 1 )(記號*表示與無此記號的信號爲邏 輯反相的信號），使信號S1爲邏輯值”1〃 。即是，在 儲存資料並不是設爲同一快取線的位址的資料時，將信號 S1設爲邏輯值。此時，因爲無法對儲存資料的寫 入緩衝器9進行寫入，所以使載入儲存應答L/SACK 設定爲否定（negate)，而且，爲了使管線鎖定而將鎖定 信號LOCK設爲肯設（assent )。管線鎖定狀態及載入 儲存應答L/S A C K的否定狀態要等待：資料正段轉送 應答D TA C K被設爲肯定，爲1次資料快取記憶體6的 儲存對像的輸入（entry)被轉送，才會被解除。再者， 在資料儲存中，在上述以外的狀態下，載入儲存應答 L / S A C K被肯定爲高準位（high level)。指令處理 裝置8則在A階段的所定時刻（timing)對載入儲存應答 L / S A C K 做取樣（sampling )。 本紙張尺度適用中國國家標率（CNS ) Λ4規格（210X 297公釐） ---L---„----裝------訂------I (請先閱讀背面之注意事項再填寫本頁) -28 - 經濟部中央標準局員工消費合作社印製 A7 _ __B7 五、發明説明（26) 在以下的場合，對寫入緩衝器9的寫入要求 WBWR E Q會被設爲肯定。 1) 有儲存要求（STRREQ=1)，對此，1次 資料記億體6快取失誤（DCMISS=1)，而且，在 此時，寫入緩衝器9內不存在有效資料時（ WBFRVLD*=1)，即是，寫入緩衝器9的空著時 〇 2) 有儲存要求（STRREQ==1)，對此，1次 資料記憶體6快取失誤（DCMISS = 1)，而且，在 此時，寫入緩衝器9內存在著有效資料（ WB FRVLD= 1 )而且位址比較器9 5檢出一致時（ BLKMCH=1)。 若對寫入緩衝器9的寫入要求WBWRE Q被設爲肯 定，則F F 1會被設爲設定lsetl狀態，顯示在寫入緩衝 器9內存在有效資料的信號WB D R V L D會被設爲肯定 狀態。 在上述1 )的狀態中，資料區段轉送要求DTREQ 會被設爲肯定。在其它場合，資料區段轉送要求 D T R E Q也會被設爲肯定，係指在等待寫入緩衝器9變 空的狀態（WB FRB SY= 1 )，有資料區段轉送應答 時（DTACK=1)。依資料區段轉送應答，且有顯示 資料區段轉送完成的資料區段轉送應答（DTACK = 1 )，則FF1會被重置（reset)，並使顯示寫入緩衝器 9內存在著有效資料的信號WB F RV L D會被設爲否定 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） I - ! - Γ I— Is I I . 1 I - II I —^1 (請先閲讀背面之注意事項再填寫本頁) -29 經濟部中央標準局員工消費合作社印製 Λ7 ______Β7____ 五、發明説明（27) (WBFRVLD=〇)。若資料區段轉送應答 DTACK被設爲肯定（DTACK=1 )，則寫入緩衝 器9的收藏情報會經由位元組選擇電路而寫入1次資料快 取記憶體6。 再者，由與資料載入（data lead )有關的圖所未示 的控制邏輯所產生的用以載入應答及管線鎖定的信號會被 應到閘G 2 ，G 3。 圖6顯示’在本實施例的微處理器1中，在執行儲存 指令時的各管線階段的動作。圖7顯示，在本實施例的微 處理器1中，在執行載入指令時的各管線階段的動作。在 圖6及圖7中’指令快取資料記憶體5 0 0及指令快取標 籤記憶體5 0 1係構成1之指令1次快取記憶體5的資料 部及標籤部’而資料快取標籤記憶體6 0 0及資料快取資 料記憶體6 0 1則構成1次資料快取記憶體5的資料部及 標籤部。 在圖6及圖7的I F階段中，指令位址暫存器I R輸 出指令位址I ARD S，並送出指令讀出要求 I FREQ到1次指令快取控制裝置5 0。接受了此要求 I FREQ的1次指令快取控制裝置5 0在1次指令快取 命中時，會將讀出1次指令快取記憶體5的指令碼經過指 令選擇器5 1而輸出到指令處理裝置8 ，並輸出指令讀出 應答I FACK。另一方面，接受了此要求I FREQ的 1次指令快取控制裝置5 0在1次指令快取失誤時，會將 由2次快取控制裝置1〇所區段轉送的指令碼經由指令選 本紙張疋度適用中國國家標準（CNS ) Λ4規格（210X 297公漦） - In - il· 1^1 ^^1 1^1 ml ^^1 ^ii 、-· (請先聞讀背面之注意事項再填寫本頁) -30 - A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 28) 1 -PB9 揮 器 5 1 而 輸 出 到 指 令 處 理 裝 置 8 9 並 輸 出 指 令 讀 出 應 答 1 I I F A C K 〇 再 者 ♦ 使 用 指 令 用 位 址 變 換 緩 衝 器 ( 指 令 1 1 I T L B ) 檢 查 是 否 可 以 對 該 負 進 行 存 取 9 如 果 不 能 進 行 1 1 1 存 取 則 使 例 外 處 理 發 生 〇 請 先 1 1 在 圖 6 及 圖 7 的 D 階 段 中 > 接 受 白 I F 階 段 的 指 令 碼 1½] 讀 背 1 1 會 被 an* ax 定 於 指 令 緩 衝 器 暫 存 器 I Β R 9 且 被 設 定 於 指 令 緩 面 1 I 衝 1 器 暫 存 器 I B R 的 指 令 碼 則 會 由 指 令 解 碼 器 I D 所 解 碼 事 項 1 I 且 再 1 * 指 令 解 碼 器 I D 會 依 此 解 碼 的 結 果 而 產 生 各 種 控 制 情 導 報 本 裝 C I 1 〇 頁 1 I 在 圖 6 及 圖 7 的 E 階 段 中 依 產 生 D 階 段 的 控 制 情 報 1 1 1 C I 1 而 從 暫 存 器 8 1 讀 出 資 料 * 運 算 器 0 U 則 使 用 所 讀 1 1 出 的 資 料 而 進 行 位 址 計 算 並 輸 出 用 以 做 資 料 存 取 的 邏 輯 位 1 訂 址 L A D R S 0 從 位 址 的 下 位 4 位 元 及 表 示 資 料 大 小 的 控 1 1 制 情 報 而 產 生 位 元 組 記 號 B Μ R Κ 0 在 儲 存 的 場 合 暫 存 1 | 器 8 1 會 輸 出 儲 存 資 料 S T R D A T 到 儲 存 資 料 暫 存 器 1 I S D R A 〇 然 後 在 指 令 解 碼 器 I D 對 儲 存 指 令 解 碼 時 » 1 I 指 令 處 理 裝 置 8 輸 出 儲 存 要 求 S T R R E Q 到 1 次 資 料 快 1 取 控 制 裝 置 6 0 〇 另 — 方 面 > 在 指 令 解 碼 器 I D 對 載 入 指 1 1 令 進 行 解 碼 時 指 令 處 理 裝 置 8 則 輸 出 載 入 要 求 1 1 L R P R E Q 到 1 次 資 料 快 取 控 制 裝 置 6 0 〇 在 圖 6 及 圖 1 | 7 中 這 些 要 求 S T R R E Q 、 L R D R E Q 係 包 含 於 控 1 I 制 情 報 C I 1 〇 1 1 I 在 固 圖 6 及 圖 7 的 A 階 段 中 來 白 運 算 器 0 U 的 上 述 趣 1 I I ±Q. 輯 位 址 L A D R S 會 被 寫 入 記 億 體 位 址 暫 存 器 Μ A R A 〇 1 1 1 本紙張歧適财關轉準（CNS) M規格（2iGX 297公餐） _ 31 - 經 濟 部 中 k 標 準 為 員 工 消 費 合 作 社 印 製 A7 B7 五、發明説明（ 29) 1 然 後 9 使 用 此 邏 輯 位 址 L A P R S 而 對 資 料 快 取 標 籤 記 憶 1 I 體 6 0 0 及 資 料 用 位 址 變 換 緩 衝 器 ( 資 料 T L B ) 進 行 存 1 1 I 取 〇 並 由 比 較 電 路 C 0 Μ P 1 對 讀 出 標 Mr 載 記 憶 體 6 0 0 以 1 1 做 爲 快 取 標 籤 的 物 理 負 位 址 、 及 » 讀 出 於 資 料 T L B 的 物 請 先 1 1 理 頁 位 址 做 比 較 0 然 後 » 進 行 1 次 資 料 快 取 記 憶 體 6 的 位 閱 背 1 元 判 定 0 而 且 > 使 用 資 料 T L B 中 的 存 取 保 護 情 報 來 檢 查 1¾ 之 1 1 是 否 可 以 對 該 頁 進 行 存 取 > 如 果 不 可 進 行 存 取 則 使 例 外 處 意 事 項 Γ I 理 產 生 0 再 然 後 » 檢 查 1 次 資 料 快 取 記 憶 ΟΛι 體 6 的 命 中 / 失 誤 9 有 寫 本 頁 '—^ %. 1 -fnT- m 插 隊 儲 存 緩 衝 器 7 是 否 已 滿 寫 入 緩 衝 器 9 內 是 否 收 1 1 藏 著 有 效 資 料 等 並 決 定 是 否 要 將 管 線 鎖 定 e 如 果 不 需 要 1 1 鎖 定 則 輸 出 載 入 / m 存 應 答 L / S A C K 到 指 令 處 理 裝 1 訂 置 8 0 在 必 需 要 鎖 定 時 將 管 線 鎖 定 信 號 L 0 C K 設 爲 肯 1 I 定 以 防 止 I F D Ε A 的 各 階 段 的 閂 A/f> 鎖 值 更 新 並 1 1 I 防 止 對 W 階 段 寫 入 致 能 ( en able ) 信 號 的 輸 出 而 使 管 線 1 1 1 被 鎖 定 0 然 後 等 待 直 到 不 再 需 要 A/l> 鎖 定 然 後 9 再 輸 出 載 1 «、，··· 入 / 儲 存 應 答 L / S A C K 到 指 令 處 理 裝 置 8 » 以 使 W 階 1 段 的 寫 入 致 能 被 輸 出 0 1 I 在 圖 6 及 圖 7 的 W 階 段 中 > 在 儲 存 指 令 的 場 合 9 將 資 1 I 料 寫 入 1 次 資 料 快 取 記 憶 體 6 或 是 寫 入 緩 衝 器 9 而 完 成 1 I 該 儲 存 指 令 的 執 行 〇 在 載 入 指 令 的 場 合 將 讀 出 於 記 億 體 1 1 6 〇 0 1 的 儲 存 寫 入 暫 存 器 8 1 > 而 完 成 該 載 入 指 令 的 執 行 1 1 1 在 上 述 儲 存 指 令 的 管 線 中 » 將 寫 入 緩 衝 器 9 爲 空 的 時 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） Α7 Β7 五、發明説明（3〇) 候在（A) 1次資料快取記憶體命中，（B) 1次資料快 取記憶體失誤，的場合分別做說明。 在上述（A)的1次資料快取記憶體命中的場合，如 圖6所示’將在A階段讀出於暫存器8 1的資料在W階段 寫入1次資料快取記憶體6的資料快取記億體6 0 1及儲 存緩衝器7。 在上述（B )的1次資料快取失誤的場合，在圖6的 A階段判明1次資料快取失誤。此時，因爲寫入緩衝器9 是空的’所以認爲若將其寫入寫入緩衝器9便可以不必將 管線鎖定’並對W階段輸出寫入緩衝器寫入要求 WBWREQ。而且，輸出資料區段轉送要求DTREQ 到2次快取控制裝置1 〇。在w階段則將儲存位址 S TRAD R S寫入寫入位址緩衝器9 〇，儲存資料 STRDAT寫入寫入資料緩衝器91，位元組記號寫入 位元組記號緩衝器9 2，並完成該儲存指令的執行》 若從2次快取控制裝置1 〇輸出資料區段轉送應答（ 完成報告）DTACK到1次資料快取控制裝置60，則 位元組選擇電路9 4會選擇寫入資料緩衝器9 0的值以做 爲對應於保存在位元組記號緩衝器9 2的位元組記號 BMRK的邏輯值*1，的位元組資料；並選擇區段轉送 資料B T D以做爲對應於位元組記號B M R K的邏輯值'^ 〇"的位元組資料，而將共計1 6位元組的資料寫入1次 資料快取記憶體6。其結果爲：1次資料快取記憶體6在 寫入區段轉送資料B TD後，會成爲與寫入儲存資料 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. -s 鲮濟部中央榡芈局員工消費合作祍印製 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（31) S TRDAT者具有相同狀態。而且，會將位元組記號緩 衝器9 2值，寫入位址緩衝器9 0的值’在位元組選擇電 路9 4所合成的區段轉送資料BTD寫入儲存緩衝器7。 在載入指令的管線中，在1次資料快取記憶體6命中 的場合，如圖7所示的，在A階段存取1次資料快取記憶 體所讀出的資料，在W階段則寫入汎用暫存器8 1 。 在載入指令的管線中，在1次資料快取記憶體6失誤 的場合，如圖7所示的，管線會被鎖定，並在後續指令的 處理被抑制的狀態下，將區段轉送要求D TR E Q輸入到 2次快取控制裝置1 0。在2次快取控制裝置1 〇輸出區 段轉送完成的應答D TA C K時，再將區段轉送資料寫入 1次資料快取記憶體6及汎用暫存器8 1 » 在上述儲存指令的管線中，在快取失誤時寫入緩衝器 9不是空著的場合，在A階段使收藏於寫入緩衝器9的資 料位址D A D R S及後續的儲存命令的資料位址 D A D R S在位址比較器9 5做比較，並依其比較結果將 動作在（C)位址比較爲一致，及，（D)位址比較爲不 一致，的場合分別的做說明》 上述（C)的位址比較爲一致的場合意味著：在A階 段有1次資料快取失誤，且由位址比較器9 5可知位於寫 入緩衝器9的上一次的儲存指令的資料位址與這次的儲存 指令的資料位址係爲同一資料區段的位址。即是，意味著 :雙方的資料位址的標籤住址及註標位址相同，雙方的資 料位址的標籤位址及註標位址相同，雙方的儲存資料應該 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公1 ) n·^ m m ^ϋ· f 一* 0¾ *vs (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 __B7 五、發明説明（32) 要收藏在1次資料快取記憶體的同一快取線內。 因此，不需要管線鎖定，在w階段中，將儲存資料收 藏在由這次儲存的位元組記號所指位的位置的寫入資料緩 衝器9 1內。位元組記號緩衝器9 2的值則以：取得起始 時寫入的值及後續儲存指令的值的每一位元的邏輯和的值 來更新。但寫入位址緩衝器9 0則不做更新。然後，若存 在從2次快取控制裝置1 〇到轉送資料緩衝器9 3的區段 轉送完成的應答DTACK，則使寫入資料緩衝器9 1的 內容及轉送資料緩衝器9 3的內容在位元組選擇電路9 4 合成’並將其寫入1次資料快取記憶體6。 上述（D )的位址比較爲不一致的場合係：位於寫入 緩衝器9 3的上一次的儲存指令的資料位址與這次的儲存 的資料位址在標籤位址或是註標位址爲不一致，雙方的儲 存資料應該是收藏在1次資料快取記憶體的不同快取線。 因此，對這次的儲存指令不必要應載入/儲存應答 L /S A C K ’而等待前面的快取失誤的轉送完成。在該 轉送成後，由1次資料快取記憶體6的快取失誤，在W階 段，將其儲存指令的資料位址DADR S，儲存位址 STRDAT’位元組記號BMRK寫入寫入緩衝器9 ， 並繼續執行指令。 在寫入緩衝器內收藏著有效資料的狀態下，執行載入 指令，即使有1次資料快取失誤，也能夠由位址比較器 9 5進行判定動作。譬如說，在其判定結果爲一致的場合 ，該載入指令係指對收藏於寫入緩衝器9的資料的載入。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） n _*· I 1'-I I I I I I m m ^1« 、T (請先閲讀背面之注意事項再填寫本頁) -35 - A7 B7 ^06442 五、發明説明（33) 此時，雖然該載入指令的A，W階段必需做管線停頓（ pipeline stall)，但是因爲必要的資料會被收藏在寫入 緩衝器中，所以不需要對應著該載入指令而再一次送出區 段轉送要求。而在寫入緩衝器9中的指令的區段轉送完畢 之後再度對1次資料快取記憶體6做存取，讀出載入資料 (load data)，並將所讀出的載入資料在W階段寫入暫 存器8 1內。 在寫入緩衝器內收藏著有效資料的狀態下，在執行載 入指令而且在1次資料快取失誤時的比較器95的判定動 作的結果爲不一致的場合，會使管線暫停（stall)，並 在寫入資料緩衝器9變成空的之後，才會依該載入指令而 输出區段轉送要求D TR E Q。此係因爲2次快取控制裝 置1 0無法同時的處理2種類的區段轉送要求之故。在2 次快取轉送裝置10輸出對應該區段轉送要求的應答 DT ACK時’ 1次資料快取控制裝置6 0會將區段轉送 了的資料寫入1次資料快取記憶體6及泛用暫存器8 1。 上述的實施例具有以下的作用效果： (1)如同使汎用暫存器81的內容退避到設於記憶 體上的堆疊一般’在連續的儲存向置於1次資料快取記憶 體6上的同一快取線的同一區段時，藉由以位址比較器 9 5將其檢出’則即使是一旦快取失誤發生後的快取失誤 ’1次資料快取控制裝置60也會使此儲存資料持續的保 持在寫入緩衝器9 ，儲存資料在保持於寫入緩衝器9的狀 態則由對儲存的L/S A CK而回到指令處理裝置8。由 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 、ys 經濟部中央標隼局員工消費合作社印製 36 -QR _ 經濟部中央標隼局員工消費合作社印繁 A7 B7 五、發明説明（34) 此，指令處理裝置8可認知該寫入存取若是儲存指令的執 行完成，並能夠進而控制下一個命令的執行。由此，可縮 短指令處理裝置8的等待期間，在1次資料快取記憶體上 即使是資料連續的儲存向同一快取線時’也能夠阻止因快 取失誤所引起的資料處理性能的下降。 (2 )在此期間，快取失誤的區段資料會從2次快取 記億體2或主記憶體裝置4轉送到轉送資料緩衝器9 3。 轉送到轉送資料緩衝器9 3的資料及寫入緩衝器9 1的資 料則被追加到1次資料快取記憶體6以做爲新的輸入。此 時，位元組選擇電路9 4則依位元組記號BMRK而將轉 送資料緩衝器9 3的區段資料，及，寫入資料緩衝器9 1 的資料合成。合成了的資料則被追加到1次資料快取記憶 體6以做爲包含快取失誤的儲存資料的新的輸入。因此， 並不需要將：上述快取輸入的追加，以及，轉送資料緩衝 器9 3的區段資料的寫入，及，以位元組記號來做選擇並 寫入寫入資料緩衝器9 1的資料，分開的來做處理，以此 點而言，也能夠縮短指令處理裝置8的等待期間。 (3 )對以管線方式來執行指令的指令處理裝置，上 述快取控制裝置6 0在依儲存指令而要求記憶體寫入存取 時（STRREQ=1)會送回：依此要求的寫入存取係 爲快取命中的形態（DCMISS = 〇)，及，要求的寫 入存取係爲快取失誤（DCMI SS = 1)且在上述寫入 資料緩衝器內並沒有保持著有效資料的狀態（ WBFRVLD=〇)，及，依此要求的寫入存取記憶體 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝- 、ys 37 - 經濟部中央標準局員工消費合作社印製 A7 ______ B7 五、發明説明（35 ) 係爲快取失誤（DCM I S S = 1 )且寫入資料緩衝器內 保持著有效資料（WB FRVLD= 1 )而且位址比較器 係檢出一致（B LKMCH= 1 )的狀態的種種對該記憶 體存取要求的應答（L/SACK)，再者，對應此記憶 體存取要求的寫入存取在，快取失誤（DCM I S S = 1 )且在寫入資料緩衝器內保持著有效資料（ WB F RVLD= 1 )且位址比較器檢出不一致（ BLKMCH=〇)的狀態下，指示管線鎖定（KOCK =1 )到指令處理裝置，其後，快取失誤的位址的區段資 料會等待到從上位記憶裝置轉送到上述轉送資料緩衝器完 成’並藉由管線鎖定的解除及供應對該記憶體存取的應答 而能夠採用管線及整合以實現上述（1 )的控制。 雖然以上是以實施例來具體的說明了本發明者的發明 ’但是本發明並不僅限於這些實施例。當然，在不脫離其 要旨的範圍內能夠有種種的變形。 譬如說，也可以是：標籤位址及註標位址的位元收並 不限於上述實施例中者，或是，並快取標籤也不限於上述 實施例中的物理頁號碼而是如包含重置（Of fsef )的一部 份的情報。再者，快取記憶體也可以是邏輯快取（logic cache )。再者，也可以省略上述實施例的2次資料快取 記憶體。 雖然在以上的說明中係以本發明者的發明的利用領域 爲適用於微處理器來做說明，但是本發明並不僅限於此而 也能夠適用於所謂大型系統（main frame)。本發明至少 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公趟） (請先閱讀背面之注意事項再填寫本頁) —装· 訂 -38 - Λ7 一 B7 五、發明説明（36 ) 也夠被廣泛的適用於具有採用交換（swap)方式的快取記 憶體的系統（syston)。 將由本專利發明中所公示的發明中的具代表性者所能 夠得到的效果簡單的說明的話，係如下所述： 經濟部中央標準局員工消費合作社印製 ------1--： -¾衣—— (請先閱讀背面之注意事項再填寫本頁) 即是，在執行記憶體存取或是儲存指令之時發生快取 記憶體快取失誤的場合，將快取失誤的區段資料從上述記 憶裝置轉送並追加到快取記憶體以做爲新的輸入，在採用 交換方式者中，就好像使汎用暫存器的內容退避到設於記 憶體上的堆疊區域的場合一般，在快取記憶體上連續的對 置於同一快取線的同一區段做儲存時，藉由位址比較器將 其檢出，而在一旦發生快取失誤後的快取失誤中，快取控 制裝置也能夠連續的將此儲存資料保持在寫入緩衝器內。 儲存資料在保持於寫入緩衝器的狀態依對儲存的應答而被 送回到指令處理裝置。由此，指令處理裝置可認知該寫入 存取或儲存指令的執行完成，並能夠進而控制下一個命令 的執行。因此，能夠縮短指令處理裝置的等待期間，而在 即使是在資料連續的儲存到同一快取記憶體上的同一快取 線之時，也能夠將快取失誤引起的資料處理性能的下降減 到最小。 在交換方式中，快取失誤的區段資料係從上位記憶體 裝置轉送到轉送資料緩衝器。選擇電路則依位元組記號將 轉送資料緩衝器的區段資料及寫入資料緩衝器的資料合成 。合成了的資料則被追加到快取記億體以做爲包含快取失 誤的儲存資料的新的輸入。因此，不需要將上述快取輸入 本紙張尺度適用中國國家標準（CNS〉A4規格（210X 297公釐） -39 - A7 t442 B7 五、發明説明（37) 的追加，及，轉送資料緩衝器的區段資料的寫入，以及， 以位元組記號來做選擇並將寫入資料緩衝器的資料寫入， 分開的進行，以此點而言，也能夠縮短指令處理裝置的等 待期間。 ------:--•裝-- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 40, 1T -27-Printed by the National Bureau of Standards, Ministry of Economic Affairs, Consumer Labor Cooperatives 11 A7 B7___ V. Description of invention (25) AND gate), G5 is an inverter (inverter). FF 1 and FF 2 are synchronized with the clock signal of one side of the no-overlap 2-phase clock signal; FFB, FF 4, and FF 5 are the same as the clock signal of the other side of the non-overlap 2-phase clock signal. The clock signal is synchronized. In FIG. 5, a storage request (STRREQ = 1) is generated, and thus a data cache error is generated (DCMISS = 1), at this time, there is valid data in the write buffer 9 (WBFRVLD = 1) And, the comparison result of the address comparator 95 knows that this storage is not the same cache line as the previous storage (BLKMC Η * = 1) (mark * indicates that the signal without this mark is logically inverted Signal), so that the signal S1 is a logical value "1". That is, when the stored data is not set to the data of the same cache line address, the signal S1 is set to a logical value. At this time, because the storage cannot be The data write buffer 9 writes, so the load storage response L / SACK is set to negate, and the lock signal LOCK is set to be asserted to lock the pipeline. The pipeline lock status and The negative state of loading the storage response L / SACK must wait: the data forward segment transfer response D TA CK is set to affirmative, and the input of the storage object of the data cache 6 is transferred once, and then it is Cancel. Furthermore, in the data storage, other than the above In the state, the load and storage response L / SACK is definitely at a high level. The instruction processing device 8 samples the load and storage response L / SACK at the timing of the A stage. This paper scale is applicable to China National Standard Rate (CNS) Λ4 specification (210X 297mm) --- L --- „---- installed ------ ordered ------ I (please read first (Notes on the back and then fill out this page) -28-A7 _ __B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of invention (26) In the following cases, the write request to the write buffer 9 WBWR EQ meeting Was set to positive. 1) There is a storage request (STRREQ = 1), for this, the data is recorded once for a cache error (DCMISS = 1), and at this time, when there is no valid data in the write buffer 9 (WBFRVLD * = 1), that is, when the write buffer 9 is empty 〇2) There is a storage request (STRREQ == 1), for this, a data memory 6 cache error (DCMISS = 1), and, in At this time, when there is valid data in the write buffer 9 (WB FRVLD = 1) and the address comparator 95 detects a match (BLKMCH = 1). If the write request to the write buffer 9 WBWRE Q is set to positive, FF 1 will be set to set lsetl state, the signal WB DRVLD showing that there is valid data in the write buffer 9 will be set to positive . In the state of 1) above, the data segment transfer request DTREQ will be set to positive. On other occasions, the data segment transfer request DTREQ will also be set to affirm, which refers to the state of waiting for the write buffer 9 to become empty (WB FRB SY = 1), when there is a data segment transfer response (DTACK = 1) . According to the data segment forwarding response, and there is a data segment forwarding response indicating that the data segment forwarding is completed (DTACK = 1), FF1 will be reset (reset), and the display write buffer 9 contains valid data The signal WB F RV LD will be set to deny that the paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) I-!-Γ I— Is II. 1 I-II I — ^ 1 (Please read first (Notes on the back and then fill out this page) -29 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Λ7 ______ Β7 ____ 5. Description of the invention (27) (WBFRVLD = 〇). If the data segment transfer response DTACK is set to affirmative (DTACK = 1), the collection information written to the buffer 9 will be written to the data cache 6 once via the byte selection circuit. Furthermore, the signals generated by the control logic not shown in the figure related to the data lead to load the response and the pipeline lock will be applied to the gates G 2 and G 3. Fig. 6 shows' in the microprocessor 1 of this embodiment, the actions of each pipeline stage when executing a storage instruction. Fig. 7 shows the actions of each pipeline stage when the load instruction is executed in the microprocessor 1 of this embodiment. In Figs. 6 and 7, 'instruction cache data memory 5 0 0 and instruction cache tag memory 5 0 1 constitute the instruction 1 primary cache memory 5 data section and label section' and the data cache The tag memory 6 0 0 and the data cache data memory 6 0 1 constitute the data part and the tag part of the primary data cache memory 5. In the I F stage of FIG. 6 and FIG. 7, the command address register I R outputs the command address I ARD S, and sends the command read request I FREQ to one command cache control device 50. Accepted this request I FREQ 1 instruction cache control device 5 0 When an instruction cache hits, the instruction code of the 1 instruction cache memory 5 is read out through the instruction selector 5 1 and output to the instruction The processing device 8 outputs an instruction read response I FACK. On the other hand, the one-time command cache control device 50 that accepted this request I FREQ will select the command code transferred from the section of the second-time cache control device 10 through the command selection when the first command cache error occurs. Paper roughness is applicable to China National Standard (CNS) Λ4 specification (210X 297 Gongluan)-In-il · 1 ^ 1 ^^ 1 1 ^ 1 ml ^^ 1 ^ ii,-· (please read the notes on the back first (Fill in this page again) -30-A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (28) 1-PB9 Swipe 5 1 and output to the command processing device 8 9 and output command read response 1 IIFACK 〇Furthermore, use the address conversion buffer for instructions (instruction 1 1 ITLB) to check whether the negative access is possible. 9 If 1 1 1 access is not possible, an exception will occur. 1 1 first in Figure 6 and In the phase D of Fig. 7 > accept the instruction code of the white IF phase 1½] read back 1 1 will be an * ax set in the instruction buffer register I Β R 9 and The instruction code set in the instruction buffer 1 I flushes 1 register IBR will be decoded by the instruction decoder ID 1 I and then 1 * The instruction decoder ID will generate various control reports according to the decoding result. This installed CI 1 〇 Page 1 I generated the control information of the D stage in the E stage of FIGS. 6 and 7 1 1 1 CI 1 and read the data from the register 8 1 * The calculator 0 U uses the read 1 1 Calculate the address of the output data and output the logical bits used for data access 1 Addressing LADRS 0 Control the data from the lower 4 bits of the address and indicate the size of the data 1 1 Generate the byte symbol B by controlling the information Μ R Κ 0 Temporary storage 1 | Device 8 1 will output the stored data STRDAT to the storage data register 1 ISDRA 〇 Then in the instruction decoder ID to the storage instruction When decoding »1 I The instruction processing device 8 outputs the storage request STRREQ to one time. The data is quickly fetched. The control device 6 0 〇 Another-aspect> When the instruction decoder ID decodes the load instruction 1 1 order, the instruction processing device 8 Output load request 1 1 LRPREQ to primary data cache control device 6 0 〇In Figure 6 and Figure 1 | 7 these requests STRREQ, LRDREQ are included in the control 1 I control information CI 1 〇1 1 I in Figure 6 And the above-mentioned fun 1 II ± Q of the white operator 0 U in the A stage of FIG. 7. The edited address LADRS will be written into the register of the address of the billion-element address Μ ARA 〇1 1 1 (CNS) M specification (2iGX 297 meal) _ 31-The Ministry of Economy ’s k standard prints A7 B7 for employee consumer cooperatives V. Description of invention (29) 1 then 9 Use this logical address LAPRS to cache label data 1 I body 6 0 0 and The material is stored in the address conversion buffer (data TLB). 1 1 I takes 0 and the comparison circuit C 0 Μ P 1 reads the target Mr. on-board memory 6 0 0 with 1 1 as the physical negative bit of the cache tag Address, and »the things read from the data TLB, please first compare the page address 1 1 to compare 0 and then» perform 1 data cache memory 6 bit read back 1 yuan judgment 0 and > use the data in the TLB Get protection information to check whether 1 of 1 1 of 1 1 can access the page > if it is not accessible, make exceptions Γ I generate 0 and then »check 1 data cache memory ΟΛι body 6 hit / Mistake 9 has written this page '— ^%. 1 -fnT- m The queue storage buffer 7 is full. Is the write buffer 9 received? 1 It contains valid data and decides whether to lock the pipeline. If not Need 1 1 lock, output load / m save Response L / SACK to the command processing device 1 Set 8 0 Set the pipeline lock signal L 0 CK to 1 when the lock is necessary. I I set to prevent the latch A / f > lock value update and 1 at each stage of IFD Ε A 1 I prevent the output of the write enable signal (enable) to the W stage to cause the pipeline 1 1 1 to be locked 0 and then wait until the A / l > lock is no longer needed and then output 9 to load 1 «,, ... / Store the response L / SACK to the command processing device 8 »to enable the write enable of the W stage 1 segment to be output 0 1 I In the W stage of FIG. 6 and FIG. 7 > in the case of storing the command 9 it will cost 1 I The data is written to the data cache memory 6 or the write buffer 9 once to complete 1 I The execution of the storage command 〇 In the case of the load command will be read out of the memory 1 1 6 〇0 1 storage write Into register 8 1 > and complete the execution of the load instruction 1 1 1 on In the pipeline for storing instructions »When the write buffer 9 is empty 1 1 1 1 This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) Α7 Β7 5. Invention description (3〇) (A) Once the data cache memory hits, (B) Once the data cache memory fails, each case will be explained separately. In the case of the primary data cache memory hit in (A) above, as shown in FIG. 6, the data read from the register 8 1 in the A stage is written into the primary data cache 6 in the W stage The data cache memory is 100 million and storage buffer 7. In the case of the above-mentioned (B) primary data cache error, the primary data cache error is identified at the stage A of FIG. 6. At this time, since the write buffer 9 is empty, it is considered that if it is written to the write buffer 9, it is not necessary to lock the pipeline, and the write buffer write request WBWREQ is output at the W stage. Furthermore, the output data section transfer request DTREQ to the secondary cache control device 10. At stage w, the storage address S TRAD RS is written to the write address buffer 90, the stored data STRDAT is written to the write data buffer 91, and the byte symbol is written to the byte symbol buffer 92, and Completion of the execution of the storage command "If the response (done report) DTACK is output from the secondary cache control device 10 output data section to the primary data cache control device 60, the byte selection circuit 94 will select to write The value of the data buffer 90 is regarded as the byte data corresponding to the logical value * 1 of the byte symbol BMRK stored in the byte symbol buffer 92; and the segment transfer data BTD is selected as The byte data corresponding to the logical value of the byte symbol BMRK '^ 〇 ", and a total of 16 bytes of data is written to the data cache memory 6 once. The result is: Once the data cache 6 transfers the data B TD in the write section, it will become and write the stored data. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) (please Read the precautions on the back and then fill out this page). Installed. -S Zangji Ministry of Economy, Central Bureau of Public Affairs Employee Consumer Cooperation Co., Ltd. Printed A7 B7 printed by the Employee Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs 5. Invention Instructions (31) Have the same status. In addition, the value of the byte mark buffer 92 and the value written in the address buffer 90 are written into the storage buffer 7 in the block transfer data BTD synthesized by the byte selection circuit 94. In the pipeline of the load command, when the data cache memory 6 hits once, as shown in FIG. 7, the data read by the data cache memory is accessed once in the A stage, and in the W stage Write to the general purpose register 8 1. In the pipeline of loading instructions, in the case of a failure of the data cache memory 6 once, as shown in FIG. 7, the pipeline will be locked, and the processing of subsequent instructions will be suppressed, the section will be forwarded to the request D TR EQ input to the secondary cache control device 10. When the secondary cache control device 10 outputs the response D TA CK for the completion of the sector transfer, the sector transfer data is written into the primary data cache 6 and the general-purpose register 8 1 » In the pipeline, when the write buffer 9 is not empty when a cache error occurs, the data address DADRS stored in the write buffer 9 and the data address DADRS of the subsequent storage command are stored in the address comparator in the A stage 9 5 Make a comparison, and compare the action at (C) address to be consistent, and (D) address comparison to be inconsistent according to the comparison result. The occasion means that there is a data cache error in the A stage, and the address comparator 95 can know the data address of the last storage command in the write buffer 9 and the data address of this storage command It is the address of the same data section. That is, it means: the label address and annotation address of the data address of both parties are the same, the label address and annotation address of the data address of both parties are the same, and the stored data of both parties should be in accordance with Chinese national standards (this national standard for paper) CNS) Λ4 specification (210X297 1) n · ^ mm ^ ϋ · f one * 0¾ * vs (please read the notes on the back before filling in this page) A7 __B7 printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Instructions (32) should be stored in the same cache line of the primary data cache. Therefore, there is no need for pipeline locking, and in the phase w, the stored data is stored in the write data buffer 91 at the position indicated by the byte symbol stored this time. The value of the byte mark buffer 92 is updated with the value of the logical sum of each byte of the value written at the beginning and the value of the subsequent storage instruction. However, the address buffer 90 is not updated. Then, if there is a response DTACK from the secondary cache control device 10 to the transfer data buffer 9 3, the contents of the write data buffer 9 1 and the transfer data buffer 9 3 The byte selection circuit 9 4 synthesizes and writes it to the data cache 6 once. When the address of (D) above is inconsistent: the data address of the last storage command located in the write buffer 93 and the current stored data address are at the tag address or the marked address as Inconsistent, the stored data on both sides should be different cache lines stored in the primary data cache. Therefore, it is not necessary to load / store the response L / SA C K 'for this storage command and wait for the transfer of the previous cache error to complete. After the transfer is completed, the cache error of the data cache memory 6 is once, in the W stage, the data address of the storage command DADR S, the storage address STRDAT 'byte symbol BMRK is written to the write buffer 9 and continue to execute instructions. In the state where valid data is stored in the write buffer, if the load instruction is executed, even if there is a data cache error once, the address comparator 95 can perform the judgment operation. For example, when the judgment result is consistent, the load command refers to the loading of the data stored in the write buffer 9. This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) n _ * · I 1'-IIIIII mm ^ 1 «, T (please read the precautions on the back before filling this page) -35-A7 B7 ^ 06442 V. Description of the invention (33) At this time, although the A and W phases of the load instruction must be pipeline stalled, the necessary data will be stored in the write buffer, so there is no need to correspond In response to the load instruction, the section transfer request is sent out again. After the section of the command written in the buffer 9 is transferred, the primary data cache 6 is accessed again, the load data is read out, and the read load data is stored in The W stage is written into the register 81. In the state where valid data is stored in the write buffer, when the load command is executed and the result of the determination operation of the comparator 95 is inconsistent when the data cache error occurs once, the pipeline will be stalled. After the write data buffer 9 becomes empty, the section transfer request D TR EQ is output according to the load command. This is because the two-time cache control device 10 cannot simultaneously handle two types of sector transfer requests. When the secondary cache transfer device 10 outputs a response DT ACK corresponding to the segment transfer request, the primary data cache control device 60 writes the data forwarded by the segment to the primary data cache memory 6 and the pan Use scratchpad 8 1. The above-mentioned embodiment has the following effects: (1) As the content of the general purpose register 81 is backed up to the stack provided on the memory, it is placed on the primary data cache 6 in the continuous storage direction When the same section of the same cache line is detected by the address comparator 95, then even if the cache error occurs once the cache error occurs, the primary data cache control device 60 will also make this The stored data is continuously held in the write buffer 9, and the stored data is returned to the command processing device 8 from the stored L / SA CK while being held in the write buffer 9. The standard of this paper is applicable to China National Standard (CNS) Λ4 specification (210X297mm) (please read the notes on the back before filling in this page). · Printed by ys Central Ministry of Economic Affairs Bureau Consumer Cooperatives 36 -QR _ The Ministry of Economic Affairs, Central Standard Falcon Bureau Employee Consumer Cooperative Indica A7 B7 V. Description of Invention (34) Therefore, the instruction processing device 8 can recognize that the write access is completed if the storage instruction is executed, and can further control the execution of the next command. As a result, the waiting period of the command processing device 8 can be shortened, and even if the data is continuously stored in the same cache line in the primary data cache, it is possible to prevent the degradation of data processing performance caused by cache errors . (2) During this period, the cached segment data will be transferred from the secondary cache memory 2 or the main memory device 4 to the transfer data buffer 93. The data transferred to the transfer data buffer 9 3 and the data written to the buffer 9 1 are added to the primary data cache 6 as new input. At this time, the byte selection circuit 94 4 synthesizes the data transferred to the data buffer 9 3 according to the byte symbol BMRK and the data written into the data buffer 9 1. The synthesized data is appended to the primary data cache memory 6 as a new input containing stored data of cache errors. Therefore, it is not necessary to add: the addition of the above-mentioned cache input, and the writing of the sector data of the forwarding data buffer 93, and the selection and writing into the writing data buffer 9 1 in byte notation The data is processed separately. In this regard, the waiting period of the command processing device 8 can also be shortened. (3) For a command processing device that executes commands in a pipeline manner, the above cache control device 60 returns when the memory write access is requested according to the storage command (STRREQ = 1): the write requested The access system is in the form of a cache hit (DCMISS = 〇), and the requested write access system is a cache error (DCMI SS = 1) and no valid data is maintained in the above write data buffer Status (WBFRVLD = 〇), and, according to the requirements of the write access memory, the paper size is applicable to the Chinese National Standard Falcon (CNS) Λ4 specification (210X 297 mm) (please read the precautions on the back before filling this page ) -Installation-, ys 37-A7 ______ B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (35) is a cache error (DCM ISS = 1) and valid data is written to the data buffer (WB FRVLD = 1) and the address comparator detects a consistent (B LKMCH = 1) status of various responses to the memory access request (L / SACK), and corresponding to this memory access request Has write access, cache error (DCM ISS = 1) and is writing In the state where the material buffer holds valid data (WB F RVLD = 1) and the address comparator detects inconsistency (BLKMCH = 〇), it indicates that the pipeline is locked (KOCK = 1) to the command processing device, and then, cache The segment data of the wrong address will wait until the transfer from the upper memory device to the above transfer data buffer is completed 'and the pipeline and integration can be used to achieve the above by releasing the pipeline lock and supplying the response to the memory access (1) Control. Although the above has specifically described the inventor's invention with examples, the present invention is not limited to these examples. Of course, there can be various deformations without departing from its gist. For example, it may be: the bit address of the tag address and the annotation address is not limited to those in the above-mentioned embodiments, or the cache tag is not limited to the physical page number in the above-mentioned embodiments, but may include Reset (Of fsef) part of the information. Furthermore, the cache memory may also be a logic cache. Furthermore, the secondary data cache memory of the above embodiment may be omitted. In the above description, the utilization field of the inventor's invention is described as being applicable to a microprocessor. However, the present invention is not limited to this but can also be applied to a so-called main frame. At least the paper size of the present invention is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 trips) (please read the precautions on the back and then fill out this page) — Binding · Ordering -38-Λ7 1 B7 V. Description of the invention (36) It is also widely applicable to a system (syston) with a cache memory using a swap method. A simple explanation of the effects that can be obtained by the representative of the inventions disclosed in this patented invention is as follows: Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy ------ 1--: -¾ clothing—— (please read the precautions on the back before filling in this page) That is, the area where the cache is missed when a cache miss occurs when executing a memory access or storage command Segment data is transferred from the above-mentioned memory device and added to the cache memory as a new input. In the case of the exchange method, it is like when the contents of the general-purpose register are backed up to the stacking area provided on the memory. , When storing the same section of the same cache line continuously on the cache memory, it is detected by the address comparator, and in the case of a cache error once a cache error occurs, the cache The fetch control device can also keep this stored data in the write buffer continuously. The stored data is sent back to the command processing device in response to the stored state while remaining in the write buffer. Thus, the instruction processing device can recognize that the execution of the write access or storage instruction is completed, and can further control the execution of the next instruction. Therefore, the waiting period of the command processing device can be shortened, and even when data is continuously stored on the same cache line on the same cache memory, the degradation of data processing performance due to cache errors can be reduced to The smallest. In the exchange method, the cached section data is transferred from the upper memory device to the transfer data buffer. The selection circuit synthesizes the data transferred to the data buffer and the data written to the data buffer according to the byte mark. The synthesized data is appended to the cache memory as a new input containing cached stored data. Therefore, it is not necessary to input the above cache into this paper. The standard of the paper is applicable to the Chinese national standard (CNS> A4 specification (210X 297 mm) -39-A7 t442 B7. V. Addition of the invention description (37), and the transfer of the data buffer The writing of sector data, and the selection of byte symbols and the writing of data to the data buffer are performed separately. In this regard, the waiting period of the command processing device can also be shortened. -----:-• Install-- (Please read the precautions on the back before filling in this page) The paper standard printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 (210X 297 Mm) 40