JPH08206330A - Control device for game apparatus - Google Patents

Abstract

PURPOSE: To prevent fraudulent replacement by detecting the fraudulent replacement of peripheral devices such as a ROM at least when a power source is turned on. CONSTITUTION: When a power source is turned on or reset, a read signal is first outputted to a read signal line L1. The code data is inputted from the ROM 3 via a data bus B2 at the time 10msec after the read signal was outputted, and a CPU 1 judges whether the received code is the same as the prescribed value or not. When the CPU 1 judges that they are inconsistent with each other, the output of the port connected to the signal line L3 on the ROM 3 side is fixed to H, and the read signal to the ROM 3 is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine control device which includes a central processing unit and a plurality of peripheral devices and which controls the operation of the gaming machine.

[0002]

2. Description of the Related Art In recent years, the spread of microcomputers has been remarkable, and microcomputers are often used in game machines such as pachinko machines and game machines.

The microcomputer includes a central processing unit (hereinafter referred to as CPU) and ROMs and Rs as storage units.
An AM and an input / output interface as an input / output unit have a basic configuration. For example, in a pachinko machine equipped with a so-called digital machine that makes a prize such as a big hit with a combination of three-digit numbers, Works like.

The detection signal of the digital start winning switch is fetched from the input / output interface, and in the CPU,
If the detection signal is in the ON state, the center accessory digital is started via the input / output interface and stopped at a predetermined timing. Further, in the CPU, when the digital numbers and symbols are a big hit combination when the digital is stopped, the special winning opening is opened via the input / output interface.

The digital design of the center character is
The data of the symbols pre-stored in the ROM is taken out, and the variation of the symbols is determined based on the random number table also pre-stored in the ROM.

[0006]

By the way, in such a gaming machine such as a pachinko machine, the probability of winning a prize such as a ball is greatly changed in the short term to enhance the playability.
In the long run, it was necessary to stabilize the balance between the profits of the player and the game hall.

However, in such a conventional pachinko machine, since the probability of winning is determined by the random number table, the probability of winning can be determined by simply replacing the ROM with another random number table stored. It could be changed easily. Such fraud may be made by the manager of the amusement hall or by a clerk of the amusement hall without knowing the administrator of the amusement hall, but the discovery was difficult.

The control device for the gaming machine of the present invention has been made in view of these problems. By preventing unauthorized replacement of the peripheral device of the CPU, for example, in the case of a pachinko machine, the probability of a payout is controlled. The purpose is to prevent unauthorized modification.

[0009]

Means for Solving the Problem and Its Action / Effect To solve such a problem, a control device for a gaming machine according to the present invention is provided with a central processing unit and a plurality of peripheral devices and operates the gaming machine. In the control device of the gaming machine to control,
At least one of the peripheral devices is provided with an identification information storage unit that stores identification information unique to the peripheral device, and the identification information stored in the identification information storage unit is stored in the central processing unit as the identification information. Identification information determining means for determining whether or not the identification information stored in advance corresponds to the stored peripheral device at a predetermined timing including at least power-on, and the identification information determining means determines both The gist is to provide an access prohibition unit that prohibits access to the peripheral device that outputs the identification information when it is determined that they do not match.

In the gaming machine control device of the present invention configured as described above, after a predetermined time from the start of the operation, the peripheral device identification information output means outputs the identification information peculiar to the peripheral device, and the central part Whether the identification information receiving means of the processing device receives the output identification information, and whether the received identification information matches the identification information stored in advance corresponding to the peripheral device that outputs the identification information. Is determined by the identification information determination means, and when it is determined that the two do not match, access to the peripheral device that has output the identification information is prohibited by the access prohibition means.

Therefore, when the peripheral device is illegally replaced, the peripheral device after the replacement should not be provided with the identification information output means. Therefore, the identification information determination means makes a determination of non-coincidence. The access to the peripheral device after the replacement is prohibited by the access prohibition means.
Therefore, it is possible to prevent unauthorized replacement of the ROM or the like that is a peripheral device of the CPU, and for example, in a pachinko machine, it is possible to prevent unauthorized operation of the probability of a payout.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
It is a block diagram which shows the principal part of the control system of the pachinko machine which mounts the control apparatus of the gaming machine which is an Example.

As shown in the figure, the control device for the gaming machine of the first embodiment is a CPU (central processing unit) 1
It is mainly composed of. The CPU 1 includes a ROM (read only memory) 3 and a RAM (random acc) as peripheral devices.
It integrates and controls the ess memory 5 and the input / output interface 7 and also performs all arithmetic or logical operations applied to the data. In the case of the present embodiment, it is an 8-bit microprocessor which incorporates a program to be described later as firmware.

The ROM 3 is a read-only memory in which a control program and various data necessary for the CPU 1 to execute arithmetic processing are recorded in advance. Here, the various data is a random number table or the like for generating random numbers for determining the big hit, including the data of the symbols displayed on the digital (display device) of the center character.

The RAM 5 is a readable / writable memory in which various data necessary for the CPU 1 to execute arithmetic processing are temporarily read / written.

The input / output interface 7 is, via the waveform shaping circuit 11, the prize switch 13 of the main body of the pachinko machine,
Data is input from the digital start winning switch 14 and the like, and through the driver 15, to the hit lamp 17 of the pachinko machine body, the display device 18 which is the digital part of the center role, the solenoid 19 for opening the special winning opening, etc. Output the data.

The ROM 3 includes a delay unit 3a for delaying a predetermined time of 10 msec and a code 0001 stored in advance.
And a code generator 3b for outputting the code. When the first read signal is input after power-on or reset, the delay device 3a is operated and the code 0001 is output from the code generator 3b. Also, the input / output interface 7 includes a delay device 7a that delays by a predetermined time of 20 msec,
A code generator 7b that outputs a code 0002 stored in advance is built in. When the first read signal is input after power-on or reset, the delay device 7a is operated to output the code 0002 from the code generator 7b. Output.

CPU 1 and these peripheral devices, that is, ROM
3, the signal path between the RAM 5 and the input / output interface 7 will be described below.

An address bus B1 and a data bus B2 are provided as main signal lines between the CPU 1 and these peripheral devices.
Is connected. Furthermore, as a control bus,
A read signal line L1 is connected between the CPU 1 and these peripheral devices, and a write signal line L2 is connected between the CPU 1 and the RAM 5 and the input / output interface 7.

In addition, AND circuits 21 and 23 are provided in the middle of the respective read signal lines L1 connected to the ROM 3 and the input / output interface 7. The other input terminal of the AND circuit 21 is connected to the control signal line L3 from the CPU 1 via the knot circuit 25, and the other input terminal of the AND circuit 23 is connected to the control signal line L4 from the CPU. It is connected through the circuit 27.

Next, how data is exchanged between the CPU 1 and these peripheral devices will be described.

When writing data to the RAM 5, the CPU 1 first sets the address to be written to the address bus B1.
Output to. The RAM 5 connects only the memory cell at that address to the data bus B2. Next, the CPU 1 outputs the data from the data bus B2 and the write signal from the write signal line L2. The RAM 5 writes the data on the data bus B2 into the memory cell at the address.

On the other hand, when reading data from the RAM 5, first, the address to be read from the CPU 1 is output to the address bus B1. The RAM 5 connects only the memory cell at the address to the data bus B2 and outputs the data from the memory cell at the address to the data bus B2. Then C
The PU1 outputs a read signal from the read signal line L1 and reads the data on the data bus.

When reading data from the ROM 3,
The same data exchange as in reading data from the RAM 5 is performed. Moreover, in this case, the CPU
It is possible to prevent the read signal output from the ROM 1 from reaching the ROM 3 and disable the reading of data from the ROM 3. When the signal output from the CPU 1 to the signal line L3 is at a low level (hereinafter, simply referred to as [L]), the signal output from the knot circuit 25 is at a high level (hereinafter, simply referred to as [H]), The read signal reaches the ROM 3 via the AND circuit 21, whereas the CPU 1
This is because, when the signal output from the to the signal line L3 becomes [H], the signal output from the knot circuit 25 becomes [L], and the read signal is cut off by the AND circuit 21.

Also when reading data from the input / output interface 7, as in the case of reading data from the ROM 3, by setting the signal output to the signal line L4 to [H], the data reading can be disabled. .

In this way, the CPU 1 executes the following processes (1) to (4) while exchanging data with the peripheral device.

(1) A process of receiving the detection signal of the winning switch 13 and discharging the prize ball while lighting the hit lamp 17, (2) Receiving the detection signal of the digital start winning switch 14, The process of starting the digital and then stopping it, (3) when the digital is stopped, it is determined whether or not the digital design matches the combination of the big hits, and when it is determined that the two match, the solenoid 1
Processing to open the special winning opening by driving 9, (4) ROM3
Fraud prevention processing that prohibits execution when peripheral devices such as are illegally replaced.

In the process (2), the random number table stored in the ROM 3 is read, and the symbols based on the random number table are read from the symbol data also stored in the ROM 3 and displayed on the display device 18 in order. Done.

The processes (1) to (3) above are executed by the control program read from the ROM 3, and
The process (4) is executed by a control program built in the CPU 1.

Next, regarding the fraud prevention processing of (4) above,
A detailed description will be given along the flowchart of FIG.

This fraud prevention process is first executed after power is turned on or after reset. When the processing is started, first, initialization processing for setting initial values to various variables such as a table is executed (step 100). Then, a read signal is output to the ROM 3 and the input / output interface 7 via the read signal line L1 (step 110).

As a result, in the ROM 3, the delay device 3a
And 10 msec have passed, the code generator 3b outputs the code 0001. Also, in the input / output interface 7, the delay device 7a operates, and after 20 msec has elapsed,
The code 0002 is output from the code generator 7b.

After executing step 110, the CPU 1 executes R
Whether or not data is output from the OM3 is determined (step 120), and if it is determined that there is data output, the ROM
The code CROM which is the data is fetched from 3 (step 130).

Then, it is judged whether or not data is output from the input / output interface 7 (step 140),
When it is determined that the data is output, the code CIO which is the data is fetched from the input / output interface 7 (step 150).

Subsequently, it is determined whether the code CROM fetched in step 130 is equal to the code 0001 (step 160). If it is determined that they are equal, the process proceeds to the next step, while if it is determined that they are not equal, the output of the port to which the signal line L3 on the ROM side is connected is fixed to [H]. (Step 170).

Then, it is determined whether the code CIO fetched in step 150 is equal to the code 0002 (step 180). If it is determined that they are equal, the process proceeds to the next step. On the other hand, if it is determined that they are not equal, the output of the port to which the signal line L4 on the input / output interface side is connected is [H]. (Step 190). After that, the process goes to "EXIT" and the fraud prevention process is terminated.

CPU with fraud prevention processing having such a configuration
The operation of No. 1 will be described based on the timing chart of FIG.

After power is turned on or after reset, a read signal is first output to the read signal line L1. 10 msec after the read signal is output, the data bus B is read from the ROM 3
If the code data is input via 2 and the code is not a predetermined 0001, the ROM side signal line L
The output of the port to which 3 is connected is fixed at [H]. As a result, the read signal is blocked by the AND circuit 21, and R
The reading of data from the OM3 becomes impossible thereafter. Also, 20 msec after the read signal is output, the code data is input from the input / output interface 7 via the data bus B2, and the code is set to a predetermined value 00.
If not 02, the signal line L on the input / output interface side
The output of the port to which 4 is connected is fixed at [H]. As a result, the read signal is blocked by the AND circuit 23, and reading of data from the input / output interface 7 becomes impossible thereafter.

Therefore, when the ROM 3 is illegally replaced, the ROM 3 after the replacement should not be provided with the delay unit 3a and the code generator 3b. , R
The signal [H] is output to the signal line L3 on the OM side, and RO
The reading of data from M3 becomes impossible thereafter.
As a result, it is possible to prevent unauthorized replacement of the ROM 3, and it is possible to prevent unauthorized operation of the probability of winning. Similarly, the input / output interface 7 can be prevented from being illegally replaced.

The second embodiment of the present invention will be described below. First
In the embodiment, the ROM 3 and the input / output interface 7
The read signal input to the input circuit is input via the AND circuits 21 and 23. Instead of this, in the second embodiment, the read signal is directly input to the ROM 3 and the input / output interface 7 as shown in FIG. Is to be entered.

Further, as shown in FIG. 5, in the fraud prevention processing executed by the CPU 1, instead of step 170 of the first embodiment, the first cell T of the preset table is replaced.
Substitute the value 1 into BL (1) (step 200), and
Instead of the step 190 of the first embodiment, the value 1 is assigned to the second cell TBL (2) of the table (step 210).

Then, in another process executed by the CPU 1,
It is determined whether or not the value 1 is assigned to each cell of the table, and when the value 1 is assigned to TBL (1), the data is read from the ROM 3 in various processes executed by the CPU 1 thereafter. Further, when the value 1 is assigned to TBL (2), reading of data from the input / output interface 7 is prohibited in various processes executed by the CPU 1 thereafter.

In the control unit for the gaming machine of the second embodiment constructed as described above, the unauthorized replacement of the ROM 3 and the input / output interface 7 is prevented as in the first embodiment.
It is possible to prevent fraud such as manipulating the probability of winning. Moreover, in the case of the present embodiment, since the prohibition of reading the data from the ROM 3 and the input / output interface 7 is realized by the software executed by the CPU 1, the configuration is simple.

In the first and second embodiments, the code of 0001 is used as the identification information of the ROM 3 and the code of 0002 is used as the identification information of the input / output interface 7, but this code is arbitrary. The set value is sufficient, and fraud prevention can be achieved more reliably.

Further, part or all of the control program stored in the peripheral device is pre-encoded, and the encoded information corresponding to the execution part of the control program is used as identification information at all times, or predetermined or as required. Output from the peripheral device to the CPU at the timing.
When it is determined that the encoded information is not valid, the access to the peripheral device may be prohibited.
With such a configuration, it is possible to prevent unauthorized modification of the control program of the peripheral device.

Further, in the first and second embodiments, the access prohibiting means M1c is configured to prohibit reading of data from the ROM and the input / output interface. However, instead of this, a CPU The operation itself may be stopped to indirectly stop the operations of those peripheral devices.

Although some embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various embodiments are possible without departing from the gist of the present invention. Of course, it can be implemented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a control system of a pachinko machine equipped with a game machine control device according to a first embodiment.

FIG. 2 is a flowchart showing fraud prevention processing executed by a CPU.

FIG. 3 is a timing chart of an operation by the fraud prevention processing.

FIG. 4 is a block diagram showing a part of a control device for a gaming machine according to a second embodiment.

FIG. 5 is a flowchart showing fraud prevention processing executed by the CPU of the second embodiment.

[Explanation of symbols]

 1 ... CPU 3 ... ROM 3a ... Delay device 3b ... Code generator 5 ... RAM 7 ... Input / output interface 7a ... Delay device 7b ... Code generator 21, 23 ... AND circuit 25, 27 ... Not circuit B1 ... Address bus B2 ... Data bus L1 ... Read signal line

Claims (1)

[Claims] 1. A game device control apparatus comprising a central processing unit and a plurality of peripheral devices for controlling the operation of a game device, wherein at least one of the peripheral devices stores identification information unique to the peripheral device. Identification information storage means is provided, and whether the identification information stored in the identification information storage means in the central processing unit matches the identification information stored in advance corresponding to the peripheral device storing the identification information. Identification information determining means for determining whether or not at a predetermined timing including at least power-on, and to the peripheral device that has output the identification information when the identification information determining means determines that the two do not match. A control device for a gaming machine, which is provided with an access prohibition means for prohibiting access of the game machine.