JPH08186764A - Integral signal detection circuit and its driving method - Google Patents

Abstract

PURPOSE: To prevent the mixture of noises by providing the 1st and 2nd amplifiers or buffers, the 1st and 2nd integrators, the 1st and 2nd sample holding circuits, and a selection circuit which selects one of outputs of both sample holding circuits. CONSTITUTION: A first-stage amplifier circuit 2 is connected to the output terminal of an object 1 to be measured, and the output of the circuit 2 is divided into two pieces and inputted to the buffers 3a and 3b. The signals of both buffers are inputted to the integrators 4a and 4b and integrated there. The integrators 4a and 4b are connected in parallel to the reset switches 43a and 43b, the integral capacitors 42a and 42b, and the operational amplifiers 41a and 41b respectively. The integration results of integrators 4a and 4b are temporarily held by the sample holding circuits 5a and 5b. The outputs of both circuits 5a and 5b are selected by an output selection switch 6, which returns the result to the output of a single series. The buffers 3a and 3b prevent the noises due to the resets of integrators 4a and 4b from mixing into the integrators 4a and 4b of the other side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge integration type signal detection circuit used for detecting a charge signal of a solid-state image pickup device and a method for driving the signal detection circuit.

[0002]

2. Description of the Related Art In order to operate a solid-state image sensor at high speed,
In addition to the operating speed of the element itself, it is necessary to increase the operating speed of the detection circuit. Commonly used to detect charge signals is Kleinfelder et al. (Stuart AK
leinfelder et al. ) By IE Transactions on Nuclear Sciences (IEEE Transactions)
on Nuclear Science Vol. Three
5, No. 1 February 1988 pp. 17
1-175), an integrator 4 including an operational amplifier 41, an integrating capacitor 42, and a reset switch 43.
It is a circuit using one. This circuit block diagram is shown in FIG. However, in the detection circuit using one integrator 4 like this circuit, it is necessary to reset the integrator within the pixel selection period as seen from the timing chart of FIG. 4, and high-speed operation is difficult. It was

To speed up the detection circuit using the integrator 4, there is a method proposed in Japanese Patent Laid-Open No. 2-114439. This is done by the integrator 4 as shown in FIG.
a and 4b are arranged in parallel, the DUT 1 is connected to either of the two integrators 4a and 4b by the input selection switch 7, and the connected integrator 4a or 4b integrates the signal. While the other integrator 4a or 4b
Is to reset. This makes it possible to prevent the operating speed from decreasing due to the reset time.

[0004]

However, in the detection circuit shown in FIG. 5, when the input selection switch 7 is inserted between the device under test 1 and the integrators 4a and 4b, the input selection switch 7 feeds. Generation of noise due to through becomes a problem. For example, the output charge amount of the solid-state image pickup device is 1 pC or less, and when a MOSFET is used for the switch, the magnitude of noise generated from the switch is several pC or more. Therefore, in the detection circuit of this configuration, by selecting the integrators 4a and 4b by the switch, switching noises of several times or more of the signal charge amount are also detected, which causes a decrease in S / N. there were. Further, in order for the integrator to operate normally even if switching noise is mixed, it is necessary to set the dynamic range of the integrator to a large value.
Therefore, there is also a drawback that an operational amplifier that operates with high accuracy and high speed is required.

An object of the present invention is to provide a charge integration type signal detection circuit for detecting a signal of a solid-state image pickup device or the like.

[0006]

An integral type charge signal detection circuit according to the present invention comprises a first stage amplifier connected to an object to be measured,
First and second amplifiers or buffers that are connected to the first-stage amplifier and receive the outputs thereof at the same time, and a capacitor, an operational amplifier, and a switch that is connected in parallel with the capacitor. First and second integrators, first and second sample and hold circuits connected to the respective integrators and temporarily holding respective signals, and the first and second sample and hold circuits It is characterized in that it comprises a selection circuit which selects the output of the above and outputs it as one output.

Further, the integral type charge signal detection circuit of the present invention simultaneously transmits the signal from the DUT to the first and second amplifiers or buffers via the first stage amplification circuit,
Reset the second integrator while the integrator is integrating the signal, and operate the first sample and hold circuit to hold the signal in the state where the first integrator integrates the signal. , The output of the first sample and hold circuit and the output of the second sample and hold circuit are alternately selected and operated by operating the selection circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing an integral type charge signal detection circuit of the present invention. First, the first-stage amplifier circuit 2 is connected to the output terminal of the device under test 1. The output is divided into two, which are input to the buffer 3a and the buffer 3b, respectively, and the signals thereof are integrator 4a and integrator 4b, respectively.
Is input to and integrated. The integrator 4a and the integrator 4b are reset switches 43a and 43b, integration capacitors 42a and 42b, and operational amplifiers 41a and 41b connected in parallel, respectively. The results integrated by the integrators 4a and 4b are temporarily held in the sample hold circuits 5a and 5b, respectively. The circuit configuration is such that the output is selected by an output selection switch and is returned to a series of outputs. Here, the buffers 3a and 3b prevent noise due to resetting of the integrators 4a and 4b from being mixed into the other integrators 4a and 4b. Similar effects can be obtained by using an amplifier instead of the buffer. Also, the integrators 4a, 4
Since there is no switching element between b and the device under test 1, noise is not mixed.

FIG. 2 is a timing chart used in the signal detection circuit shown in FIG. FIG. 2 shows a method of detecting a device such as a solid-state image sensor in which signals are sequentially output at a certain clock timing. The signal Vin to be detected is a waveform in which the change of the signal ends with a time constant of a value determined for each object to be measured, and an output is obtained by integrating this until the output change ends. First, the signal Vin is amplified by the first-stage amplifier circuit, input to the buffers 3a and 3b, and the output thereof is input to the integrators 4a and 4b.

For example, the operation when detecting the signal of the pixel 2n will be described.

Since SW1 (reset switch 43a) is in a disconnected state, the integrator 4a integrates the pixel signal. After the change of the signal of the pixel 2n is completed, the output of the integrator is held in the sample hold circuit 1 (5a) by switching the SW3 (sampling switch 52a) to the disconnected state.

Since SW2 (reset switch 43b) is in the conductive state, the signal of the pixel 2n is not integrated in the integrator 4b, and the circuit is reset by discharging the charge of the integrating capacitor 42b. After the change of the signal of the pixel 2n is finished, SW2 (reset switch 43b) is changed to the disconnection state, and the circuit maintains the initial state. The sample hold circuit 5b holds a value obtained by integrating the signal of the pixel 2n-1.

SW5 (output selection switch 6) is connected to B and selects the output of the sample hold circuit 5b.

Next, the operation of detecting the signal of the pixel 2n and the subsequent detection of the signal of the pixel 2n + 1 will be described.

In the integrator 4a, SW1 (reset switch 43a) is reset when it is conductive,
After the change of the signal of the pixel 2n + 1 is completed, the switch SW1 is disconnected so that the initial state is maintained. A value obtained by integrating the signal of the pixel 2n is output to the sample hold circuit 5a.

In the integrator 4b, since SW2 (reset switch 43b) is in a disconnection state, the integration of the signal is performed, and after the change of the signal of the pixel 2n + 1 is completed, SW4
By disconnecting the (sampling switch 52b), the output of the integrator 4b is held in the sample hold circuit 5b.

SW5 (output selection switch 6) is connected to A and selects the output of the sample hold circuit 5a.

That is, by repeating such an operation, the output of this circuit is such that the pixel signal and the signal delayed by one pixel are sequentially integrated and output, and apparently one conventional integrator is used. A signal similar to that of the detection circuit is obtained.
For example, when the detection circuit of the MOS image sensor is made of individual parts, the configuration using one integrator can shorten the reset time of about 100 nsec and realize a speedup of 1.5 times or more. . In addition, 2 integrator
It was confirmed that the decrease in S / N due to the use of one of these did not appear.

[0020]

As described above, the construction in which no switching element is arranged between the two integrators arranged in parallel and the object to be measured is realized, and the two integrators are dedicated to each other. By connecting to the buffer circuit, it is possible to prevent noise from being mixed by the switch for selecting the integrator, which was inevitably generated by the former method by the former method, and by the latter, noise when the integrator is reset It became possible to prevent the mixture of. Due to this effect, high S / N and high-speed operation can be realized at the same time, and it becomes possible to perform high-speed signal detection with an output charge amount of 1 pC or less as in a solid-state image sensor.

As described above, according to the present invention, it is possible to use a low slew rate operational amplifier as the integrator, a slow operation speed reset switch element, or a small element size, which is an individual element. A cost effect can be obtained also when manufacturing and integrating.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of an integral type charge signal detection circuit of the present invention.

FIG. 2 is a diagram showing a timing chart used in the signal detection circuit of the present invention.

FIG. 3 is a diagram showing a detection circuit of a conventional solid-state image sensor.

FIG. 4 is a diagram showing a timing chart used in the detection circuit shown in FIG.

FIG. 5 is a diagram showing a signal detection circuit using two conventional integrators.

[Explanation of symbols]

 1 DUT 2 First stage amplifier circuit 3a, 3b Buffer 4, 4a, 4b Integrator 5a, 5b Sample hold circuit 41, 41a, 41b Operational amplifier 42, 42a, 42b Integrating capacitor 43, 43a, 43b Reset switch 51a, 51b Sample Capacitance 52a, 52b Sampling switch 6 Output selection switch 7 Input selection switch Vin Output waveform from DUT SW1 Switch 43a control signal SW3 Switch 52a control signal V1 Integrator 4a output signal SW2 Switch 42b control signal SW4 Control signal V2 of switch 52b Output waveform of integrator 4b TSW5 Control signal of switch 6 V3 output waveform

Claims (2)

[Claims] 1. A first-stage amplifier connected to a device under test and a first-stage amplifier connected to the first-stage amplifier and receiving the outputs thereof at the same time.
And second amplifiers or buffers, first and second integrators each of which is connected to each of the amplifiers or buffers and includes a capacitor, an operational amplifier, and a switch connected in parallel with the capacitor, and each of the first and second integrators. First and second sample and hold circuits connected to the integrator and temporarily holding respective signals, and a selection circuit for selecting the outputs of the first and second sample and hold circuits to form one output An integral type signal detection circuit comprising: 2. A signal from a device under test is simultaneously transmitted to a first and a second amplifier or a buffer via a first-stage amplifier circuit, and a second integration is performed during a period in which the first integrator integrates the signal. The first sample-hold circuit and the second sample-hold circuit to operate the first sample-hold circuit so as to hold the signal in a state in which the signal is integrated by the first integrator. 2. The method for driving an integral type signal detection circuit according to claim 1, wherein the selection circuit is operated so as to alternately select and output the output of FIG.