WO2018117322A1

WO2018117322A1 - Switched-capacitor integrator using single gain buffer

Info

Publication number: WO2018117322A1
Application number: PCT/KR2017/000128
Authority: WO
Inventors: 안길초; 곽용식
Original assignee: 서강대학교 산학협력단
Priority date: 2016-12-22
Filing date: 2017-01-05
Publication date: 2018-06-28
Also published as: KR101956309B1; KR20180073290A

Abstract

The present invention relates to an integrator using a single gain buffer and including: a positive differential switched-capacitor which adds a positive input signal to a value stored in a previous phase, and cumulates and stores the added values; a negative differential switched-capacitor which adds a negative input signal to a value stored in a previous phase, and cumulates and stores the added values; a positive single gain buffer which delivers, to an integration capacitor, a value obtained by adding positive input signals; and a negative single gain buffer which delivers, to the integration capacitor, a value obtained by adding negative input signals.

Description

Switched-Capacitor Integrator with Single Gain Buffer

The present invention relates to an integrator using a single gain buffer, and more particularly to a single gain buffer based switched-capacitor integrator capable of low power and small area implementation at high speeds.

Integrator circuits are critical blocks used in the implementation of application circuits such as analog computers, analog-to-digital converters, and wave shaping. It can be divided into integrator and discrete-time integrator.

The DT integrator uses a switched-capacitor circuit technique to obtain relatively accurate coefficients of the transfer function, making it easy to design, especially in delta-sigma analog-to-digital converters, which have less impact on clock jitter than CT integrators. Has the advantage of receiving.

However, the application of the DT integrator is much limited in applications requiring a wide bandwidth such as a mobile communication system. Depending on the application system used, the DT integrator's operating clock rate must be several hundred MHz or more. To meet this operating rate with a DT switched-capacitor integrator based on a traditional closed-loop architecture, the bandwidth design requirements of the amplifier are required. Due to this very wide power consumption, there is a problem that the area occupied by the circuit increases.

The problem to be solved by the present invention is to provide a technical means that can obtain a wider bandwidth than the switched-capacitor integrator consisting of a conventional closed loop.

Instead of the conventional complex amplifier, the integrator is implemented using a relatively simple source-follower as a single gain buffer to realize small area and low power in the DT integrator of high-speed operation.

In addition, the integrator's structure is implemented in an open-loop using a single gain buffer, eliminating the overhead incurred by feedback in the traditional closed-loop integrator, compared to the integrator of the conventional capacitor-feedback structure. Implement faster high speed operation.

According to an embodiment of the present invention, by implementing the structure of the integrator in an open-loop using a single gain buffer, because the overhead caused by feedback in the existing closed loop integrator is eliminated, the existing capacitor Faster high-speed operation is possible compared to the integrator with feedback structure.

In addition, according to an embodiment of the present invention, by implementing an integrator using a source-follower circuit having a relatively simple structure as a single gain buffer instead of a complex amplifier, the total area of the DT integrator can be reduced, and power consumption is reduced. It can also be reduced.

1 is a detailed circuit diagram and timing diagram of an integrator using a single gain buffer according to an embodiment of the present invention.

2A through 2C are detailed circuit diagrams and timing diagrams of respective phases of an integrator according to an embodiment of the present invention.

3 illustrates a single gain buffer of a source-follower structure in one embodiment of the invention.

4 is a diagram illustrating a unit-gain feedback differential amplifier.

An integrator using a single gain buffer according to an embodiment of the present invention includes a first positive integrating capacitor and a first negative integrating capacitor which add each input signal having a different polarity to a value stored in a previous phase, and the first positive integrating unit. A signal received from the second positive integrating capacitor and the second negative integrating capacitor and the first positive integrating capacitor and the first negative integrating capacitor respectively accumulating and storing signal values added by the capacitor and the first negative integrating capacitor, respectively; And a positive single gain buffer and a negative single gain buffer to pass to the two positive integral capacitors and the second negative integral capacitors.

Before describing the embodiments of the present invention, the problems of the existing closed loop structure switched-capacitor integrator in the implementation of the DT integrator operating at high speed are examined, and then the embodiments of the present invention are solved to solve these problems. An overview of the technical measures adopted.

The application of the conventional DT integrator has been much limited in applications requiring a wide signal bandwidth of several tens of MHz or more, such as communication systems. In order to meet this operating speed with the existing closed-loop DT integrator structure, the bandwidth design requirements of the integrator internal amplifier are greatly increased, which increases the power consumed and occupied by the integrator circuit.

Accordingly, embodiments of the present invention propose a technical means that can operate at a faster clock speed than an integrator composed of a conventional closed loop by implementing the structure of the integrator in an open-loop using a single gain buffer. do.

In addition, embodiments of the present invention propose a technical means to reduce the area and power consumption of the integrator by implementing the integrator using a simpler source-follower circuit as a single gain buffer instead of a complex amplifier. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in the following description and the accompanying drawings, detailed descriptions of well-known functions or configurations that may obscure the subject matter of the present invention will be omitted. In addition, it should be noted that like elements are denoted by the same reference numerals as much as possible throughout the drawings.

Referring to FIG. 1, the positive differential switched-capacitor includes a first positive integrating capacitor C _1P and a second positive integrating capacitor C _2P and a plurality of switches.

The plurality of switches serve to switch between alternating an execution of adding the positive input signal and an execution of storing the added input signal values according to a phase change.

During phase Ø _2A , the second positive integrating capacitor C _2P accumulates and stores the input signal values added by the first positive integrating capacitor C _1P . In this case, the positive single gain buffer BF _P serves to transfer the input signal values added by the first positive integration capacitor C _1P to the second positive integration capacitor C _2P .

The negative differential switched-capacitor comprises a first negative integrating capacitor C _1N and a second negative integrating capacitor C _2N and a plurality of switches.

The plurality of switches serve to switch between performing the addition of the negative input signal and the execution of storing the added input signal values in accordance with the phase change.

During phase Ø _2A , the second negative integrating capacitor C _2N accumulates and stores the input signal values added by the first negative integrating capacitor C _1N . Similar to the positive single gain buffer BF _P , the negative single gain buffer BF _N serves to deliver the input signal values added by the first negative integration capacitor C _1N to the second negative integration capacitor C _2N .

Hereinafter, an operation of an integrator using a single gain buffer according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2C.

First, it is assumed that the first positive integration capacitor C _1P , the first negative integration capacitor C _1N , the second positive integration capacitor C _2P and the second negative integration capacitor C _2N have the same size of the capacitor.

Referring to FIG. 2A, the charges Q _1P (n) and Q _1N (n) stored in the first positive integration capacitor and the first negative integration capacitor during phase Ø _1A are calculated by Equation 1.

To this end, the plurality of switches are configured from the positive signal input node to the first positive integrating capacitor C _1P. And connect an input node of the positive single gain buffer BF _P , and connect an input node of the negative signal input node to the first negative integration capacitor C _1N and the negative single gain buffer BF _N.

Next, referring to FIG. 2B, the input signals V _INP (n + 1/2) and V _INN (n + 1/2) during the phase Ø _2A are defined by the first positive integrating capacitor C _1P and the first negative integrating capacitor C _1N. Each is connected to and added to the value previously stored when the phase Ø _1A . In this case, the added value is stored in the second positive integral capacitor C _2P and the second negative integral capacitor C _2N through the positive single gain buffer BF _P and the negative single gain buffer BF _N , and the charge stored in each capacitor is represented by Equation 2 below. Is calculated.

To this end, a plurality of switches inside the positive switched-capacitor block is connected from the positive signal input node to the first positive integrating capacitor C _1P. And connects the input node of the positive unity gain buffer BF _P and connecting the positive unity gain buffer BF _P output node to the second negative integral capacitor C _2N. In addition, the plurality of switches inside the negative switched-capacitor block include the negative signal input node to the first negative integrating capacitor C _1N. And connects the negative unity gain buffer BF _N of input nodes, connected to the output node of the negative unity gain buffer BF _N to the second positive integral capacitor C _2P.

Next, referring to FIG. 2C, input signals V _INP (n + 1) and V _INN (n + 1) of the integrator during phase Ø _1B are connected through a second positive integration capacitor C _2P and a second negative integration capacitor C _2N . Delivered. At this time, the amount of charge stored in the second positive integral capacitor C _2P and the second negative integral capacitor C _2N is calculated by Equation 3 below.

To this end, a plurality of switches inside the positive switched-capacitor block allow the input node of the positive positive input capacitor C _2P and the positive single gain buffer BF _P to be connected from the positive signal input node. In addition, a plurality of switches inside the negative switched-capacitor block allow the input node of the second negative integrating capacitor C _2N and the negative single gain buffer BF _N to be connected from the negative signal input node.

According to the charge conservation law, the total transfer function of the integrator is calculated by Equation 4.

In this case, when the transfer function is converted into a z domain (z-domain), it is calculated by Equation 5.

In this structure of the integrator using a single gain buffer according to an embodiment of the present invention, two differential switch-capacitor networks each add a signal and alternately store and receive the added value through a single gain buffer. By doing so, we can obtain the transfer function of the integrator.

The open-loop integrator structure using a single gain buffer eliminates the overhead caused by feedback, resulting in wider bandwidth than conventional capacitor-feedback integrators, thereby reducing power consumption. It has the advantage of being reduced.

3 is a circuit diagram of a single gain buffer using a source-follower according to an embodiment of the present invention. Referring to FIG. 3, a single gain buffer according to an embodiment of the present invention is a PMOS device for bias current. It can be composed of M _BS and PMOS source-follower device M _SF . The PMOS source-follower device M _SF can be implemented by connecting the body and source nodes to minimize nonlinearity and gain error due to the body-effect.

4 is a circuit diagram of a unit-gain feedback differential amplifier according to an embodiment of the present invention. As shown in FIG. 4, a single gain buffer according to an embodiment of the present invention may be implemented using single-gain negative feedback to the differential amplifier A. FIG.

The present invention has been described above with reference to various embodiments thereof. Those skilled in the art will understand that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

In order to use the DT switched-capacitor integrator based on the closed loop structure of the existing technology in applications requiring a wide bandwidth such as a mobile communication system, the bandwidth design requirements of the amplifier are very wide to satisfy the operation speed, thereby increasing power consumption. In other words, the area occupied by the circuit is increased, and there is a tendency that the marketability and businessability are inferior, whereas the circuit proposed by the embodiments of the present invention implements an integrator structure in an open loop using a single gain buffer. Eliminating the overhead caused by feedback in traditional closed loop integrators allows for faster, faster operation compared to traditional capacitor-feedback integrators, improving productivity.

In addition, by implementing the integrator using a simpler source-follower circuit as a single gain buffer instead of the conventional complex amplifier, the total area of the DT integrator can be reduced and power consumption can be reduced. .

Claims

A positive differential switched-capacitor for adding a positive input signal to a value stored in a previous phase and accumulating and storing the added values;

A negative differential switched-capacitor for adding a negative input signal to a value stored in a previous phase and accumulating and storing the further values;

A positive single gain buffer which transfers the added values of the positive input signals to an integral capacitor; And

And a negative single gain buffer configured to transfer a value obtained by adding the negative input signals to an integral capacitor.
The method of claim 1,

The positive differential switched capacitor,

A first positive integrating capacitor that adds the positive input signal to a value stored in a previous phase;

A second positive integrating capacitor which accumulates and stores the signal values added by the integrating capacitor from a single gain buffer; And

And a plurality of switches for alternately switching the execution of adding the positive input signal and the execution of accumulating and storing the added input signal values in accordance with a phase change.
The method of claim 2,

The negative differential switched capacitor,

A first negative integrating capacitor that adds the negative input signal to a value stored in a previous phase;

A second negative integrating capacitor configured to receive and store signal values added by the integrating capacitor from the single gain buffer; And

And a plurality of switches for alternately switching between adding the negative input signal and changing the accumulatively storing the added input signal values according to a phase change.
The method of claim 3, wherein

The first to the positive integral capacitor, a first negative integral capacitor, the second positive integrating capacitors and the second negative-integration capacitor is the case where the capacitors are the same, the phase Ø 1A while, the first positive integration capacitor and the first negative integral capacitor The stored charges Q 1P (n) and Q 1N (n)

Integrator using a single gain buffer, calculated as.
The method of claim 4, wherein

The input signal of the integrator during phase Ø 2A is coupled to the first positive integrating capacitor and the first negative integrating capacitor, respectively, and is added to the value previously stored in the phase Ø 1A , which is added to the positive single gain buffer and The negative single gain buffer is stored in the second positive integrating capacitor and the second negative integrating capacitor, wherein the charge stored in each capacitor is stored.

Integrator using a single gain buffer, calculated as.
The method of claim 5, wherein

The input signal of the integrator during phase Ø 1B is transmitted through the second positive integrating capacitor and the second negative integrating capacitor, and the amount of charge stored in each integrating capacitor is

Integrator using a single gain buffer, calculated as.
The method of claim 6,

According to the charge conservation law, the output of the integrator

If the transfer function is converted to a z domain (z-domain),

Integrator using a single gain buffer, calculated as.
The method of claim 1,

The positive single gain buffer and negative single gain buffer,

Integrator with a single gain buffer, consisting of either source-follower or single-gain feedback differential amplifiers.