KR20160028932A - Semiconductor device and semiconductor system - Google Patents

Abstract

Provided are a semiconductor device and a semiconductor system, which can increase immunity against noises through tertiary correlated double sampling (CDS). The semiconductor device comprises: an amplifier that receives a driving signal and an external input, resets for each predetermined period of the driving signal, and performs first sampling, through reset, the noise generated by the external input, wherein the first sampled noise includes a noise difference between two consecutive reset points; and a sampler that alternately performs second sampling and third sampling on the first sampled noise, and performs fourth sampling on the second and third sampled noises. The first sampled noise includes first to third noise differences. The second sampled noise is a difference between first and second noises. The third sampled noise is a difference between the second and third noises, and the fourth sampled noise is a difference between the second and third sampled noises.

Description

[0001] DESCRIPTION [0002] Semiconductor device and semiconductor system [

The present invention relates to a semiconductor device and a semiconductor system.

In a capacitive touch controller, a read-out circuit is a main block that detects that the capacitance of a connected panel (e.g., a touch panel) is changed by an external human hand or a conductor. Such a readout circuit may be influenced by noise or the like of the external environment. Thus, increasing immunity to noise is a key factor in sensing changes in capacitance.

A problem to be solved by the present invention is to provide a semiconductor device capable of enhancing immunity to noise through third CDS (Correlated Double Sampling).

Another problem to be solved by the present invention is to provide a semiconductor system capable of enhancing immunity to noise through third CDS (Correlated Double Sampling).

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a noise reduction circuit for receiving a noise and a driving signal provided from an external input from a panel, resetting the noise signal at every predetermined period of a driving signal, 1 sampling, wherein the first sampled noise comprises an amplification part comprising a noise difference between two consecutive reset points; And a sampling unit for alternately sampling second and third sampled noises and fourth sampling second and third sampled noises, wherein the first sampled noise includes first to third noise differences The second sampled noise is the difference between the first and second noise differences, the third sampled noise is the difference between the second and third noise differences, and the fourth sampled noise is the difference between the second and third sampling Is the difference between the noise produced.

The amplifier includes a first operational amplifier, a first resistor connected between the input and output terminals of the first operational amplifier, a first capacitor connected in parallel with the first resistor, and a first reset switch connected in parallel with the first capacitor can do.

The noise provided through the external input may be high pass filtered through the first resistor and the first capacitor.

The specific period of the driving signal may be a half period of the driving signal.

The panel may include a touch screen panel, and the external input may include a touch input.

The amplification unit may include a charge amplifier.

And an offset removing unit for receiving a driving signal from the panel to remove an offset of the driving signal.

The amplification unit may receive the external input from the offset removal unit, the noise provided through the external input, and the driving signal from which the offset is removed.

The sampling unit may include a first sub-sampling unit for performing a second sampling, a second sub-sampling unit for performing a third sampling, and a third sub-sampling unit for performing a fourth sampling.

The first and second sub-sampling units may be located in parallel between the amplification unit and the third sub-sampling unit.

The first sub-sampling unit includes a second capacitor connected to the amplifying unit, a first switch connected to the second capacitor and receiving a common mode voltage, and a second switch connected between the second capacitor and the third sub- A second switch, a first integrator connected between the second switch and the third sub-sampling unit, and a second reset switch connected in parallel with the first integrator.

The second sub-sampling unit includes a third capacitor connected to the amplifying unit, a third switch connected to the third capacitor and receiving a common mode voltage, and a third switch connected between the third capacitor and the third sub- A second integrator connected between the fourth switch and the third subsampling unit, and a third reset switch connected in parallel with the second integrator.

The first and second integrators may include second and third operational amplifiers, respectively, and the second and third operational amplifiers may be provided with a common mode voltage.

The third sub-sampling unit may perform the subtraction operation by receiving outputs of the first and second integrators.

The first switch and the fourth switch may be turned on or off at the same time.

The second switch and the third switch may be turned on or off at the same time.

The amplifying unit includes a first operational amplifier receiving a common mode voltage. The sampling unit includes a first sub-sampling unit for performing a second sampling, a second sub-sampling unit for performing a third sampling, Sampling unit includes a second capacitor connected to the amplifying unit, a second switch connected between the second capacitor and the third sub-sampling unit, and a second switch connected between the second switch and the third sub-sampling unit, And a second integrator coupled to the second integrator.

When the driving signal is in the first state and the second switch is turned on and the amplification unit is reset, the output voltage of the amplification unit is reduced by the first voltage variation amount, and the output voltage of the first integrator may be increased by the first voltage variation amount.

When the drive signal changes to a second state different from the first state, the output voltage of the amplification unit further decreases by the first voltage change amount, and the output voltage of the first integrator may further increase by the first voltage change amount.

The second sub-sampling unit operates in the same manner as the first sub-sampling unit, the polarity of the output voltage variation amount of the second subsampling unit is opposite to the polarity of the output voltage variation amount of the first subsampling unit, And the output voltage variation of each of the third sub-sampling units.

The first voltage variation amount may be determined based on the driving signal.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an offset canceling unit that receives a noise and a driving signal provided through an external input from a panel and removes an offset of a driving signal; A correlated double sampling unit that reduces noise through sampling; And a sample and hold amplifier for performing buffering and low pass filtering by receiving an output of the correlated double sampling unit, wherein the correlated double sampling unit comprises: a first sampling circuit for sampling the noise supplied through the external input through a reset, a second sampling for the first sampled noise and a third sampling for the third sampling noise, and a second and third sampled noise to the sample and hold amplifier, , The first sampled noise is the noise difference between two consecutive reset points, the first sampled noise includes the first through third noise differences, and the second sampled noise is between the first and second noise differences And the third sampled noise is the difference between the second and third noise differences.

The sample and hold amplifier may buffer and low pass filter the second and third sampled noise.

And an analog-to-digital converter for fourth sampling the buffered and low-pass filtered second and third sampled noises, wherein the fourth sampled noise may be a difference between the second and third sampled noises.

The correlated double sampling unit may be provided with an external input from the offset elimination, a noise provided through the external input, and a driving signal from which the offset is removed.

The specific period of the driving signal may be a half period of the driving signal.

According to another aspect of the present invention, there is provided a semiconductor system comprising: a panel provided with an external input; And a control chip for controlling the panel, wherein the control chip comprises: a logic module for providing a driving signal to the panel; a panel control module for reducing noise provided through the external input; Wherein the panel control module comprises: an offset eliminating unit for eliminating an offset of a driving signal provided from the panel; a reset unit for resetting the driving signal every half cycle of the driving signal; A first sampling is performed, wherein the first sampled noise is a noise difference between two consecutive reset points, a sampling section for alternately sampling second and third sampled noises, Performs buffering and low-pass filtering by receiving the third sampled noise, and outputs the buffered and low-pass filtered second and third sampled noises to the analog To-digital converter, wherein the first sampled noise includes first to third noise differences, the second sampled noise is a difference between the first and second noise differences, and the third sampled noise is a difference between the first and second noise differences, The sampled noise is the difference between the second and third noise differences, and the fourth sampled noise is the difference between the second and third sampled noises.

The analog-to-digital converter may fourthly sample the buffered and low-pass filtered second and third sampled noises, and the fourth sampled noise may be a difference between the second and third sampled noises.

The first amplification unit may include a charge amplification unit, and the second amplification unit may include a sample and hold amplification unit.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention.
Figure 2 is a diagram illustrating the correlated double sampling unit of Figure 1;
FIG. 3 is a view for explaining the first amplifying unit of FIG. 2. FIG.
4 and 5 are views for explaining the sampling unit of FIG.
6 is a timing chart for explaining a change in output voltage according to the operation of the semiconductor device of FIG.
7 is a timing chart for explaining a change in noise according to the operation of the semiconductor device of FIG.
8 is a block diagram illustrating a semiconductor device according to another embodiment of the present invention.
Figure 9 is a diagram illustrating the correlated double sampling unit of Figure 8;
10 is a diagram for explaining the sampling unit of FIG.
11 is a view for explaining the offset removing unit, the correlated double sampling unit, and the second amplifying unit of FIG.
12 is a block diagram illustrating a semiconductor system according to an embodiment of the present invention.
13 to 15 are exemplary electronic systems to which a semiconductor device according to some embodiments of the present invention may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention. Figure 2 is a diagram illustrating the correlated double sampling unit of Figure 1; FIG. 3 is a view for explaining the first amplifying unit of FIG. 2. FIG. 4 and 5 are views for explaining the sampling unit of FIG.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention may include an offset removal unit 120, a correlated double sampling unit 140, and the like. Here, the semiconductor device 100 may be, for example, but not limited to, a capacitive touch screen controller.

The offset removing unit 120 may receive the driving signal DS from the panel 10 to remove the offset of the driving signal DS.

Specifically, the offset removal unit 120 may receive the driving signal DS from the panel 10 and may remove an offset, i.e., an ambient portion, of the driving signal DS. The offset removal unit 120 may also provide the offset-removed drive signal OC-DS to the correlated double sampling unit 140.

The drive signal DS can be provided with a larger gain value by removing the offset of the drive signal DS so that the operation range of the semiconductor device 100 can be widened have.

Also, the offset removal section 120 may receive the noise N provided from the panel 10 through the external input. The offset removal unit 120 may provide the noise N provided from the panel 10 to the correlated double sampling unit 140.

Here, the panel 10 may include, for example, a touch screen panel, and more specifically, but not exclusively, an electrostatic touch screen panel. The external input may also include, for example, a touch input, and more specifically, but not exclusively, a touch input by a user's hand or an input by a stylus pen.

The panel 10 may include a mutual capacitance (not shown) formed between a horizontal line and a vertical line within the panel 10 and may be connected by a touch input When the capacitance value of the mutual capacitor is changed, the magnitude of the current input to the first amplifying unit 150 (see FIG. 2) described later is changed, and the touch sensing can be performed using the capacitance.

Further, when a voltage difference occurs between the panel 10 and the user's finger due to the touch of the user, the noise voltage of the user's finger is transmitted to the panel 10 through a self-capacitance (not shown) Lt; / RTI >

The correlation double sampling unit 140 may perform sampling by receiving the noise N and the offset-canceled driving signal OC-DS from the offset removal unit 120. [

Specifically, the correlated double sampling unit 140 reduces the noise N provided from the offset removal unit 120 through three sampling and outputs the noise N sampled three times to the analog-to-digital conversion unit 200 . Also, the correlation double sampling unit 140 increases the offset-removed drive signal OC-DS provided from the offset removal unit 120 through three sampling and outputs the drive signal OC-DS sampled three times to the analog- It is possible to provide the driving signal DS.

Here, the analog-to-digital conversion unit 200 receives the output of the correlated double sampling unit 140 (that is, the sum of the noise N-3S and the driving signal OC-DS-3S each sampled three times) It can be converted into a digital signal.

Referring to FIG. 2, the correlated double sampling unit 140 may include a first amplification unit 150 and a sampling unit 160.

The first amplifying unit 150 may perform the first sampling by receiving the noise N and the driving signal DS provided from the panel 10 through the external input.

Specifically, the first amplifying unit 150 receives the noise N supplied through the external input from the offset removing unit 120 and the driving signal OC-DS from which the offset is removed, and the first reset switch By resetting the drive signal OC-DS at a specific period of the drive signal DS and resetting the noise N and the offset-removed drive signal OC-DS through a reset. The first sampled noise (N-1S) may include a noise difference between two consecutive reset points, and a detailed description thereof will be described later.

Here, the first amplifying unit 150 may perform high-pass filtering on the noise N through reset to reduce low frequency noise and limit the frequency bandwidth. This can reduce the limiting factor in designing the circuit described later.

The first amplifying unit 150 may include, for example, a charge amplifier and the specific period of the driving signal DS may include, for example, a half period of the driving signal DS However, the present invention is not limited thereto.

The first amplifying unit 150 may provide the sampling unit 160 with the first sampled noise N-1S and the first sampled driving signal OC-DS-1S.

The sampling unit 160 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S from the first amplifying unit 150 and performs a plurality of sampling alternately have.

Specifically, the sampling unit 160 receives the first sampled noise N-1S from the first amplifying unit 150 to perform second and second sampling in turn, and performs second and second sampling (N-3S) can be generated by thirdly sampling the noise that has been generated by the noise processing unit.

The noise N can be reduced through this multiple sampling. Here, each sampling may be, for example, a correlated double sampling method, but is not limited thereto.

The sampling unit 160 receives the first sampled driving signal OC-DS-1S from the first amplifying unit 150 and alternately performs second and second sampling, And generate a third sampled driving signal OC-DS-3S by third sampling the sampled driving signal.

The driving signal DS can be increased through such a plurality of sampling. Here, each sampling may be, for example, a correlated double sampling method, but is not limited thereto.

The sampling unit 160 may provide the third sampled noise N-3S and the third sampled driving signal OC-DS-3S to the analog-to-digital conversion unit 200, The third sampled noise N-3S and the third sampled driving signal OC-DS-3S may be provided in a combined state.

Referring to FIG. 3, a circuit diagram of the first amplifier 150 of FIG. 2 is shown.

Specifically, the first amplifying unit 150 may include a first operational amplifier amp1, a first resistor R1, a first capacitor C1, and a first reset switch RS1.

The first operational amplifier amp1 receives the noise N and the offset-removed driving signal OC-DS from the offset eliminator 120 as an inverting input and receives the common mode voltage Vcom as the non- Can be provided. The first resistor R1 may be connected between the input and output terminals of the first operational amplifier amp1. Also, the first capacitor C1 may be connected in parallel with the first resistor R1, and the first reset switch RS1 may be connected in parallel with the first capacitor C1.

The first amplifier 150 has such a structure that the noise N provided through the external input can be high pass filtered using the first resistor R1 and the first capacitor C1 have.

As described above, the first reset switch RS1 resets the first amplifier 150 every predetermined period (for example, half period of the drive signal DS) of the drive signal DS, Pass filtering using the first capacitor R1 and the first capacitor C1.

Of course, the first amplifying unit 150 can perform the first sampling (i.e., the primary CDS) as well as the high-pass filtering through the reset by the first reset switch RS1.

Referring to Figures 4 and 5, the sampling unit 160 of Figure 2 is shown.

Specifically, the sampling unit 160 includes a first sub-sampling unit 165 and a second sub-sampling unit 170 for performing a second sampling (i.e., a second-order CDS), and a third sampling And a third sub-sampling unit 175 for performing a second sub-sampling process.

The first sub-sampling unit 165 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S to perform a second sampling and outputs a second sampled noise N 2S and the second sampled driving signal OC-DS-2S to the third subsampling unit 175. [

The first sub-sampling unit 165 includes a second capacitor C2, a first switch S1, a second switch S2, a first integrator INT1, and a second reset switch RS2 can do.

Specifically, the second capacitor C2 may be connected to the first amplifying unit 150. [ That is, the second capacitor C2 may be connected between the first amplifier 150 and the second switch S2.

The first switch S1 may be connected to the second capacitor C2 and may be provided with the common mode voltage Vcom. That is, the first switch S1 may be connected to the second capacitor C2 and the second switch S2 and may receive the common mode voltage Vcom.

The second switch S2 may be connected between the second capacitor C2 and the third sub-sampling unit 175. [ That is, the second switch S2 may be connected between the second capacitor C2 and the first integrator INT1, and may also be connected to the first switch S1 and the second reset switch RS2.

The first integrator INT1 may be connected between the second switch S2 and the third sub-sampling unit 175. [ That is, the first integrator INT1 may be connected between the second switch S2 and the third sub-sampling unit 175 and may be connected in parallel with the second reset switch RS2.

The first integrator INT1 may include a second operational amplifier amp2 and a fourth capacitor C4 and the fourth capacitor C4 may be connected between the input and output terminals of the second operational amplifier amp2 . More specifically, the fourth capacitor C4 is connected between the inverting input terminal and the output terminal of the second operational amplifier amp2, and the non-inverting input terminal of the second operational amplifier amp2 is connected to the common mode voltage Vcom / RTI >

The second reset switch RS2 may be connected in parallel with the first integrator INT1. That is, the second reset switch RS2 is connected in parallel with the fourth capacitor C4 and outputs the first integrator INT1 for every one driving period (for example, a whole cycle, not one period of the driving signal DS) Can be reset.

The second sub-sampling unit 170 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S to perform a second sampling and outputs a second sampled noise N Sampling signal (OC-DS-2S ') and the second sampled driving signal (OC-DS-2S') to the third subsampling unit 175.

The second sub-sampling unit 170 includes a third capacitor C3, a third switch S3, a fourth switch S4, a second integrator INT2, and a third reset switch RS3 can do.

Specifically, the third capacitor C3 may be connected to the first amplifier 150. [ That is, the third capacitor C3 may be connected between the first amplifying unit 150 and the fourth switch S4.

The third switch S3 may be connected to the third capacitor C3 and may receive the common mode voltage Vcom. That is, the third switch S3 may be connected to the third capacitor C3 and the fourth switch S4 and may receive the common mode voltage Vcom.

The fourth switch S4 may be connected between the third capacitor C3 and the third sub-sampling unit 175. [ That is, the fourth switch S4 may be connected between the third capacitor C3 and the second integrator INT2, and may also be connected to the third switch S3 and the third reset switch RS3.

The second integrator INT2 may be connected between the fourth switch S4 and the third sub-sampling unit 175. [ That is, the second integrator INT2 may be connected between the fourth switch S4 and the third sub-sampling unit 175 and may be connected in parallel with the third reset switch RS3.

The second integrator INT2 may include a third operational amplifier amp3 and a fifth capacitor C5 and a fifth capacitor C5 may be connected between the input and output terminals of the third operational amplifier amp3 . More specifically, the fifth capacitor C5 is connected between the inverting input terminal and the output terminal of the third operational amplifier amp3 and the non-inverting input terminal of the third operational amplifier amp3 is connected to the common mode voltage Vcom / RTI >

The third reset switch RS3 may be connected in parallel with the second integrator INT2. That is, the third reset switch RS3 is connected in parallel with the fifth capacitor C5 and outputs the second integrator INT2 every one driving period (for example, a whole cycle, not one period of the driving signal DS) Can be reset.

Here, the first switch S1 and the fourth switch S4 can be turned on or off at the same time. Also, the second switch S2 and the third switch S3 can be turned on or off at the same time. In addition, the first switch S1 and the fourth switch S4 can operate in opposition to the second switch S2 and the third switch S3. That is, when the first switch S1 and the fourth switch S4 are turned on, the second switch S2 and the third switch S3 are turned off and the first switch S1 and the fourth switch S4 Is turned off, the second switch S2 and the third switch S3 can be turned on.

The third sub-sampling unit 175 receives the second sampled noise N-2S and the second sampled driving signal OC-DS-2S from the first sub-sampling unit 165, (N-2S ') and the second sampled driving signal (OC-DS-2S') from the sampling circuit 170 and perform the third sampling

Specifically, the third sub-sampling unit 175 receives the second sampled noise N-2S and the second sampled driving signal OC-DS-2S from the first integrator INT1, (N-3S) by performing a subtraction operation by receiving a second sampled noise (N-2S ') and a second sampled driving signal (OC-DS-2S' And a third sampled driving signal OC-DS-3S.

The third sub-sampling unit 175 may provide a signal obtained by combining the third sampled noise N-3S and the third sampled driving signal OC-DS-3S to the analog-to-digital conversion unit 200 have.

Hereinafter, the change of the output voltage and the noise according to the operation of the semiconductor device of FIG. 1 will be described with reference to FIG. 6 and FIG.

6 is a timing chart for explaining a change in output voltage according to the operation of the semiconductor device of FIG. 7 is a timing chart for explaining a change in noise according to the operation of the semiconductor device of FIG.

Referring to Figs. 3, 5 and 6, there is shown a variation of the output voltage according to the operation of the semiconductor device 100 of Fig.

Specifically, at time t1, while the second switch S2 and the third switch S3 are turned on (the first switch S1 and the fourth switch S4 are turned off), the second capacitor C2 is turned off 1 integrator (INT1). The output voltage VOC-DS-1S of the first amplifying part 150 becomes equal to the common mode voltage Vcom + the first voltage change amount? V (I.e., Vcom + DELTA V) to the common mode voltage Vcom.

Here, Vcom + DELTA V is the output voltage (VOC-DS-1S) of the first amplifier 150 in the previous cycle (i.e., when the first switch S1 and the fourth switch S4 are turned on) ), And the first voltage change amount? V may be determined based on the drive signal DS. More specifically, the first voltage change amount? V may be expressed by Equation (1) below.

<Formula 1>

The first voltage change amount? V = the magnitude VH * of the drive signal voltage when the drive signal DS is in the first state (for example, the high level state) 10) / the capacitance value of the first capacitor (C1) of the first amplification unit (150)

The charge stored in the second capacitor C2 in the previous cycle (i.e., when the first switch S1 and the fourth switch S4 are turned on) (i.e., the capacitance value of the second capacitor C2 * (The capacitance value of the second capacitor C2 * the first voltage change amount DELTA V)) is discharged until the first integrator INT1 (i.e., To the fourth capacitor C4 of the second transistor Q4.

Assuming that the capacitance value of the fourth capacitor C4 is equal to the second capacitor C2 for convenience of explanation, the output voltage VOC-DS-2S of the first subsampling portion 165 is also the first voltage variation (? V).

The output voltage VOC-DS-1S of the first amplifying part 150 is set to the voltage level of the first amplifying part 150 when the driving signal voltage VDS changes from the second state (0V) to the first state (VH) The common mode voltage Vcom may change from the common mode voltage Vcom to the first voltage variation amount? V (i.e., Vcom -? V).

As a result, the charge stored in the second capacitor C2 is changed from 0 to - (the capacitance value of the second capacitor C2 * the first voltage change amount? V), and the same negative charge again The output voltage VOC-DS-2S of the first sub-sampling unit 165 may be further increased by the first voltage change amount DELTA V as it is transmitted to the fourth capacitor C4 of the first integrator INT1.

Accordingly, when the second switch S2 and the third switch S3 are turned on and the first switch S1 and the fourth switch S4 are turned off, the output of the first sub-sampling unit 165 The voltage VOC-DS-2S may increase by 2 * the first voltage change amount? V.

Thereafter, when the second switch S2 and the third switch S3 are turned off, charge equal to - (the capacitance value of the third capacitor C3 * the first voltage change amount? V) (C3). When the first switch S1 and the fourth switch S4 are turned on and the first reset switch RS1 is turned on at time t3, the capacitance value of the third capacitor C3 * the first voltage change amount? V ) Can be transferred to the fifth capacitor C5 of the second integrator INT2.

The output voltage VOC-DS-1S of the first amplifying unit 150 is set such that the second switch S2 and the third switch S3 are turned on and the first switch S1 and the fourth switch S4 are turned off The second switch S2 and the third switch S3 are turned off and the first switch S1 and the fourth switch S4 are turned on, the 2 * first voltage change amount? V). Also, the output voltage VOC-DS-2S 'of the second sub-sampling unit 170 can be reduced by 2 * the first voltage change amount? V.

Specifically, it is as follows.

The third capacitor C3 is turned off while the fourth switch S4 and the first switch S1 are turned on (the second switch S2 and the third switch S3 are turned off) at time t3, INT2). The output voltage VOC-DS-1S of the first amplifying unit 150 is the sum of the common mode voltage Vcom and the first voltage change amount? V (? V) as a result of the first reset switch RS1 being turned on at time t3 Vcom -? V) to the common mode voltage Vcom.

Here, Vcom - DELTA V is the output voltage (VOC-DS-1S) of the first amplifying part 150 in the previous cycle (i.e., when the second switch S2 and the third switch S3 are turned on) ).

(-) (capacitance value of the third capacitor C3 *) stored in the third capacitor C3 in the previous cycle (i.e., when the second switch S2 and the third switch S3 are turned on) (I.e., the capacitance value of the third capacitor C3 * the first voltage change amount DELTA V) is discharged until the second integrator INT2 (first voltage change amount DELTA V) To a fifth capacitor (C5) of the second transistor (C1).

The output voltage VOC-DS-2S 'of the second sub-sampling unit 170 is also set to the first voltage (V3), assuming that the capacitance value of the fifth capacitor C5 is the same as that of the third capacitor C3 Can be reduced by the amount of change DELTA V.

When the drive signal voltage VDS changes from the first state VH to the second state 0V at a time t4 after a short reset period, the output voltage VOC-DS-1S of the first amplifier 150 is The common mode voltage Vcom can be changed from the common mode voltage Vcom + the first voltage variation amount? V (i.e., Vcom +? V).

As a result, the charge stored in the third capacitor C3 changes from 0 to + (the capacitance value of the third capacitor C3 * the first voltage change amount? V), and the same positive positive charge The output voltage VOC-DS-2S 'of the second sub-sampling unit 170 is further reduced by the first voltage change amount DELTA V as it is transmitted to the fifth capacitor C5 of the second integrator INT2 have.

Accordingly, when the first switch S1 and the fourth switch S4 are turned on and the second switch S2 and the third switch S3 are turned off, the output of the second sub-sampling unit 170 The voltage VOC-DS-2S 'can be reduced by 2 * the first voltage change amount DELTA V.

That is, the amount of change of the output voltage VOC-DS-2S of the first sub-sampling unit 165 is the same as the amount of change of the output voltage VOC-DS-2S 'of the second subsampling unit 170, They can be opposite. Accordingly, the third sub-sampling unit 175 subtracts the output voltage VOC-DS-2S of the first sub-sampling unit 165 from the output voltage VOC-DS-2S 'of the second sub-sampling unit 170 The output voltage VOC-DS-3S of the third sub-sampling unit 175 can be changed by 4 * the first voltage change amount DELTA V by performing an operation of subtracting these two output voltages from each other.

 Referring now to FIGS. 3, 5 and 7, there is shown a variation in noise due to the operation of the semiconductor device 100 of FIG.

The first amplifying unit 150 may first sample the provided noise N every periodical reset (for example, a half cycle of the driving signal DS). Here, the first sampled noise N-1S may include a noise difference between two consecutive reset points (e.g., time t0 and time t1).

That is, the first amplifying unit 150 receiving the continuously increasing noise N can first sample the noise N through the periodic reset by the first reset switch RS1, The first sampled noise (N-1S) output through the unit 150 may correspond to each of the variations of the noise N between two consecutive reset points.

That is, the output of the first amplifying unit 150 through the primary CDS for the noise N can be prevented from being saturated due to the noise N provided through the external input.

Next, the first sampled noise (N-1S) is calculated by, for example, a first noise difference N (t1) -N (t0), a second noise difference N (t3) 3 noise difference (N (t5) -N (t3)). Of course, the times t0, t1, t3, and t5 correspond to successive reset points, respectively.

First, the first sub-sampling unit 165 starts operating while being reset at time t1, and outputs the first sampled noise N-1S (i.e., the first sampled noise) when the second and third switches S2 and S3 are turned on The first sampled noise N-1S when the second and third switches S2 and S3 are turned off (i.e., the first noise difference N (t1) -N (t0) The difference (N (t3) -N (t1))) can be provided and the two can be subtracted from each other. In other words, the first sub-sampling unit 165 performs a subtraction operation (a second CDS (Nos)) between the second noise difference N (t3) -N (t1) and the first noise difference N ) To generate a second sampled noise N-2S (i.e., {N (t3) -N (t1)} - {(N (t1) -N (t0)}).

Subsequently, the second sub-sampling unit 170 starts operating while being reset at the time t3, and outputs the first sampled noise N-1S (i.e., the second sampled noise N-1S) when the first and fourth switches S1 and S4 are turned on, The first sampled noise N-1S when the first and fourth switches S1 and S4 are turned off (i.e., the second noise difference N (t3) -N (t1) The difference (N (t5) -N (t3))) can be subtracted from each other. In other words, the first sub-sampling unit 165 performs a subtraction operation (a second CDS (t)) between the third noise difference N (t5) -N (t3) and the second noise difference N ) To generate a second 'sampled noise N-2S' (i.e., {N (t5) -N (t3)} - {(N (t3) -N (t0))} .

Next, the third sub-sampling unit 175 receives the second sampled noise N-2S (i.e., {N (t3) -N (t1)} - {(N (t) -N (t0))} from the second sub-sampling unit 170 and a second sampled noise N-2S '(i.e., {N (t5) -N (N (t3) -N (t0))}) to perform the third sampling.

  That is, the third sub-sampling unit 175 receives the second sampled noise N-2S (i.e., {N (t3) -N (t1)} - {(N (t1) -N (t0) (Third CDS) for subtracting the second sampled noise N-2S '(i.e., {N (t5) -N (t3)} { (T3) -N (t3) -N (t0)}] - [{N (t3) - ) -N (t1)} - {(N (t1) -N (t0))}].

As can be seen in FIG. 7, it can be seen that noise (N) is gradually reduced through third order sampling (i.e., CDS).

The semiconductor device 100 according to an embodiment of the present invention can reduce the noise N provided through the external input as well as the low frequency noise through the third-order CDS and amplify the driving signal DS. In addition, the semiconductor device 100 may remove the offset of the driving signal DS through the offset canceling unit 120 so that the driving signal DS is supplied with a larger gain value. In addition, since the drive signal DS is provided with a larger gain value, the operation range of the semiconductor device 100 itself can also be widened.

Hereinafter, a semiconductor device 300 according to another embodiment of the present invention will be described with reference to FIGS. 8 to 11. FIG. The difference from the above-described embodiment will be mainly described.

8 is a block diagram illustrating a semiconductor device according to another embodiment of the present invention. Figure 9 is a diagram illustrating the correlated double sampling unit of Figure 8; 10 is a diagram for explaining the sampling unit of FIG. 11 is a view for explaining the offset removing unit, the correlated double sampling unit, and the second amplifying unit of FIG.

8, a semiconductor device 300 according to another embodiment of the present invention includes an offset removing unit 310, a correlated double sampling unit 320, a second amplifying unit 380, an analog-to-digital converting unit 390 ).

The offset removing unit 310 performs the same function as the offset removing unit 120 of FIG. 1, and a description thereof will be omitted.

The correlated double sampling unit 320 may receive the noise N and the offset-canceled drive signal OS-DS from the offset eliminator 310 and perform sampling.

Specifically, the correlated double sampling unit 320 reduces the noise N provided from the offset removal unit 310 through two sampling and outputs the noise N-2S, which is sampled twice to the second amplifying unit 380, N-2S '). The correlation double sampling unit 320 also increases the offset-canceled drive signal OS-DS provided from the offset removal unit 310 through two sampling and outputs the drive signal OS-DS, which is sampled twice by the second amplification unit 380 Signal (OC-DS-2S, OC-DS-2S ').

The second amplifying unit 380 receives the second sampled noise N-2S and N-2S 'and the second sampled driving signals OC-DS-2S and OC-DS-2S' ) And low pass filtering. The second amplifying unit 380 amplifies the buffered and low-pass filtered second sampled noise N-2S, N-2S ', buffering and low-pass filtered second sampled driving signals OC-DS- OC-DS-2S ') to the analog-to-digital conversion unit 390.

Here, the second amplification unit 380 may include, for example, a sample and hold amplifier, but is not limited thereto.

The analog-to-digital converter 390 receives the buffered and low-pass filtered second sampled noise (N-2S, N-2S ') and the buffered and low-pass filtered second sampled driving signals (OC-DS- OC-DS-2S ') may be sampled third.

Specifically, the analog-to-digital converter 390 receives the buffered and low-pass filtered second sampled noise (N-2S, N-2S ') from the second amplifier 380, The third sampling may be performed by receiving the sampled driving signals OC-DS-2S and OC-DS-2S ', and the sum of the third sampled noise and the driving signal may be converted into a digital signal.

Here, the third sampled noise is a difference between the second sampled noises (N-2S, N-2S ') and the third sampled driving signal is the difference between the two sampled driving signals (OC-DS- OC-DS-2S ').

Referring to FIG. 9, the correlated double sampling unit 320 may include a first amplification unit 325 and a sampling unit 330.

The first amplifying unit 325 performs the same function as the first amplifying unit 150 of FIG. 2, and a description thereof will be omitted.

The sampling unit 330 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S from the first amplifying unit 325 and performs a plurality of sampling alternately have.

In detail, the sampling unit 330 receives the first sampled noise N-1S from the first amplification unit 325 and alternately performs second and second sampling, and performs second and second sampling (N-2S ') to the second amplifying unit 380. [0156] FIG.

The sampling unit 330 receives the first sampled driving signal OC-DS-1S from the first amplifying unit 325 and alternately performs second and second sampling. And may provide the sampled driving signal OC-DS-2S 'to the second amplifying unit 380.

Referring to FIG. 10, the sampling unit 330 may include a first sub-sampling unit 340 and a second sub-sampling unit 350. Unlike the sampling unit 160 of FIG. 4, the sampling unit 330 does not include the third sub-sampling unit 175 (FIG. 4).

Here, the first sub-sampling unit 340 and the second sub-sampling unit 350 output the respective outputs (the second sampled noise N-2S and the second sampled driving signals OC-DS-2S, 4 except that it provides the second amplified signal 380 to the second amplifying unit 380 in response to the second sampled noise N-2S 'and the second sampled driving signal OC-DS-2S' And may perform the same function as the sub-sampling unit 340 and the second sub-sampling unit 350.

Referring to FIG. 11, a circuit diagram of the offset removing unit 310, the first amplifying unit 325, the sampling unit 330, and the second amplifying unit 380 is shown.

The second amplifying unit 380 is added between the sampling unit 330 and the analog-to-digital converting unit 390, unlike the above-described embodiment (the semiconductor device 100) And the output terminal of the second sub-sampling unit 350 may be connected to the second amplifier unit 380 in a state where they are separated from each other.

Since the second amplifying unit 380 is also a differential structure, the second sampled noise N-2S and the second sampled driving signal OC-DS-2S provided from the first sub- Sampled noise (N-2S ') and the second sampled driving signal (OC-DS-2S') provided from the second sub-sampling unit 350, Pass filtering can be performed.

The semiconductor device 300 according to another embodiment of the present invention can reduce the noise N provided through the external input as well as the low frequency noise through the CDS over the third time and amplify the driving signal DS. In addition, unlike the semiconductor device 100, the semiconductor device 300 may include a second amplification unit 380 (i.e., a sample and hold amplification unit) to perform additional buffering and low-pass filtering, It is possible to further improve the immunity against. In addition, the semiconductor device 300 may remove the offset of the drive signal DS through the offset eliminator 120 so that the drive signal DS is provided with a larger gain value. In addition, since the drive signal DS is provided with a larger gain value, the operation range of the semiconductor device 300 itself can also be widened.

Hereinafter, a semiconductor system according to an embodiment of the present invention will be described with reference to FIG. The contents overlapping with the above-described embodiments will be omitted.

12 is a block diagram illustrating a semiconductor system according to an embodiment of the present invention.

Referring to FIG. 12, a semiconductor system 500 according to an embodiment of the present invention may include a panel 510 and a control chip 520.

Specifically, the panel 510 may be provided with an external input. The panel 510 may also be provided with a drive signal DS from the logic module 550 of the control chip 520.

Here, the panel 510 may include, for example, a touch screen panel, and more specifically, but not exclusively, an electrostatic touch screen panel. The external input may also include, for example, a touch input, and more specifically, but not exclusively, a touch input by a user's hand or an input by a stylus pen.

The control chip 520 includes a logic module 550 for providing a driving signal DS to the panel 510, a panel control module 530 for reducing the noise provided through the external input, And an analog-to-digital converter 540 for converting the output signal FS into a digital signal.

Herein, the logic module 550 may include, for example, an offset table, a flash memory, interface logic, a microcontroller unit (MCU), and the like.

In addition, the panel control module 530 may include the same configuration as the offset removal unit 310, the correlation double sampling unit 320, and the second amplification unit 380 in FIG. That is, the panel control module 530 includes an offset removal unit (not shown) for removing an offset of the drive signal DS provided from the panel 510, a reset unit 530 for resetting the drive signal DS every half cycle, DS) and a noise (N) provided through an external input through a reset, a first amplifying unit (not shown) for alternately performing a second and a second sampling of the first sampled noise and the driving signal, (Not shown), second and second sampled noise and driving signals to perform buffering and low-pass filtering, and buffering and low-pass filtered second and second sampled noise and driving signals And a second amplifying unit (not shown) provided to the analog-to-digital converting unit 540.

The analog-to-digital conversion unit 540 thirdly samples the output signal FS of the panel control module 530 (i.e., the second and second 'sampled noise and drive signals), and outputs the third sampled output signal It can be converted into a digital signal. That is, the analog-to-digital converter 540 may perform the same function as the analog-to-digital converter 390 of FIG.

13 to 15 are exemplary electronic systems to which a semiconductor device according to some embodiments of the present invention may be applied.

Fig. 13 shows a tablet PC 1200, Fig. 14 shows a notebook 1300, and Fig. 15 shows a smartphone 1400. Fig. The semiconductor devices 1 and 2 according to some embodiments of the present invention can be used in such a tablet PC 1200, the notebook 1300, the smart phone 1400, and the like.

It should also be apparent to those skilled in the art that the semiconductor devices 100 and 300 according to some embodiments of the present invention may be applied to other integrated circuit devices not illustrated. That is, although only the tablet PC 1200, the notebook computer 1300, and the smartphone 1400 are described as examples of the electronic system according to the present embodiment, the electronic system according to the present embodiment is not limited thereto. In some embodiments of the invention, the electronic system may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a wireless phone, A mobile phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, A digital audio recorder, a digital audio recorder, a digital picture recorder, a digital picture player, a digital video recorder, ), A digital video player, or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: Panel 120: Offset removal
140: correlation double sampling unit 150: first amplification unit
160: Sampling unit 165: First sub-sampling unit
170: second sub-sampling unit 175: third sub-sampling unit
200: analog-to-digital conversion section

Claims (10)

Wherein the first sampled noise is supplied in two consecutive periods, wherein the first sampled noise is supplied in two consecutive periods, An amplifier including a noise difference between reset points; And
And a sampling unit for alternately performing second and third sampling of the first sampled noise and fourth sampling the second and third sampled noises,
Wherein the first sampled noise comprises first to third noise differences, the second sampled noise is a difference between the first and second noise differences, and the third sampled noise is a difference between the first and second sampled noises, 3 &lt; / RTI &gt; noise difference, and the fourth sampled noise is a difference between the second and third sampled noises. The method according to claim 1,
Wherein,
A first operational amplifier,
A first resistor connected between the input and output terminals of the first operational amplifier,
A first capacitor connected in parallel with the first resistor,
And a first reset switch connected in parallel with the first capacitor. The method according to claim 1,
Wherein the specific period of the drive signal is a half cycle of the drive signal. The method according to claim 1,
And an offset removing unit that receives the driving signal from the panel and removes an offset of the driving signal. The method according to claim 1,
Wherein the sampling unit comprises:
A first sub-sampling unit for performing the second sampling,
A second sub-sampling unit for performing the third sampling,
And a third sub-sampling unit for performing the fourth sampling. 6. The method of claim 5,
Wherein the first sub-
A second capacitor connected to the amplifier,
A first switch connected to the second capacitor and receiving a common mode voltage,
A second switch connected between the second capacitor and the third sub-sampling unit,
A first integrator connected between the second switch and the third subsampling unit,
And a second reset switch connected in parallel with the first integrator. The method according to claim 6,
And the second sub-
A third capacitor connected to the amplifier,
A third switch connected to the third capacitor and receiving a common mode voltage,
A fourth switch connected between the third capacitor and the third subsampling unit,
A second integrator connected between the fourth switch and the third subsampling unit,
And a third reset switch connected in parallel with the second integrator. The method according to claim 1,
Wherein the amplifier section includes a first operational amplifier which is supplied with a common mode voltage,
Wherein the sampling unit includes a first sub-sampling unit for performing the second sampling, a second sub-sampling unit for performing the third sampling, and a third sub-sampling unit for performing the fourth sampling,
The first sub-sampling unit includes a second capacitor connected to the amplification unit, a second switch connected between the second capacitor and the third sub-sampling unit, and a second switch connected between the second switch and the third sub- 1 integrator. An offset canceling unit that receives a noise and a driving signal provided from an external input from the panel and removes an offset of the driving signal;
A correlated double sampling unit that reduces the noise through sampling; And
And a sample and hold amplifier for receiving the output of the correlated double sampling unit and performing buffering and low pass filtering,
The correlated double sampling unit first samples the noise provided through the external input through a reset at a specific period of the drive signal from which the offset has been removed and outputs the first sampled noise to the second and third And providing the second and third sampled noises to the sample and hold amplifier,
Wherein the first sampled noise is a noise difference between two consecutive reset points, the first sampled noise includes first to third noise differences, and the second sampled noise is a noise difference between the first and second Wherein the third sampled noise is a difference between the second and third noise differences. A panel provided with an external input; And
And a control chip for controlling the panel,
The control chip includes:
A logic module for providing a driving signal to the panel;
A panel control module for reducing noise provided through the external input;
And an analog-to-digital converter for converting an output signal of the panel control module into a digital signal,
Wherein the panel control module comprises:
An offset removing unit for removing an offset of a driving signal provided from the panel,
Wherein the first sampled noise is a noise difference between two consecutive reset points, wherein the first sampled noise is a noise difference between two consecutive reset points, ,
A sampling unit for alternately performing second and third sampling of the first sampled noise,
And a second amplifying unit that performs buffering and low-pass filtering by receiving the second and third sampled noises and provides the buffered and low-pass filtered second and third sampled noises to the analog-to-digital converting unit However,
Wherein the first sampled noise comprises first to third noise differences, the second sampled noise is a difference between the first and second noise differences, and the third sampled noise is a difference between the first and second sampled noises, 3 &lt; / RTI &gt; noise difference, and the fourth sampled noise is a difference between the second and third sampled noises.

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