KR102199869B1 - Semiconductor device and semiconductor system - Google Patents

Abstract

A semiconductor device and a semiconductor system are provided. The semiconductor device receives a driving signal and an external input from a panel, resets at a specific period of the driving signal, and first samples noise provided through an external input through reset, and the first sampled noise is 2 An amplification unit including a noise difference between four consecutive reset points; And a sampling unit for alternately sampling the second and third samples of the first sampled noise and for a fourth sampling of the second and third sampled noise, wherein the first sampled noise includes the first to third noise differences. And, the second sampled noise is the difference between the first and second noise, the third sampled noise is the difference between the second and third noise, and the fourth sampled noise is the second and third sampled noise Is the difference between.

Description

Semiconductor device and semiconductor system

The present invention relates to a semiconductor device and a semiconductor system.

In a capacitive touch controller, a read-out circuit is a main block that detects that the capacitance of a connected panel (for example, a touch panel) is changed by an external human hand or a conductor. These readout circuits may be affected by noise from an external environment. Therefore, developing immunity to noise is a key factor in detecting changes in capacitance.

The problem to be solved by the present invention is to provide a semiconductor device capable of enhancing immunity to noise through third-order correlated double sampling (CDS).

Another problem to be solved by the present invention is to provide a semiconductor system capable of enhancing immunity to noise through third-order correlated double sampling (CDS).

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

An embodiment of the semiconductor device of the present invention for solving the above problem is to receive noise and a driving signal provided through an external input from a panel, reset every specific period of the driving signal, and remove the noise through reset. An amplifying unit including one sampling, wherein the first sampled noise includes a noise difference between two consecutive reset points; And a sampling unit for alternately sampling the second and third samples of the first sampled noise and for a fourth sampling of the second and third sampled noise, wherein the first sampled noise includes the first to third noise differences. And, the second sampled noise is the difference between the first and second noise differences, the third sampled noise is the difference between the second and third noise differences, and the fourth sampled noise is the second and third sampling Is the difference between the noise.

The amplification unit includes a first operational amplifier, a first resistor connected between the input and output terminals of the first operational amplifier, a first capacitor connected in parallel with the first resistor, and a first reset switch connected in parallel with the first capacitor can do.

Noise provided through the external input may be high pass filtered through a first resistor and a first capacitor.

The specific period of the driving signal may be a half period of the driving signal.

The panel may include a touch screen panel, and an external input may include a touch input.

The amplification unit may include a charge amplifier.

It may further include an offset removing unit for removing an offset of the driving signal by receiving the driving signal from the panel.

The amplification unit may receive an external input from the offset removal unit, noise provided through the external input, and a driving signal from which the offset is removed.

The sampling unit may include a first sub-sampling unit performing second sampling, a second sub-sampling unit performing third sampling, and a third sub-sampling unit performing fourth sampling.

The first and second sub-sampling units may be positioned in parallel between the amplifying unit and the third sub-sampling unit.

The first sub-sampling unit may include a second capacitor connected to the amplifying unit, a first switch connected to the second capacitor and receiving a common mode voltage, and connected between the second capacitor and the third sub-sampling unit. It may include a second switch, a first integrator connected between the second switch and the third sub-sampling unit, and a second reset switch connected in parallel with the first integrator.

The second sub-sampling unit includes a third capacitor connected to the amplifying unit, a third switch connected to the third capacitor and receiving a common mode voltage, and connected between the third capacitor and the third sub-sampling unit. It may include a fourth switch, a second integrator connected between the fourth switch and the third sub-sampling unit, and a third reset switch connected in parallel with the second integrator.

Each of the first and second integrators may include second and third operational amplifiers, and the second and third operational amplifiers may receive a common mode voltage.

The third sub-sampling unit may perform a subtraction operation by receiving outputs of each of the first and second integrators.

The first switch and the fourth switch may be simultaneously turned on or turned off.

The second switch and the third switch may be turned on or off at the same time.

The amplification unit includes a first operational amplifier receiving a common mode voltage, and the sampling unit performs a first sub-sampling unit for performing a second sampling, a second sub-sampling unit for performing a third sampling, and a fourth sampling unit. A third sub-sampling unit, wherein the first sub-sampling unit includes a second capacitor connected to the amplifying unit, a second switch connected between the second capacitor and the third sub-sampling unit, and between the second switch and the third sub-sampling unit It may include a first integrator connected to.

When the driving signal is in the first state and the second switch is turned on and the amplifying unit is reset, the output voltage of the amplifying unit may decrease by a first voltage change amount, and the output voltage of the first integrator may increase by a first voltage change amount.

When the driving signal is changed to a second state different from the first state, the output voltage of the amplifying unit may be further decreased by the first voltage change amount, and the output voltage of the first integrator may further increase by the first voltage change amount.

The second sub-sampling unit operates in the same manner as the first sub-sampling unit, except that the polarity of the output voltage change amount of the second sub-sampling unit is opposite to the polarity of the output voltage change amount of the first sub-sampling unit, and And a difference between the output voltage variation amount of each of the third sub-sampling units.

The first voltage change amount may be determined based on a driving signal.

Another embodiment of the semiconductor device of the present invention for solving the above problem includes: an offset removing unit receiving noise and a driving signal provided through an external input from a panel and removing an offset of the driving signal; A correlated double sampling unit that reduces noise through sampling; And a sample-and-hold amplifier that receives the output of the correlated double sampling unit and performs buffering and low pass filtering, wherein the correlated double sampling unit is reset at a specific period of the driving signal from which the offset is removed. The noise provided through the external input through (reset) is first sampled, the first sampled noise is alternately sampled second and third, and the second and third sampled noise is provided to the sample and hold amplification unit. , The first sampled noise is a noise difference between two consecutive reset points, the first sampled noise includes a first to third noise difference, and the second sampled noise is between the first and second noise differences And the third sampled noise is the difference between the second and third noise differences.

The sample-and-hold amplifying unit may buffer and low-pass filter the second and third sampled noise.

An analog-to-digital converter for fourth sampling the second and third sampled noises subjected to the buffering and low pass filtering may be further included, wherein the fourth sampled noise may be a difference between the second and third sampled noises.

The correlated double sampling unit may receive an external input from an offset removal unit, noise provided through the external input, and a driving signal from which the offset is removed.

The specific period of the driving signal may be a half period of the driving signal.

An embodiment of the semiconductor system of the present invention for solving the above other problems, a panel receiving an external input; And a control chip for controlling the panel, wherein the control chip includes a logic module providing a driving signal to the panel, a panel control module reducing noise provided through an external input, and an output signal of the panel control module as a digital signal. It includes an analog-to-digital conversion unit that converts, wherein the panel control module includes an offset removing unit that removes an offset of a driving signal provided from the panel, and resets every half cycle of the driving signal, and resets noise provided through an external input. The first sampled noise is a first amplification unit that is a noise difference between two consecutive reset points, a sampling unit that alternately samples the second and third samples of the first sampled noise, and the second and Including a second amplification unit that receives the third sampled noise, performs buffering and low pass filtering, and provides the buffered and low pass filtered second and third sampled noise to the analog-to-digital converter, wherein the first sampled The noise includes the first to third noise differences, the second sampled noise is the difference between the first and second noise differences, the third sampled noise is the difference between the second and third noise differences, and 4 Sampled noise is the difference between the second and third sampled noise.

The analog-to-digital converter performs a fourth sample of the buffered and low-pass filtered second and third sampled noise, and the fourth sampled noise may be a difference between the second and third sampled noise.

The first amplification unit may include a charge amplification unit, and the second amplification unit may include a sample and hold amplification unit.

Other specific details of the present invention are included in the detailed description and drawings.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the correlated double sampling unit of FIG. 1.
3 is a diagram illustrating a first amplifier of FIG. 2.
4 and 5 are diagrams illustrating a sampling unit of FIG. 2.
6 is a timing diagram illustrating a change in an output voltage according to an operation of the semiconductor device of FIG. 1.
FIG. 7 is a timing diagram illustrating a change in noise according to an operation of the semiconductor device of FIG. 1.
8 is a block diagram illustrating a semiconductor device according to another embodiment of the present invention.
9 is a diagram illustrating the correlated double sampling unit of FIG. 8.
10 is a diagram illustrating a sampling unit of FIG. 9.
11 is a diagram illustrating an offset removing unit, a correlated double sampling unit, and a second amplifying unit of FIG. 8.
12 is a block diagram illustrating a semiconductor system according to an embodiment of the present invention.
13 to 15 are exemplary electronic systems to which a semiconductor device according to some embodiments of the present invention can be applied.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims. The sizes and relative sizes of components indicated in the drawings may be exaggerated for clarity of description. Throughout the specification, the same reference numerals refer to the same elements, and “and/or” includes each and all combinations of one or more of the recited items.

When an element or layer is referred to as “on” or “on” of another element or layer, it is possible to interpose another layer or other element in the middle as well as directly above the other element or layer. All inclusive. On the other hand, when a device is referred to as "directly on" or "directly on", it indicates that no other device or layer is interposed therebetween.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc., as shown in the figure It may be used to easily describe the correlation between the device or components and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, if an element shown in the figure is turned over, an element described as “below” or “beneath” of another element may be placed “above” another element. Accordingly, the exemplary term “below” may include both directions below and above. The device may be oriented in other directions, and thus spatially relative terms may be interpreted according to the orientation.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, “comprises” and/or “comprising” do not exclude the presence or addition of one or more other elements other than the mentioned elements.

Although the first, second, etc. are used to describe various devices or components, it is a matter of course that these devices or components are not limited by these terms. These terms are only used to distinguish one device or component from another device or component. Therefore, it goes without saying that the first device or component mentioned below may be a second device or component within the technical idea of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings that can be commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not interpreted ideally or excessively unless explicitly defined specifically.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the correlated double sampling unit of FIG. 1. 3 is a diagram illustrating a first amplifier of FIG. 2. 4 and 5 are diagrams illustrating a sampling unit of FIG. 2.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention may include an offset removing unit 120 and a correlated double sampling unit 140. Here, the semiconductor device 100 may be, for example, a capacitive touch screen controller, but is not limited thereto.

The offset removal unit 120 may receive the driving signal DS from the panel 10 and remove the offset of the driving signal DS.

Specifically, the offset removal unit 120 may receive the driving signal DS from the panel 10 and remove the offset of the driving signal DS, that is, an ambient portion. In addition, the offset removal unit 120 may provide the driving signal OC-DS from which the offset is removed to the correlated double sampling unit 140.

As the offset removal unit 120 removes the offset of the driving signal DS, the driving signal DS may be provided with a larger gain value, thereby expanding the operation range of the semiconductor device 100. have.

In addition, the offset removal unit 120 may receive noise N provided through an external input from the panel 10. The offset removing unit 120 may provide the noise N provided from the panel 10 to the correlated double sampling unit 140.

Here, the panel 10 may include, for example, a touch screen panel, and more specifically, may include a capacitive touch screen panel, but is not limited thereto. In addition, the external input may include, for example, a touch input, and more specifically, may include a touch input by a user's hand or an input by a stylus pen, but is not limited thereto.

The panel 10 may include a mutual capacitance (not shown) formed between a horizontal line and a vertical line therein, and may be formed by a touch input (eg, a user's finger touch). When the capacitance value of the mutual capacitor is changed, the magnitude of the current flowing into the first amplifying unit (150 in FIG. 2) to be described later is changed, and touch sensing may be performed using this.

In addition, when a voltage difference occurs between the panel 10 and, for example, the user's finger due to the user's touch, the noise voltage of the user's finger is reduced to the panel 10 through a self-capacitance (not shown). Can be provided as

The correlated double sampling unit 140 may perform sampling by receiving the driving signal OC-DS from which the noise N and the offset have been removed from the offset removing unit 120.

Specifically, the correlated double sampling unit 140 reduces the noise (N) provided from the offset removal unit 120 through three sampling times to reduce the noise (N) sampled three times by the analog-to-digital conversion unit 200. Can provide. In addition, the correlated double sampling unit 140 increases the offset-removed drive signal (OC-DS) provided from the offset removal unit 120 through three sampling times, and is sampled three times by the analog-to-digital conversion unit 200. A driving signal DS may be provided.

Here, the analog-digital conversion unit 200 receives the output of the correlated double sampling unit 140 (that is, the sum of the noise (N-3S) and the driving signal (OC-DS-3S) sampled three times each) It can be converted into a digital signal.

Referring to FIG. 2, the correlated double sampling unit 140 may include a first amplifying unit 150 and a sampling unit 160.

The first amplifying unit 150 may receive noise N and a driving signal DS provided through an external input from the panel 10 and perform a first sampling.

Specifically, the first amplification unit 150 receives noise (N) provided through an external input from the offset removal unit 120 and a driving signal OC-DS from which the offset is removed, and a first reset switch (FIG. 3) The driving signal OC-DS, which is reset every specific period of the driving signal DS by R1), and from which noise N and offset are removed, may be first sampled through reset. The first sampled noise N-1S may include a noise difference between two consecutive reset points, and a detailed description thereof will be described later.

Here, the first amplifying unit 150 may perform high pass filtering on the noise N through reset to reduce low-frequency noise and limit a frequency bandwidth. Through this, it is possible to reduce the limiting factor when designing a circuit to be described later.

The first amplifying unit 150 may include, for example, a charge amplifier, and a specific period of the driving signal DS may include, for example, a half period of the driving signal DS. However, it is not limited thereto.

In addition, the first amplifying unit 150 may provide the first sampled noise N-1S and the first sampled driving signal OC-DS-1S to the sampling unit 160.

The sampling unit 160 may receive a first sampled noise N-1S and a first sampled driving signal OC-DS-1S from the first amplifying unit 150 and alternately perform a plurality of sampling. have.

Specifically, the sampling unit 160 receives the first sampled noise N-1S from the first amplifying unit 150 and alternately performs second and second' sampling, and the second and second' sampling The third sampled noise may be sampled to generate a third sampled noise N-3S.

Noise (N) may be reduced through such a number of sampling. Here, each sampling may be, for example, a correlated double sampling method, but is not limited thereto.

In addition, the sampling unit 160 receives the first sampled driving signal OC-DS-1S from the first amplifying unit 150 and alternately performs second and second ′ sampling, and performs the second and second ′ sampling. A third sampled driving signal OC-DS-3S may be generated by third sampling the sampled driving signal.

The driving signal DS may be increased through such a plurality of sampling. Here, each sampling may be, for example, a correlated double sampling method, but is not limited thereto.

The sampling unit 160 may provide the third sampled noise N-3S and the third sampled driving signal OC-DS-3S to the analog-to-digital conversion unit 200, and the analog-to-digital conversion unit When provided at 200, the third sampled noise N-3S and the third sampled driving signal OC-DS-3S may be provided in a combined state.

Referring to FIG. 3, a circuit diagram of the first amplifier 150 of FIG. 2 is shown.

Specifically, the first amplifier 150 may include a first operating amplifier (amp1), a first resistor (R1), a first capacitor (C1), and a first reset switch (RS1).

The first operational amplifier (amp1) receives the noise (N) and the driving signal (OC-DS) from which the offset is removed from the offset removing unit 120 as an inverting input, and a common mode voltage (Vcom) as a non-inverting input. Can be provided. The first resistor R1 may be connected between the input and output terminals of the first operational amplifier amp1. In addition, the first capacitor C1 may be connected in parallel with the first resistor R1, and the first reset switch RS1 may be connected in parallel with the first capacitor C1.

Since the first amplifier 150 has such a structure, high pass filtering can be performed on the noise N provided through an external input using the first resistor R1 and the first capacitor C1. have.

In addition, as described above, the first reset switch RS1 resets the first amplifying unit 150 every specific period of the driving signal DS (for example, a half period of the driving signal DS), thereby High pass filtering using (R1) and the first capacitor (C1) may be enabled.

Of course, the first amplification unit 150 may perform first sampling (ie, primary CDS) as well as high pass filtering through reset by the first reset switch RS1.

4 and 5, the sampling unit 160 of FIG. 2 is shown.

Specifically, the sampling unit 160 includes a first sub-sampling unit 165 and a second sub-sampling unit 170 performing a second sampling (ie, secondary CDS), and a third sampling (ie, a third CDS). It may include a third sub-sampling unit 175 to perform ).

The first sub-sampling unit 165 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S, performs a second sampling, and performs a second sampled noise N-1S. -2S) and the second sampled driving signal OC-DS-2S may be provided to the third sub-sampling unit 175.

In addition, the first sub-sampling unit 165 includes a second capacitor C2, a first switch S1, a second switch S2, a first integrator INT1, and a second reset switch RS2. can do.

Specifically, the second capacitor C2 may be connected to the first amplifier 150. That is, the second capacitor C2 may be connected between the first amplifying unit 150 and the second switch S2.

The first switch S1 is connected to the second capacitor C2 and may receive a common mode voltage Vcom. That is, the first switch S1 may be connected to the second capacitor C2 and the second switch S2 and may receive the common mode voltage Vcom.

The second switch S2 may be connected between the second capacitor C2 and the third sub-sampling unit 175. That is, the second switch S2 may be connected between the second capacitor C2 and the first integrator INT1, and may also be connected to the first switch S1 and the second reset switch RS2.

The first integrator INT1 may be connected between the second switch S2 and the third sub-sampling unit 175. That is, the first integrator INT1 may be connected between the second switch S2 and the third sub-sampling unit 175 and may be connected in parallel with the second reset switch RS2.

In addition, the first integrator INT1 may include a second operational amplifier amp2 and a fourth capacitor C4, and the fourth capacitor C4 is connected between the input and output terminals of the second operational amplifier amp2. I can. More specifically, the fourth capacitor C4 is connected between the inverting input terminal and the output terminal of the second operational amplifier amp2, and a common mode voltage Vcom is applied to the non-inverting input terminal of the second operational amplifier amp2. Is provided.

The second reset switch RS2 may be connected in parallel with the first integrator INT1. That is, the second reset switch RS2 is connected in parallel with the fourth capacitor C4, and the first integrator INT1 is operated every one driving period (for example, not one period of the driving signal DS). Can be reset.

The second sub-sampling unit 170 receives the first sampled noise N-1S and the first sampled driving signal OC-DS-1S, performs a second sampling, and performs the second sampled noise N-1S. -2S') and the second sampled driving signal OC-DS-2S' may be provided to the third sub-sampling unit 175.

In addition, the second sub-sampling unit 170 includes a third capacitor C3, a third switch S3, a fourth switch S4, a second integrator INT2, and a third reset switch RS3. can do.

Specifically, the third capacitor C3 may be connected to the first amplifier 150. That is, the third capacitor C3 may be connected between the first amplifying unit 150 and the fourth switch S4.

The third switch S3 is connected to the third capacitor C3 and may be provided with a common mode voltage Vcom. That is, the third switch S3 may be connected to the third capacitor C3 and the fourth switch S4 and may receive the common mode voltage Vcom.

The fourth switch S4 may be connected between the third capacitor C3 and the third sub-sampling unit 175. That is, the fourth switch S4 may be connected between the third capacitor C3 and the second integrator INT2, and may also be connected to the third switch S3 and the third reset switch RS3.

The second integrator INT2 may be connected between the fourth switch S4 and the third sub-sampling unit 175. That is, the second integrator INT2 may be connected between the fourth switch S4 and the third sub-sampling unit 175 and may be connected in parallel with the third reset switch RS3.

In addition, the second integrator INT2 may include a third operational amplifier (amp3) and a fifth capacitor (C5), and the fifth capacitor (C5) is connected between the input and output terminals of the third operational amplifier (amp3). I can. More specifically, the fifth capacitor C5 is connected between the inverting input terminal and the output terminal of the third operational amplifier amp3, and a common mode voltage Vcom is applied to the non-inverting input terminal of the third operational amplifier amp3. Is provided.

The third reset switch RS3 may be connected in parallel with the second integrator INT2. That is, the third reset switch RS3 is connected in parallel with the fifth capacitor C5, and the second integrator INT2 is operated every one driving period (for example, not one period of the driving signal DS). Can be reset.

Here, the first switch S1 and the fourth switch S4 may be simultaneously turned on or turned off. Also, the second switch S2 and the third switch S3 may be turned on or off at the same time. Additionally, the first switch S1 and the fourth switch S4 may operate opposite to the second switch S2 and the third switch S3. That is, when the first switch S1 and the fourth switch S4 are turned on, the second switch S2 and the third switch S3 are turned off, and the first switch S1 and the fourth switch S4 are turned off. When) is turned off, the second switch S2 and the third switch S3 may be turned on.

The third sub-sampling unit 175 receives the second sampled noise N-2S and the second sampled driving signal OC-DS-2S from the first sub-sampling unit 165 and receives a second sub-sampling unit. The third sampling may be performed by receiving the second sampled noise N-2S' and the second sampled driving signal OC-DS-2S' from 170.

Specifically, the third sub-sampling unit 175 receives the second sampled noise N-2S and the second sampled driving signal OC-DS-2S from the first integrator INT1, and receives the second integrator ( The third sampled noise (N-3S) is performed by performing a subtraction operation by receiving the second' sampled noise (N-2S') and the second' sampled driving signal (OC-DS-2S') from INT2). And a third sampled driving signal OC-DS-3S may be generated.

The third sub-sampling unit 175 may provide a signal in which the third sampled noise N-3S and the third sampled driving signal OC-DS-3S are combined to the analog-to-digital converter 200. have.

Hereinafter, changes in output voltage and noise according to the operation of the semiconductor device of FIG. 1 will be described with reference to FIGS. 6 and 7.

6 is a timing diagram illustrating a change in an output voltage according to an operation of the semiconductor device of FIG. 1. FIG. 7 is a timing diagram illustrating a change in noise according to an operation of the semiconductor device of FIG. 1.

3, 5, and 6 illustrate changes in output voltages according to the operation of the semiconductor device 100 of FIG. 1.

Specifically, at time t1, the second switch S2 and the third switch S3 are turned on (the first switch S1 and the fourth switch S4 are turned off), and the second capacitor C2 is 1 Can be connected to the integrator (INT1). In addition, as a result of turning on the first reset switch RS1 at time t1, the output voltage VOC-DS-1S of the first amplifier 150 is the common mode voltage Vcom + the first voltage change amount (ΔV). ) (That is, Vcom + ΔV) to the common mode voltage (Vcom).

Here, Vcom + ΔV is the output voltage (VOC-DS-1S) of the first amplifier 150 in the previous cycle (that is, when the first switch S1 and the fourth switch S4 are turned on). ), and the first voltage change amount ΔV may be determined based on the driving signal DS. More specifically, the first voltage change amount ΔV may be as shown in Equation 1 below.

<Equation 1>

The first voltage change amount (ΔV) = the magnitude of the driving signal voltage (VH) when the driving signal DS is in the first state (for example, a high level state) * (Panel (Fig. 10) the capacitance value of the mutual capacitor / the capacitance value of the first capacitor (C1) of the first amplifier 150)

In addition, the charge stored in the second capacitor C2 in the previous cycle (that is, when the first switch S1 and the fourth switch S4 are turned on) (that is, the capacitance value of the second capacitor C2 * 1st The voltage change amount (ΔV)) is discharged until it becomes 0, and the corresponding charge (i.e.,-(capacitance value of the second capacitor C2 * first voltage change amount (△V))) is the first integrator (INT1). ) May be transferred to the fourth capacitor C4.

For convenience of explanation, assuming that the capacitance value of the fourth capacitor C4 is the same as the second capacitor C2, the output voltage VOC-DS-2S of the first sub-sampling unit 165 is also the first voltage change amount. It can be increased by (△V).

After a short reset period, when the driving signal voltage VDS changes from the second state (0V) to the first state (VH) at time t2, the output voltage (VOC-DS-1S) of the first amplifier 150 is The common mode voltage Vcom may change from the common mode voltage Vcom to the first voltage change amount ΔV (ie, Vcom-ΔV).

As a result, the charge stored in the second capacitor C2 changes from 0 to-(the capacitance value of the second capacitor C2 * the first voltage change amount (ΔV)), and the same amount of negative charge is again The output voltage VOC-DS-2S of the first sub-sampling unit 165 by being transferred to the fourth capacitor C4 of the first integrator INT1 may further increase by the first voltage change amount ΔV.

Accordingly, when the second switch S2 and the third switch S3 are turned on, and the first switch S1 and the fourth switch S4 are turned off, as a result, the output of the first sub-sampling unit 165 The voltage VOC-DS-2S may increase by 2 * the first voltage change amount ΔV.

Thereafter, when the second switch (S2) and the third switch (S3) are turned off,-(capacitance value of the third capacitor (C3) * the first voltage change amount (ΔV)) of the third capacitor Can be stored in (C3). In addition, at time t3, when the first switch S1 and the fourth switch S4 are turned on and the first reset switch RS1 is turned on,-(capacitance value of the third capacitor C3 * first voltage change amount (△V) )) may be transferred to the fifth capacitor C5 of the second integrator INT2.

As for the output voltage VOC-DS-1S of the first amplifier 150, the second switch S2 and the third switch S3 are turned on, and the first switch S1 and the fourth switch S4 are turned off. Unlike in the previous state, when the second switch S2 and the third switch S3 are turned off, and the first switch S1 and the fourth switch S4 are turned on, 2 * the first voltage change amount (△ It can be increased by V). In addition, the output voltage VOC-DS-2S' of the second sub-sampling unit 170 may decrease by 2 * the first voltage change amount ΔV.

Looking at this in detail, it is as follows.

At time t3, while the fourth switch S4 and the first switch S1 are turned on (the second switch S2 and the third switch S3 are turned off), the third capacitor C3 is turned on to the second integrator ( INT2) can be connected. In addition, as a result of turning on the first reset switch RS1 at time t3, the output voltage VOC-DS-1S of the first amplifier 150 is the common mode voltage Vcom-the first voltage change amount ΔV That is, it may change from Vcom-ΔV) to the common mode voltage Vcom.

Here, Vcom-ΔV is the output voltage (VOC-DS-1S) of the first amplifier 150 in the previous cycle (that is, when the second switch S2 and the third switch S3 are turned on). ) Can be.

In addition, the charge stored in the third capacitor C3 in the previous cycle (that is, when the second switch S2 and the third switch S3 are turned on) (i.e.,-(capacitance value of the third capacitor C3 * The first voltage change amount (△V)) is discharged until it becomes 0, and the corresponding charge (that is, the capacitance value of the third capacitor C3 * the first voltage change amount (△V)) is the second integrator INT2 ) May be transferred to the fifth capacitor C5.

For convenience of explanation, assuming that the capacitance value of the fifth capacitor C5 is the same as the third capacitor C3, the output voltage VOC-DS-2S' of the second sub-sampling unit 170 is also the first voltage. It can be reduced by the amount of change (△V).

After a short reset period, when the driving signal voltage VDS changes from the first state (VH) to the second state (0V) at time t4, the output voltage (VOC-DS-1S) of the first amplifier 150 is The common mode voltage Vcom may change from the common mode voltage Vcom + the first voltage change amount ΔV (ie, Vcom + ΔV).

As a result, the charge stored in the third capacitor C3 changes from 0 to + (the capacitance value of the third capacitor C3 * the first voltage change amount (ΔV)), and the same amount of positive charge is changed. It is transferred to the fifth capacitor C5 of the second integrator INT2 again, and the output voltage VOC-DS-2S' of the second sub-sampling unit 170 can be further reduced by the first voltage change amount ΔV. have.

Accordingly, when the first switch S1 and the fourth switch S4 are turned on, and the second switch S2 and the third switch S3 are turned off, as a result, the output of the second sub-sampling unit 170 The voltage VOC-DS-2S' may decrease by 2 * the first voltage change amount ΔV.

That is, the amount of change in the output voltage VOC-DS-2S of the first sub-sampling unit 165 is the same as the amount of change in the output voltage VOC-DS-2S' of the second sub-sampling unit 170, and the polarity is They can be opposite to each other. Accordingly, the third sub-sampling unit 175 determines the output voltage VOC-DS-2S of the first sub-sampling unit 165 and the output voltage VOC-DS-2S' of the second sub-sampling unit 170 By receiving and subtracting the two output voltages from each other, the output voltage VOC-DS-3S of the third sub-sampling unit 175 can be changed by 4 * the first voltage change amount ΔV.

Next, referring to FIGS. 3, 5 and 7, changes in noise according to the operation of the semiconductor device 100 of FIG. 1 are illustrated.

The first amplifying unit 150 may first sample the supplied noise N for each periodic reset (eg, a half cycle of the driving signal DS). Here, the first sampled noise N-1S may include a noise difference between two consecutive reset points (eg, time t0 and time t1).

That is, the first amplification unit 150 receiving the continuously increasing noise N may first sample the noise N through periodic reset by the first reset switch RS1, and the first amplification The first sampled noise N-1S output through the unit 150 may correspond to each change in noise N between two consecutive reset points.

That is, it is possible to prevent the output of the first amplifier 150 from being saturated due to the noise N provided through the external input through the primary CDS for the noise N.

Subsequently, the first sampled noise N-1S is, for example, a first noise difference (N(t1)-N(t0)), a second noise difference (N(t3)-N(t1)), Suppose you include the 3 noise difference (N(t5)-N(t3)). Of course, times t0, t1, t3, and t5 respectively correspond to successive reset points.

First, the first sub-sampling unit 165 starts operating while being reset at time t1, and the first sampled noise (N-1S) when the second and third switches S2 and S3 are turned on (i.e., The first noise difference (N(t1)-N(t0)) and the first sampled noise (N-1S) when the second and third switches S2 and S3 are turned off (that is, the second noise Given the difference (N(t3)-N(t1)), you can subtract the two from each other. That is, the first sub-sampling unit 165 performs a subtraction operation (secondary CDS) between the second noise difference (N(t3)-N(t1)) and the first noise difference (N(t1)-N(t0)). ), the second sampled noise N-2S (that is, {N(t3)-N(t1)}-{(N(t1)-N(t0))}) may be generated.

Subsequently, the second sub-sampling unit 170 starts operation while being reset at time t3, and the first sampled noise (N-1S) when the first and fourth switches S1 and S4 are turned on (i.e., The second noise difference (N(t3)-N(t1)) and the first sampled noise (N-1S) when the first and fourth switches S1 and S4 are turned off (that is, the third noise Given the difference (N(t5)-N(t3)), you can subtract the two from each other. That is, the first sub-sampling unit 165 performs a subtraction operation (second CDS) between the third noise difference (N(t5)-N(t3)) and the second noise difference (N(t3)-N(t1)). ), it is possible to generate the second' sampled noise N-2S' (that is, {N(t5)-N(t3)}-{(N(t3)-N(t0))}). .

Next, the third sub-sampling unit 175 is the second sampled noise (N-2S) from the first sub-sampling unit 165 (that is, {N(t3)-N(t1)}-{(N( t1)-N(t0))}) and the second' sampled noise N-2S' from the second sub-sampling unit 170 (that is, {N(t5)-N(t3)}-{ A third sampling may be performed by receiving (N(t3)-N(t0))}).

That is, the third sub-sampling unit 175 is the second sampled noise N-2S (that is, {N(t3)-N(t1)}-{(N(t1)-N(t0))}) And the second' sampled noise (N-2S') (that is, {N(t5)-N(t3)} {(N(t3)-N(t0))}) subtracted from each other (3rd order CDS) By performing the third sampled noise (N-3S) (that is, [{N(t5)-N(t3)}-{(N(t3)-N(t0))})-[{N(t3 )-N(t1)}-{(N(t1)-N(t0))}]) can be generated.

As can be seen from FIG. 7, it can be seen that the noise (N) gradually decreases through three-order sampling (ie, CDS).

The semiconductor device 100 according to an exemplary embodiment of the present invention may reduce not only low-frequency noise but also noise N provided through an external input and amplify the driving signal DS through three-order CDS. In addition, the semiconductor device 100 may remove the offset of the driving signal DS through the offset removing unit 120 so that the driving signal DS receives a larger gain value. In addition, as the driving signal DS is provided with a larger gain value, the operation range of the semiconductor device 100 itself may be widened.

Hereinafter, a semiconductor device 300 according to another embodiment of the present invention will be described with reference to FIGS. 8 to 11. It will be described focusing on differences from the above-described embodiment.

8 is a block diagram illustrating a semiconductor device according to another embodiment of the present invention. 9 is a diagram illustrating the correlated double sampling unit of FIG. 8. 10 is a diagram illustrating the sampling unit of FIG. 9. 11 is a diagram illustrating an offset removing unit, a correlated double sampling unit, and a second amplifying unit of FIG.

Referring to FIG. 8, a semiconductor device 300 according to another embodiment of the present invention includes an offset removing unit 310, a correlated double sampling unit 320, a second amplifying unit 380, and an analog-to-digital conversion unit 390. ) Can be included.

The offset removal unit 310 performs the same role as the offset removal unit 120 of FIG. 1, and a description thereof will be omitted.

The correlated double sampling unit 320 may perform sampling by receiving the driving signal OS-DS from which the noise N and the offset are removed from the offset removing unit 310.

Specifically, the correlated double sampling unit 320 reduces the noise (N) provided from the offset removal unit 310 through two sampling times, and the noise (N-2S) sampled twice by the second amplification unit 380, N-2S') can be provided. In addition, the correlated double sampling unit 320 increases the offset-removed driving signal (OS-DS) provided from the offset removal unit 310 through two sampling times, and is then sampled twice by the second amplifier 380. Signals (OC-DS-2S, OC-DS-2S') can be provided.

The second amplifying unit 380 receives the noise sampled twice (N-2S, N-2S') and the driving signal sampled twice (OC-DS-2S, OC-DS-2S') and buffers it. ) And low pass filtering. In addition, the second amplification unit 380 includes the buffered and low-pass filtered noise sampled twice (N-2S, N-2S') and the buffered and low-pass filtered noise sampled twice (OC-DS-2S, OC-DS-2S') may be provided to the analog-digital conversion unit 390.

Here, the second amplification unit 380 may include, for example, a sample and hold amplifier, but is not limited thereto.

The analog-to-digital converter 390 includes the buffered and low-pass filtered noise sampled twice (N-2S, N-2S') and the buffered and low-pass filtered noise sampled twice (OC-DS-2S, OC-DS-2S') may be subjected to a third sampling.

Specifically, the analog-to-digital conversion unit 390 includes the second sampled noise (N-2S, N-2S') buffered and low-pass filtered from the second amplifying unit 380 and the second buffered and low-pass filtered. A third sampling may be performed by receiving the sampled driving signals OC-DS-2S and OC-DS-2S', and the sum of the third sampled noise and the driving signal may be converted into a digital signal.

Here, the third sampled noise is the difference between the second sampled noises N-2S and N-2S', and the third sampled driving signal is the second sampled driving signals OC-DS-2S, OC-DS-2S') may be the difference between.

Referring to FIG. 9, the correlated double sampling unit 320 may include a first amplifying unit 325 and a sampling unit 330.

The first amplification unit 325 performs the same role as the first amplification unit 150 of FIG. 2, and a description thereof will be omitted.

The sampling unit 330 may receive a first sampled noise N-1S and a first sampled driving signal OC-DS-1S from the first amplifying unit 325 and alternately perform a plurality of sampling. have.

Specifically, the sampling unit 330 receives the first sampled noise N-1S from the first amplification unit 325 and alternately performs second and second' sampling, and the second and second' sampling The generated noise N-2S' may be provided to the second amplifying unit 380.

In addition, the sampling unit 330 receives the first sampled driving signal OC-DS-1S from the first amplification unit 325 and alternately performs second and second ′ sampling, and performs second and second ′ sampling. The sampled driving signal OC-DS-2S' may be provided to the second amplifier 380.

Referring to FIG. 10, the sampling unit 330 may include a first sub-sampling unit 340 and a second sub-sampling unit 350. However, unlike the sampling unit 160 of FIG. 4, the sampling unit 330 does not include the third sub-sampling unit 175 of FIG. 4.

Here, the first sub-sampling unit 340 and the second sub-sampling unit 350 each output (a second sampled noise (N-2S) and a second sampled driving signal (OC-DS-2S), Except that the second'sampled noise (N-2S') and the second' sampled driving signal (OC-DS-2S') are provided to the second amplifier 380, the first It may perform the same role as the sub-sampling unit 340 and the second sub-sampling unit 350.

Referring to FIG. 11, a circuit diagram of an offset removing unit 310, a first amplifying unit 325, a sampling unit 330, and a second amplifying unit 380 is shown.

Unlike the above-described embodiment (semiconductor device 100), since the second amplifying unit 380 is added between the sampling unit 330 and the analog-digital conversion unit 390, the first sub-sampling unit 340 The output terminal and the output terminal of the second sub-sampling unit 350 may be connected to the second amplifier 380 while being separated from each other.

In addition, since the second amplifying unit 380 is also a differential structure, the second sampled noise N-2S and the second sampled driving signal OC-DS- provided from the first sub-sampling unit 340 are 2S), the second'sampled noise (N-2S') and the second' sampled driving signal (OC-DS-2S') provided from the second sub-sampling unit 350 are separated and buffered and low. Pass filtering can be performed.

The semiconductor device 300 according to another exemplary embodiment of the present invention may reduce not only low-frequency noise but also noise N provided through an external input through CDS over three orders of magnitude, and amplify the driving signal DS. In addition, unlike the semiconductor device 100, the semiconductor device 300 may perform additional buffering and low-pass filtering by including the second amplifying unit 380 (ie, a sample and hold amplifying unit), thereby preventing noise. You can further improve your immunity. Additionally, the semiconductor device 300 may remove the offset of the driving signal DS through the offset removing unit 120 so that the driving signal DS receives a larger gain value. In addition, as the driving signal DS is provided with a larger gain value, the operation range of the semiconductor device 300 itself may be widened.

Hereinafter, a semiconductor system according to an embodiment of the present invention will be described with reference to FIG. 12. Contents overlapping with the above-described embodiments will be omitted.

12 is a block diagram illustrating a semiconductor system according to an embodiment of the present invention.

Referring to FIG. 12, a semiconductor system 500 according to an embodiment of the present invention may include a panel 510 and a control chip 520.

Specifically, the panel 510 may receive an external input. In addition, the panel 510 may receive the driving signal DS from the logic module 550 of the control chip 520.

Here, the panel 510 may include, for example, a touch screen panel, and more specifically, may include a capacitive touch screen panel, but is not limited thereto. In addition, the external input may include, for example, a touch input, and more specifically, may include a touch input by a user's hand or an input by a stylus pen, but is not limited thereto.

The control chip 520 includes a logic module 550 that provides a driving signal DS to the panel 510, a panel control module 530 that reduces noise provided through an external input, and the panel control module 530. It may include an analog-digital converter 540 for converting the output signal FS into a digital signal.

Here, the logic module 550 may include, for example, an offset table, a flash memory, an interface logic, and a micro controller unit (MCU).

In addition, the panel control module 530 may include the same configuration as the offset removing unit 310, the correlation double sampling unit 320, and the second amplifying unit 380 of FIG. 8. That is, the panel control module 530 resets the offset removal unit (not shown) for removing the offset of the driving signal DS provided from the panel 510 and resets every half cycle of the driving signal DS. DS) and a first amplification unit (not shown) that first samples the noise (N) provided through an external input through a reset, and a sampling that alternately samples the first sampled noise and the driving signal second and second' A sub (not shown) and second and second' sampled noise and driving signals are received, buffering and low-pass filtering are performed, and the buffered and low-pass filtered second and second' sampled noise and driving signals are It may include a second amplifying unit (not shown) provided to the analog-to-digital conversion unit 540.

The analog-to-digital conversion unit 540 third samples the output signal FS (that is, the second and second'sampled noise and driving signal) of the panel control module 530 and receives the third sampled output signal. It can be converted to a digital signal. That is, the analog-to-digital conversion unit 540 may perform the same role as the analog-to-digital conversion unit 390 of FIG. 8.

13 to 15 are exemplary electronic systems to which a semiconductor device according to some embodiments of the present invention can be applied.

FIG. 13 is a diagram illustrating a tablet PC 1200, FIG. 14 is a diagram illustrating a notebook 1300, and FIG. 15 is a diagram illustrating a smartphone 1400. The semiconductor devices 1 and 2 according to some embodiments of the present invention may be used for the tablet PC 1200, notebook 1300, smart phone 1400, and the like.

In addition, it is obvious to those skilled in the art that the semiconductor devices 100 and 300 according to some embodiments of the present invention can be applied to other integrated circuit devices not illustrated. That is, in the above, only the tablet PC 1200, the notebook 1300, and the smartphone 1400 have been recited as examples of the electronic system according to the present embodiment, but the example of the electronic system according to the present embodiment is not limited thereto. In some embodiments of the present invention, the electronic system includes a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, and a wireless phone. , Mobile phone, e-book, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3D receiver (3-dimensional television), digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder ), digital video player, or the like.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects.

10: panel 120: offset removal unit
140: correlated double sampling unit 150: first amplification unit
160: sampling unit 165: first sub-sampling unit
170: second sub-sampling unit 175: third sub-sampling unit
200: analog-digital conversion unit

Claims (10)

An amplifying unit receiving an input signal and a driving signal, resetting at a specific period of the driving signal, and first sampling the input signal to generate a first sampled input signal; And
The first sampled input signal is second sampled to generate a second sampled input signal, the first sampled input signal is third sampled to generate a third sampled input signal, and the second sampled input A sampling unit for generating a fourth sampled input signal by fourth sampling the signal and the third sampled input signal,
The first sampled input signal is a difference between a first reset point and a first input signal that is a change in the input signal between the first reset point and a second continuous reset point, and the second reset point and the second reset point. The difference in the second input signal, which is a change in the input signal between the 2 reset point and the continuous third reset point, and the change in the input signal between the third reset point and the third reset point and a successive fourth reset point Including the difference of the third input signal, which is the minute,
The second sampled input signal is a difference between the first input signal and the second input signal,
The third sampled input signal is a difference between a difference between the second input signal and a difference between the third input signal,
The fourth sampled input signal is a difference between the second sampled input signal and a third sampled input signal. The method of claim 1,
The amplification unit,
A first operational amplifier,
A first resistor connected between the input and output terminals of the first operational amplifier,
A first capacitor connected in parallel with the first resistor,
A semiconductor device comprising a first reset switch connected in parallel with the first capacitor. The method of claim 1,
The specific period of the driving signal is a half period of the driving signal. The method of claim 1,
The semiconductor device further comprising an offset removing unit configured to remove an offset of the driving signal by receiving the driving signal. The method of claim 1,
The sampling unit,
A first sub-sampling unit that performs the second sampling,
A second sub-sampling unit that performs the third sampling,
A semiconductor device including a third sub-sampling unit that performs the fourth sampling. The method of claim 5,
The first sub-sampling unit,
A second capacitor connected to the amplification unit,
A first switch connected to the second capacitor and receiving a common mode voltage,
A second switch connected between the second capacitor and the third sub-sampling unit,
A first integrator connected between the second switch and the third sub-sampling unit,
And a second reset switch connected in parallel with the first integrator. The method of claim 6,
The second sub-sampling unit,
A third capacitor connected to the amplification unit,
A third switch connected to the third capacitor and receiving a common mode voltage,
A fourth switch connected between the third capacitor and the third sub-sampling unit,
A second integrator connected between the fourth switch and the third sub-sampling unit,
And a third reset switch connected in parallel with the second integrator. The method of claim 1,
The amplification unit includes a first operational amplifier receiving a common mode voltage,
The sampling unit includes a first sub-sampling unit for performing the second sampling, a second sub-sampling unit for performing the third sampling, and a third sub-sampling unit for performing the fourth sampling,
The first sub-sampling unit includes a second capacitor connected to the amplifying unit, a second switch connected between the second capacitor and the third sub-sampling unit, and a second switch connected between the second switch and the third sub-sampling unit. 1 A semiconductor device comprising an integrator. An offset removal unit receiving an input signal and a driving signal and removing an offset of the driving signal;
A correlated double sampling unit for reducing the input signal through sampling; And
A sample and hold amplification unit receiving the output of the correlated double sampling unit and performing buffering and low pass filtering,
The correlated double sampling unit resets at each specific period of the driving signal from which the offset is removed, first samples the input signal to generate a first sampled input signal, and receives the first sampled input signal. A second sampled input signal is generated, the first sampled input signal is third sampled to generate a third sampled input signal, the second sampled input signal and a third sampled input signal Provided to the sample and hold amplification unit,
The first sampled input signal is a difference between a first reset point and a first input signal that is a change in the input signal between the first reset point and a second continuous reset point, and the second reset point and the second reset point. The difference in the second input signal, which is a change in the input signal between the 2 reset point and the continuous third reset point, and the change in the input signal between the third reset point and the third reset point and a successive fourth reset point Including the difference of the third input signal, which is the minute,
The second sampled input signal is a difference between a difference between the first input signal and a difference between the second input signal,
The third sampled input signal is a difference between a difference between the second input signal and a difference between the third input signal. A panel receiving an external input; And
Including a control chip for controlling the panel,
The control chip,
A logic module providing a driving signal to the panel,
A panel control module for reducing noise provided through the external input,
Including an analog-digital conversion unit for converting the output signal of the panel control module into a digital signal,
The panel control module,
An offset removing unit that removes an offset of the driving signal provided from the panel,
A first amplification unit that resets every half cycle of the driving signal and first samples an input signal provided through the external input through the reset,
The first sampled input signal is second sampled to generate a second sampled input signal, the first sampled input signal is third sampled to generate a third sampled input signal, and the second sampled input A sampling unit for generating a fourth sampled input signal by fourth sampling the signal and the third sampled input signal;
The second sampled input signal and the third sampled input signal are received, buffering and low pass filtering are performed, and the buffered and low pass filtered second sampled input signal and third sampled input signal are converted into the analog- Including a second amplification unit provided to the digital conversion unit,
The first sampled input signal is a difference between a first reset point and a first input signal that is a change in the input signal between the first reset point and a second continuous reset point, and the second reset point and the second reset point. The difference in the second input signal, which is a change in the input signal between the 2 reset point and the continuous third reset point, and the change in the input signal between the third reset point and the third reset point and a successive fourth reset point Including the difference of the third input signal, which is the minute,
The second sampled input signal is a difference between a difference between the first input signal and a difference between the second input signal,
The third sampled input signal is a difference between a difference between the second input signal and a difference between the third input signal,
The fourth sampled input signal is a difference between the second sampled input signal and the third sampled input signal.

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