JPH06303138A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH06303138A
JPH06303138A JP9009293A JP9009293A JPH06303138A JP H06303138 A JPH06303138 A JP H06303138A JP 9009293 A JP9009293 A JP 9009293A JP 9009293 A JP9009293 A JP 9009293A JP H06303138 A JPH06303138 A JP H06303138A
Authority
JP
Japan
Prior art keywords
terminal
input
resistor
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9009293A
Other languages
Japanese (ja)
Inventor
Chuichi Watanabe
忠一 渡邉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9009293A priority Critical patent/JPH06303138A/en
Publication of JPH06303138A publication Critical patent/JPH06303138A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To obtain a changeover device selecting one input signal or a difference between two input signals for the A/D converter and selecting an input voltage range by providing an input buffer circuit whose gain and an amplifier circuit are selected externally to the A/D converter. CONSTITUTION:When terminals 11, 12 are connected externally, an input buffer circuit 1 acts as an inverting amplifier circuit using an operational amplifier 7 and when terminals 13, 14 are disconnected, a gain of the circuit 1 is set to be 1. On the other hand, when the terminals 13, 14 are connected, the gain of the circuit 1 is set to be 2. When the terminals 11, 12 are disconnected and the terminals 13, 14 are connected externally, the circuit 1 acts as a differential amplifier circuit employing the operational amplifier 7 and its gain is set to be 1 and a signal being the subtraction of the input signal to the terminal 11 from the input signal to the terminal 10 is an input signal to the A/D converter. Thus, the input voltage range and the input signal are switched.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は入力信号と入力信号の
電圧範囲を変えることのできるA/D変換装置に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter capable of changing an input signal and a voltage range of the input signal.

【0002】[0002]

【従来の技術】図2は従来の入力電圧範囲を切り換えら
れるA/D変換装置の構成図である。図において、15
は入力バッファ回路、16は第1の抵抗器、17は第2
の抵抗器、18は第3の抵抗器、19は第4の抵抗器、
20はオペアンプであり、21はS&H回路、22はA
/D変換回路、23は第1の入力端子、24は第2の入
力端子である。
2. Description of the Related Art FIG. 2 is a block diagram of a conventional A / D converter capable of switching an input voltage range. In the figure, 15
Is an input buffer circuit, 16 is a first resistor, 17 is a second resistor
Resistor, 18 is a third resistor, 19 is a fourth resistor,
20 is an operational amplifier, 21 is an S & H circuit, and 22 is A
A / D conversion circuit, 23 is a first input terminal, and 24 is a second input terminal.

【0003】従来のA/D変換装置では、第1の抵抗器
16の抵抗値をR1、第2の抵抗器17の抵抗値をR
2、第3の抵抗器18の抵抗値をR3とし、第1の入力
端子23に信号を入れた場合、入力バッファ回路15の
ゲインはR1/(R2+R3)となり、第2の入力端子
24に信号を入れた場合、入力バッファ回路15のゲイ
ンはR1/R3となる。
In the conventional A / D converter, the resistance value of the first resistor 16 is R1, and the resistance value of the second resistor 17 is R.
2, when the resistance value of the third resistor 18 is R3 and a signal is input to the first input terminal 23, the gain of the input buffer circuit 15 is R1 / (R2 + R3), and the signal is input to the second input terminal 24. When is input, the gain of the input buffer circuit 15 becomes R1 / R3.

【0004】第2の入力端子23への入力電圧範囲を−
A〜Aとすると第1の入力端子24への入力電圧範囲は
−A×R3/(R2+R3)〜A×R3/(R2+R
3)となる。このように入力端子を換えて入力バッファ
回路のゲインを切り換えることで入力電圧範囲を切り換
えていた。
The input voltage range to the second input terminal 23 is
Assuming A to A, the input voltage range to the first input terminal 24 is -A * R3 / (R2 + R3) to A * R3 / (R2 + R).
3). In this way, the input voltage range is switched by switching the input terminal and switching the gain of the input buffer circuit.

【0005】[0005]

【発明が解決しようとする課題】上記のようなA/D変
換装置では入力電圧範囲の切り換えはできたが、入力信
号はグランドを基準とした一つの入力信号しか扱うこと
ができなかった。この発明は入力電圧範囲が切り換えら
れ、入力信号をグランドを基準とした一つの入力信号を
使用するものと二つの入力信号の差を入力信号に使用す
るものとに切り換えられるA/D変換器を得ることを目
的とし、さらに、この入力信号と入力電圧範囲が異なる
8個以下の信号を同時にA/D変換できるA/D変換装
置を得ることを目的とする。
In the above A / D converter, the input voltage range can be switched, but the input signal can handle only one input signal with reference to the ground. The present invention relates to an A / D converter whose input voltage range is switched and which is switched between one that uses one input signal with respect to ground as an input signal and one that uses the difference between two input signals as an input signal. Further, it is an object of the present invention to obtain an A / D converter capable of simultaneously A / D converting the input signal and eight or less signals having different input voltage ranges.

【0006】[0006]

【課題を解決するための手段】この発明に係るA/D変
換器は、ゲインと増幅回路を外部で切り換えられる入力
バッファ回路をもたせたものである。
The A / D converter according to the present invention is provided with an input buffer circuit whose gain and amplifier circuits can be switched externally.

【0007】またこの入力バッファ回路とS&H回路を
8個と、信号を切り換えるマルチプレクサ回路と、8個
の変換信号を記憶するレジスタを持たせる。
Further, this input buffer circuit, eight S & H circuits, a multiplexer circuit for switching signals, and a register for storing eight converted signals are provided.

【0008】[0008]

【作用】入力バッファ回路のゲインを外部で切り換える
ことで入力電圧範囲が切り換えられ、入力バッファ回路
の増幅回路を外部で切り換えることで入力信号が切り換
えられる。
The input voltage range is switched by externally switching the gain of the input buffer circuit, and the input signal is switched by externally switching the amplifier circuit of the input buffer circuit.

【0009】また入力バッファ回路とS&H回路を8個
と、マルチプレクサ回路を持たせることにより、入力電
圧範囲と入力信号の異なる8個以下の信号を同時にA/
D変換する。
Further, by providing an input buffer circuit, eight S & H circuits, and a multiplexer circuit, eight or less signals having different input voltage ranges and input signals can be A / S simultaneously.
D-convert.

【0010】[0010]

【実施例】実施例1.図1に、この発明による実施例の
構成図を示す。図において、1は入力バッファ回路、2
は第1の抵抗器、3は第2の抵抗器、4は第3の抵抗
器、5は第4の抵抗器、6は第5の抵抗器で抵抗値は全
てR、7はオペアンプ、8はS&H回路、9はA/D変
換回路、10は第1の端子、11は第2の入力端子、1
2は第3の端子、13は第4の端子、14は第5の端子
である。
EXAMPLES Example 1. FIG. 1 shows a block diagram of an embodiment according to the present invention. In the figure, 1 is an input buffer circuit, 2
Is a first resistor, 3 is a second resistor, 4 is a third resistor, 5 is a fourth resistor, 6 is a fifth resistor and all resistance values are R, 7 is an operational amplifier, 8 Is an S & H circuit, 9 is an A / D conversion circuit, 10 is a first terminal, 11 is a second input terminal, 1
2 is a third terminal, 13 is a fourth terminal, and 14 is a fifth terminal.

【0011】図1において第2の端子11と第3の端子
12を外部で接続すると、入力バッファ回路1はオペア
ンプ7による反転増幅回路となり、第4の端子13と第
5の端子14を接続するか離すかにより、入力バッファ
回路1のゲインが変わる。第4の端子13と第5の端子
14を離した場合、入力バッファ回路1のゲインは1と
なり、第4の端子13と第5の端子14を接続した場
合、入力バッファ回路1のゲインは2となる。
In FIG. 1, when the second terminal 11 and the third terminal 12 are externally connected, the input buffer circuit 1 becomes an inverting amplifier circuit by the operational amplifier 7, and the fourth terminal 13 and the fifth terminal 14 are connected. The gain of the input buffer circuit 1 changes depending on whether it is released or not. When the fourth terminal 13 and the fifth terminal 14 are separated, the gain of the input buffer circuit 1 is 1, and when the fourth terminal 13 and the fifth terminal 14 are connected, the gain of the input buffer circuit 1 is 2 Becomes

【0012】第4の端子13と第5の端子14を離した
場合の入力端子10への入力電圧範囲を−A〜Aとする
と、第4の端子13と第5の端子14を接続した場合の
入力電圧範囲は−2×A〜2×Aとなる。
When the input voltage range to the input terminal 10 when the fourth terminal 13 and the fifth terminal 14 are separated is -A to A, when the fourth terminal 13 and the fifth terminal 14 are connected to each other. The input voltage range of is -2 × A to 2 × A.

【0013】また第2の端子11と第3の端子12を離
し、第4の端子13と第5の端子14を外部で接続する
と入力バッファ回路1はオペアンプ7による作動増幅回
路でゲインは1となり、第1の端子10への入力信号か
ら第2の端子11への入力信号を引いたものがこのA/
D変換器の入力信号となる。上記の通り端子を外部で接
続することで、入力電圧範囲と入力信号を切り換えられ
る。
When the second terminal 11 and the third terminal 12 are separated and the fourth terminal 13 and the fifth terminal 14 are externally connected, the input buffer circuit 1 is an operational amplifier circuit by the operational amplifier 7 and the gain is 1. , Which is obtained by subtracting the input signal to the second terminal 11 from the input signal to the first terminal 10 is A /
It becomes the input signal of the D converter. By connecting the terminals externally as described above, the input voltage range and the input signal can be switched.

【0014】実施例2.図3は図1の入力バッファ1の
数を増やしたもので、25は入力バッファ回路、26は
S&H回路、27はマルチプレクサ、28はA/D変換
器、29レジスタである。
Example 2. FIG. 3 is a diagram in which the number of the input buffers 1 in FIG. 1 is increased. 25 is an input buffer circuit, 26 is an S & H circuit, 27 is a multiplexer, 28 is an A / D converter, and 29 registers.

【0015】図3において電圧範囲と入力信号の異なる
8個の信号が入力バッファ回路25を通りS&H回路2
6にはいる。S&H回路26は入力信号を全て同時にサ
ンプリングとホールドを行う。この出力をマルチプレク
サ27に入れ時分割に出力しA/D変換させる。レジス
タは8個の変換された出力データを記憶し、出力する。
このように上記入力バッファ回路を8個備えることによ
り、入力電圧範囲と入力信号の異なる8個以下の信号を
同時にA/D変換する。
In FIG. 3, eight signals having different voltage ranges and input signals pass through the input buffer circuit 25 and the S & H circuit 2
Enter 6 The S & H circuit 26 simultaneously samples and holds all input signals. This output is input to the multiplexer 27 and output in a time division manner for A / D conversion. The register stores and outputs the eight converted output data.
By providing eight input buffer circuits as described above, eight or less signals having different input voltage ranges and input signals are simultaneously A / D converted.

【0016】[0016]

【発明の効果】この発明は上記の通り、入力バッファ回
路に端子を設け、入力電圧範囲を2種類から選択でき、
入力信号を1つの入力信号を使用するものと2つの入力
信号の差を使用するものとに選択できるA/D変換装置
を得る。
As described above, according to the present invention, the input buffer circuit is provided with the terminals, and the input voltage range can be selected from two types.
(EN) An A / D conversion device capable of selecting an input signal using one input signal and one using a difference between two input signals.

【0017】また、上記入力バッファ回路とS&H回路
を8個と、レジスタを設けることにより入力電圧範囲と
入力方式の異なる8個以下の信号を同時にA/D変換で
きるA/D変換装置を得る。
Further, by providing eight input buffer circuits and eight S & H circuits and a register, an A / D converter capable of simultaneously A / D converting eight or less signals having different input voltage ranges and input methods is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例1の構成を示した図である。FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention.

【図2】従来の入力電圧範囲を変えることができるA/
D変換装置の構成を示した図である。
FIG. 2 A / A that can change the conventional input voltage range
It is the figure which showed the structure of the D converter.

【図3】この発明の実施例2の構成を示した図である。FIG. 3 is a diagram showing a configuration of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 入力バッファ回路 2 第1の抵抗器 3 第2の抵抗器 4 第3の抵抗器 5 第4の抵抗器 6 第5の抵抗器 8 S&H回路 9 A/D変換回路 10 第1の端子 11 第2の端子 12 第3の端子 13 第4の端子 14 第5の端子 26 マルチプレクサ 28 レジスタ 1 Input buffer circuit 2 1st resistor 3 2nd resistor 4 3rd resistor 5 4th resistor 6 5th resistor 8 S & H circuit 9 A / D conversion circuit 10 1st terminal 11 1st 2 terminal 12 3rd terminal 13 4th terminal 14 5th terminal 26 multiplexer 28 register

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 入力信号を入れるための第1の端子と、
その後段に信号を受けるための第1の抵抗器と、前記第
1の端子から入力される信号との差をとるための信号を
入力する第2の端子と、その後段に信号を受ける第2の
抵抗器と、前記第1の端子と第2の端子からの信号のグ
ランドを決める第3の端子と、前記第2の端子と第3の
端子とのオフセット電圧を解消するために第3の端子と
第2の抵抗器の間に設けられた第3の抵抗器と、前記第
1の端子と第2の端子からの信号を増幅させるために第
1の抵抗器の後段に設けられた第4の抵抗器及び第5の
抵抗器と、その増幅度を決定するために第4の抵抗器の
後から外部に出す第4の端子と、前記第4の端子と同様
に増幅度を決定するために第5の抵抗器の後から外部に
出す第5の端子を備えたことを特徴とする入力バッファ
回路と、その出力にサンプリングとホールドを行うS&
H(Sample & Hold)回路と、A/D変換
回路を持つA/D変換装置。
1. A first terminal for receiving an input signal,
A first resistor for receiving a signal in the subsequent stage, a second terminal for inputting a signal for taking the difference between the signal input from the first terminal, and a second terminal for receiving the signal in the subsequent stage Resistor, a third terminal for determining the ground of signals from the first terminal and the second terminal, and a third terminal for eliminating the offset voltage between the second terminal and the third terminal. A third resistor provided between the terminal and the second resistor, and a third resistor provided after the first resistor for amplifying signals from the first terminal and the second terminal. The fourth resistor and the fifth resistor, the fourth terminal which is output to the outside after the fourth resistor to determine the amplification degree, and the amplification degree are determined in the same manner as the fourth terminal. An input buffer circuit having a fifth terminal for outputting to the outside after the fifth resistor, and its output S to perform the sampling and hold &
An A / D conversion device having an H (Sample & Hold) circuit and an A / D conversion circuit.
【請求項2】 入力電圧範囲と入力信号の異なる信号を
8個まで受けるための前記入力バッファ回路を8個と、
その8個以下の信号を同時にA/D変換するためのS&
H回路を8個と、マルチプレクサ回路と、変換データを
記憶するレジスタを持つ請求項1記載のA/D変換装
置。
2. The eight input buffer circuits for receiving up to eight signals having different input voltage ranges and input signals,
S & for simultaneous A / D conversion of 8 or less signals
The A / D conversion device according to claim 1, comprising eight H circuits, a multiplexer circuit, and a register for storing conversion data.
JP9009293A 1993-04-16 1993-04-16 A/d converter Pending JPH06303138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9009293A JPH06303138A (en) 1993-04-16 1993-04-16 A/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9009293A JPH06303138A (en) 1993-04-16 1993-04-16 A/d converter

Publications (1)

Publication Number Publication Date
JPH06303138A true JPH06303138A (en) 1994-10-28

Family

ID=13988879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9009293A Pending JPH06303138A (en) 1993-04-16 1993-04-16 A/d converter

Country Status (1)

Country Link
JP (1) JPH06303138A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020053752A (en) * 2018-09-25 2020-04-02 ローム株式会社 Analog/digital converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020053752A (en) * 2018-09-25 2020-04-02 ローム株式会社 Analog/digital converter

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